Experimental Results and Comparisons

To validate the look-ahead constraint checking and candidate generation techniques proposed in Section 4.3 and Section 4.4, we compared two different flows on QB-trees: (1) without the techniques and (2) with the techniques. Table 5.2 compares the placement results of these two flows based on the ota design, where

“# of Sym. Groups” gives the number of symmetry groups and the number of modules in each group, “QB-tree w/o LCC” and “QB-tree w/ LCC” represent our proposed flow without and with the look-ahead constraint checking and candidate generation techniques, respectively. The results show that the flow with the look-ahead constraint checking and candidate generation techniques achieve an averagely 20% runtime reduction, 5% dead space rate reduction, and 4% wirelength reduc-tion, which validates the two proposed techniques. Although the flow with the two techniques has two additional techniques which might consume more runtime, yet they effectively help avoid infeasible solutions and reduce the convergence time of the simulated annealing scheme.

To show the completeness and efficiencies of our placement system, we evalu-ated our work in handling the aforementioned constraints and compared the results

considering the constraints handled by both works. As shown in Table 5.3, our QB-trees can achieve smaller dead space rate while consuming less runtime on average.

Second, we compared our QB-trees with [22]². For the common constraints handled by both CB-trees and QB-trees, as shown in Table 5.4, our proposed QB-trees can achieve an averagely 30% runtime reduction, 40% dead space rate reduction, and 11% wirelength reduction compared with the previous work based on design ota;

besides, for designs biasynth 2p4g and lnamixbias 2p4g, we can achieve an averagely 23% runtime reduction and 47% dead space rate reduction. For all the constraints listed in Section 1.1, as shown in Table 5.5, our proposed QB-trees can achieve an averagely 2% runtime reduction, 30% dead space rate reduction, and 7% wirelength reduction compared with the previous work based on design ota; besides, for de-signs biasynth 2p4g and lnamixbias 2p4g, we can achieve an averagely 28% runtime reduction and 90% dead space rate reduction. Figures 5.1 and 5.2 show the result-ing layouts of designs biasynth 2p4g and lnamixbias 2p4g with multiple constraints, respectively.

2

Comparisonsofdeadspaces(DS)(%),wirelength(WL)(103 µm),andCPUtimes(s)forQB-trees tflows. CircuitsOtherQB-treew/oLCCQB-treew/LCC ConstraintsTimeDSWLTimeDSWL 1maxsep,2preplaced439.576.8329.175.5 1range,2preplaced499.676.6479.164.9 1close-to-boundary fixed-boundary ota1close-to-boundary769.974.3679.177.3 1maxsep fixed-boundary 1close-to-boundary879.481.0669.280.5 1range,1maxsep Comparisons1.21.051.041.001.001.00

Table5.3:Comparisonsofdeadspaces(DS)(%)andCPUtimes(s)forsequencepairwithdummynodes[21], basedoncommonconstraints. Circuits#of#ofSym.OtherSPwDQB-tree Mod.GroupsConstraintsTimeDSTimeDS data70b709+5+91preplaced,1maxsep607.1474.3 data70d7091preplaced,1maxsep565.9264.2 data100a1009+5+9+91preplaced,1maxsep2605.41273.5 data100c1004+9+91preplaced,1range1294.7834.8 1maxsep Comparison1.81.391.001.00

Comparisonsofdeadspaces(DS)(%),wirelength(WL)(103 µm),andCPUtimes(s)forCB-and oncommonconstraints. CircuitsOtherCB-treeQB-tree ConstraintsTimeDSWLTimeDSWL ota

1fixed-boundary,1minsep7112.970.1498.669.9 1preplaced8011.976.9709.163.6 1proximity,1boundary Comparisons1.301.401.111.001.001.00 th2p4g

2preplaced,9variant4512.5N/A4510.2N/A 2preplaced8011.8N/A6610.6N/A 1proximity,1minsep 2p4g

1preplaced,2proximity7822.9N/A5713.2N/A 1minsep,2boundary 1fixed-boundary,1boundary26917N/A1999.5N/A 1minsep,1proximity Comparisons1.231.47N/A1.001.00N/A

Table5.5:Comparisonsofdeadspaces(DS)(%),wirelength(WL)(103 µm),andCPUtimes(s)forCB-and QB-treesbasedonalltheaforementionedconstraints. CircuitsOtherCB-treeQB-tree ConstraintsTimeDSWLTimeDSWL 1preplaced,2range649.972.6709.165.2 ota1fixed-boundary6410.872.6577.170.7 1range,1close-to-boundary Comparisons1.021.301.071.001.001.00 2maxsep,2preplaced11216.3N/A11110.6N/A biasynth2p4g1preplaced,1boundary12615N/A9210.7N/A 1maxsep,1range lnamixbias2p4g

1fixed-boundary20923.7N/A1728.9N/A 3maxsep,1range 1preplaced,2boundary43718.2N/A2899.1N/A 2maxsep,1range Comparisons1.281.90N/A1.001.00N/A

m1

Figure 5.1: The resulting layout of biasynth 2p4g with three symmetry groups (yel-low), two preplaced modules (indigo), two boundary modules (red), two maximum separation module pairs (purple and blue).

m110

Figure 5.2: The resulting layout of lnamixbias 2p4g (rotated by 90^◦ clockwise) with five symmetry groups (yellow), one preplaced module (indigo), four boundary mod-ules (red), two maximum separation module pairs (purple and blue), one module with range constraint (pink).

Conclusions and Future Work

In this thesis, we have proposed a novel analog placement algorithm based on the QB-tree representation. With embedded geometrical information, the QB-tree rep-resentation can handle general geometrical constraints effectively and completely while maintaining the advantages of B*-trees, achieving linear, lower-bound time complexity of module packing and constraint handling for the general geometrical constraints. Experimental results have shown that our algorithm is superior to ex-isting analog placement works in solution quality, running time, and completeness of constraint handling for real industry designs.

Some future research directions are provided as follows:

• Development of an analog placer considering buffer block planning based on the proposed QB-tree. In addition to all the constraints considered in this thesis, global interconnect planning and prediction in deep submicron (DSM) designs have become the dominant factor in determining the overall circuit performance and complexity. Among all the optimization techniques, such as spacing, wire sizing, and topology generation (please refer to [10] and [12] for a tutorial), buffer insertion are commonly adopted to break long interconnect to

functional modules and the rest segments are buffer blocks. Because buffer blocks can not be placed on any hard intellectual property (IP) modules, our QB-tree might be able to generate some candidate feasible regions for buffer blocks based on the tree structure, as shown in Figure 6.1(b).

• Development of a placer for mixed-signal design considering noise reduction.

Contemporary CMOS ASICs and system-on-a-chip designs often contain both analog and digital sections. Inevitable noise problems often occur when com-bining the two sections into a mixed-signal IC. In order to take the noise into consideration, the layout engineers need to integrate noise-related design knowledge into the floorplanning/placement stage. As shown in Figure 6.2, which is one of the possible layout configuration considering noise reduction obtained from [2]. For example, constantly clocked digital circuitry usually is the major source of dynamic noise; as a result, it is undesirable to place those modules closely to some sensitive analog modules. In order to achieve as small layout size as possible while maintaining acceptable noise property, mixed-signal floorplanning/placement problem is crucial and challenging.

(a)

(b) p₂ p₁

: candidate feasible regions

: functional modules : buffer blocks

: preplaced modules

Figure 6.1: Future work considering buffer block planning based on our proposed QB-trees. (a) The resulting layout of the MCNC circuit xerox obtained from [11], the ten big modules are circuit functional modules and the rest segments are buffer blocks. (b) Candidate feasible regions for buffer blocks which might be able to

Small-amplitude Analog Circuits Large-swing Analog Circuits

Guard Bar – Analog Power Substrate Contacts Guard Bar – Digital Power

Static Digital Circuits Guard Bar – Digital Power

Active Digital Circuits Noisy

Quiet

Power/

ground split

Analog Digital

Figure 6.2: Future work considering noise reduction. The layout configuration is obtained and suggested by [2], where analog and digital parts are separated and the layout follows an order based on the noise properties of different circuits.

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[1] I.-P. Wu, H.-C. Ou, and Y.-W. Chang, “QB-Trees: towards an optimal topolog-ical representation and its applications to analog layout designs,” in Proceedings of ACM/IEEE Design Automation Conference, June 2016.

[2] H.-C. Ou, K.-H. Tseng, J.-Y. Liu, I.-P. Wu, and Y.-W. Chang, “Layout-dependent-effects-aware analytical analog placement,” in Proceedings of ACM/IEEE Design Automation Conference, June 2015.

[3] H.-C. Ou, K.-H. Tseng, J.-Y. Liu, I.-P. Wu, and Y.-W. Chang, “Layout-dependent-effects-aware analytical analog placement,” to appear in IEEE Trans.

Computer-Aided Design of Integrated Circuits and Systems, 2016.