Chapter 2 Experimental Procedures
2.1 Fabrication of Thin Film Transistors
In this study, ZrZnO TFTs were fabricated on glass substrate coated with a 1000 Å sputtered MoW, which acts as gate electrodes for our TFT structure, and 3000 Å PECVD silicon nitride are deposited to be the gate insulator. Indium tin oxide (ITO) was deposited for the source and drain electrodes. TFTs which were fabricated for this study are bottom-gate structures with the ZrZnO active channel layer deposited at room temperature and room pressure by spin-on deposition. The rotation rate of the spin coater is 400rpm/15 seconds for step 1 and 2000rpm/20 seconds for step 2. After the ZrZnO film deposition, samples were taken to the hot
heated up to 300℃ and baked for 10 minutes. After baked thin films, they were crystallized at 350℃ for 1 hour in the furnace to improve the film quality. The device structure was shown in Fig2-1. The active channel was patterned using standard photolithography and wet etching.
There are many scientific or technical literatures which report HCl and HNO3 can etch ZrZnO film, however, we find the etching rate is too fast to avoid lateral etching. We use CH3COOH as buffer solution to reduce the etching rate. We mix HCl, HNO3, CH3COOH, and de-ionized water with the optimal volume rate. Finally, we fabricate the device with
“Standard Manufacturing Processes”.
The bottom-gate structure devices were fabricated by the Taiwan TFT LCD Association (TTLA). The ZrZnO thin film was fabricated by spin coater in the National Nano Device Laboratories (NDL).
2.2 Experimental Procedures
The transfer characteristics [log (IDS) - VGS] of ZrZnO TFT fabricated by the “Standard Manufacturing Processes” are shown in Fig2-2. We can see the device is normally-on and independent of gate bias and on current is about 10-6A. Fig2-3 shows the transfer characteristics of devices which were placed for 2 weeks, we observe that electric properties varied with time, and devices changed from depletion mode to enhanced mode. We need to understand the mechanism and find the method to solve it.
We consider that devices are placed in environment will suffer ambience effect, such as air. As we want to eliminate these behaviors and
obtain proper characteristics immediately, we add one more step annealing process and try to solve it. Thus, we define the first annealing step as “Curing” and the second one as “Annealing” to avoid being confused, and we also define the baking step as “Baking”.
2.2.1 Various Ambience and Treatment Time
In this section, we discuss the ambience and time of heat treatment.
Table2-3 shows experimental flow of various ambience and treatment
time in my experiment. First of all, we fabricate devices under various annealing ambience, such as oxygen, nitrogen, and vacuum. In order to compare performances resulting from the annealing step under various ambience and time, we fix the curing process at 350℃ for 1 hour under oxygen ambience in atmospheric anneal furnace but only change the annealing conditions. The ambience flow of oxygen and nitrogen are 10L, and the treatment time change from 10 minutes to 60 minutes. The annealing temperature are always fixed at 350℃. Atmospheric anneal furnace is used for oxygen and nitrogen ambience conditions, and backend vacuum annealing furnace for vacuum.2.2.2 Various Film Deposition Conditions of Active Layer
In this section, we discuss the film deposition with various conditions.
Table2-4 and Table2-5 show the various film deposition conditions of
active channel layer in my experiment. We divide the deposition conditions into three parts: numbers of active layers, period of bakingtime, and HMDS coating between dielectric and active layer interface.
Devices fabricated by optimal curing and annealing conditions still don’t have large on currents. From pre study, we know devices with double active layers have better electrical properties. Thus, after first ZrZnO film deposition, we repeat the same spin-on process and coat another layer on the first one. Each layer is baked at 300℃ for 60 minutes. However, after ZrZnO deposition, we apply only one curing process under oxygen and one annealing process under nitrogen. N&K measurement system is used to fit the thickness of ZrZnO films.
The first step is used to adjust the period of baking times. The films are baked on the hot plate for three different times: 10, 30, and 60 minutes. In general, on current will be increased through better crystallization; therefore, we extend the baking time to obtain better quality of films.
In order to have a good interface between the insulator and active layer, we coat HMDS on the interface between insulator and active layer to reduce interface defects, and obtain better subthresold swing (S.S).
HMDS is a purified hexamethyldisilazane with the chemical formula [(CH3)2Si]2NH. The product is used to augment the adhesion of photoresist on silicon and SiO2 surfaces. We compare electrical
characteristics of devices with or without HMDS coating.
Generally speaking, the physical characteristics of semiconductors are easily modified by the crystallite size and boundary effects. We compare the devices that were only deposited single active layer and baked for 60 minutes. By this experiment, the effect of double layer can be observed.
2.2.3 Various Treatment on Devices
Table 2-6 shows the experimental flow of various RTA treatment and
passivation process in my experiment. Rapid Thermal Annealing (RTA) can enhance the conductivity of the film, and further to improve device performances. Therefore, application of RTA under two different ambiences is placed between curing process and annealing one. The first RTA is under Ar ambience, the second one is under NH3 ambience. The pressure is at 10mtorr and rate of gas flow are 20sccm, and the process temperature is at 350℃ for 2 minutes. All treatment conditions are the same except ambiences.Besides, thin film transistors usually need the passivation layer to protect active channel layer from humidity, gas, and other factors from circumstance. Silicon oxide (SiOx), silicon nitride (SiNx) and PC403 are deposited to passivate the device. SiOx and SiNx are deposited by DC sputter. PC403 is coated by spin-on deposition, and the spin condition is 800rpm/18 seconds, followed by the exposure to UV light and post-bake at 220℃ for 1 hour.
2.2.4 Other Transparent Oxide Semiconductor TFTs
We now understand the optimal manufacturing processes of ZrZnO TFTs, however, devices performances are not good enough to compete with a-si TFTs. Fortunately, there are still many kinds of sol-gel derived materials. We replace the ZrZnO active channel layers by these materials, such as zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (IZO), and compare the electrical properties. ZrZnO and ZnO TFTs fabricating conditions are: double layers, with HMDS coating, baking for 60 minutes, curing for 60 minutes under oxygen, and annealing for 60minutes under nitrogen. ZTO and IZO TFTs fabricating conditions are: one layer, baking for 60 minutes, curing for 60 minutes under oxygen and annealing for 10 minutes under nitrogen or oxygen. We compare performances of each material and use material analysis to explain results.