Fabrication process flow

SOI MEMS technology and Inductively Coupled Plasma (ICP) deep silicon etching is a convenient way for fabricating high aspect ratio MEMS structures. Other difficulties in MEMS fabrication such as electrical insulation and device flatness can also be overcome easily by the SOI technology.

In order to reduce resistive loss and maintain high operation speed, the p-type device layer is heavily doped with resistivity less than 0.02 Ω-cm to minimize contact and parasitic resistance. The orientation of the device layer is <100>. The device thickness should be as large as possible within the ICP fabrication capability to define the finger structures. Thus, an SOI wafer with a 200 μm device layer is chosen.

The buried oxide layer is 2 μm thick for better electrical insulation. The handle layer is 400 μm thick for a firm structural support.

The fabrication process is illustrated in Fig. 3.1. Several steps are merged into one for clarity, whereas dicing and cleaning procedures are not shown.

Process parameters Step A: Wafer cleaning

Standard RCA wafer cleaning procedure was performed to remove organic contaminants from the wafer surface, then remove the thin oxide layer that may have built up, and finally remove any ionic or heavy metal contaminants. Notice that the RCA clean should be performed prior to any crucial steps, especially those involving high temperatures. Detailed parameters are given as below. Every step begins and ends with a 5 minute de-ionized water (DI water) rinse.

Step Process parameters Function

1 H2SO4 : H2O2 = 3 : 1 (10 min 85 °C) Organic removal 2 HF : H2O = 1 :100 (room temperature 30 seconds) Chemical oxide removal 3 NH4OH : H2O2 : H2O = 1 : 4 : 20 (10 min 85 °C) Particle removal 4 HCL : H2O2 : H2O = 1 : 1 : 6 (10 min 85 °C) Ionic removal 5 HF : H2O = 1 :100 (room temperature 30 seconds) Chemical oxide removal

Step B: Back side silicon oxide deposition

Silicon oxide with a thickness of 4.5 μm was deposited by a BR-2000LL plasma enhanced chemical vapor deposition (PECVD) system on the handle layer of the SOI wafer, as shown in Fig. 3.1 (a). The silicon oxide will be used as the hard mask for the 400 μm back side ICP etching process since it makes the subsequent double side photolithography more convenient. Heat dissipation during the ICP etching is also improved. The thickness was chosen according to the minimum selectivity of 100:1 between silicon and oxide in the ICP process. Deposition was divided into several 1.5 μm steps to prevent cracking of the oxide layer. Detailed parameters are given as below.

Description Process parameters Remarks

SiH4 flow rate 5 sccm BR-2000LL

N2O flow rate 90 sccm BR-2000LL

Process pressure 400 mTorr BR-2000LL

Process temperature 350 °C BR-2000LL

RF power 10 W BR-2000LL

Deposition rate 20 minutes resulting in 1.5 μm Repeat 3 times

Step C: Back side photolithography on silicon oxide

The back side photolithography was performed by a EV620 aligner on the deposited silicon oxide, as shown in Fig. 3.1 (b). AZ4620 was spin coated and patterned as a 7 μm thick photoresist mask. Detailed parameters are given as below.

Step Description Process parameters Remarks

1 Pre-bake 150 °C 30 minutes YES – 5

8 Development 75 seconds EDP1000

9 Rinse 90 seconds DI water

10 Hard bake 120 °C at least 1 hour Hot plate

Step D: Back side hard mask definition by wet etching

As shown in Fig. 3.1 (b), the 4.5 μm silicon oxide below the photoresist mask is etched by a NH4F:HF = 6:1 buffered oxide etchant (BOE) with an etch rate of roughly 1 μm per minute. The reason for using BOE isotropic etching instead of reactive ion etching (RIE) is the relatively low selectivity between silicon oxide and photoresist in the RIE process, which means an excessively thick photoresist mask is needed to etch

the thick oxide layer. The undercutting effect of wet etching is rather irrelevant to the back side pattern for partial substrate removal. The photoresist mask must be hard baked for at least 1 hour before immersing into the BOE solvent, or else peeling off of the photoresist mask may happen.

Step E: Front side photolithography

As shown in Fig. 3.1 (c), the front side photolithography is done by an EV620 double side aligner to define the photoresist mask for the subsequent ICP etching of the device layer. This is the main process to define the device structure. Parameters have been carefully tuned to produce all patterns correctly, especially the finger bump structures. The minimum selectivity of ICP etching between silicon and AZ4620 photoresist is 40:1. Thus, the photoresist thickness is chosen as 5 μm. It should not be too thick; otherwise it becomes difficult to produce small line width structures. Hard baking should be as long as possible in order for the photoresist to withstand the ICP process. Detailed parameters are given as below.

Step Description Process parameters Remarks

1 Pre-bake 150 °C 30 minutes YES – 5

8 Development 55 seconds EDP1000

9 Rinse 90 seconds DI water

10 Hard bake 120 °C at least 1 hour Hot plate

Step F: Front side deep silicon etching

The deep silicon etching of the device layer is performed by using a STS MESC multiplex ICP reactor with the standard Bosch process, as shown in Fig. 3.1 (d).

Additional guarding structures are used to reduce the influence of non-ideal etching effects, as discussed later. The averaged etch rate is roughly 2.2 μm per minute. Front side ICP etching is done on the wafer level. It provides a better etching profile and a more uniform etch rate due to the better heat dissipation. Detailed parameters are given as below.

Description Etch phase parameters Passivation phase parameters

Time per cycle 11.5 seconds 7.0 seconds

SF6 flow rate 130 sccm 0 sccm

Helium back side pressure = 10 Torr Maximum helium leak up rate = 20 mTorr/min Etch rate 0.6-0.7 μm per cycle depending on pattern

Step G: Silicon nitride deposition

As shown in Fig. 3.1 (e), low stress silicon-rich nitride is deposited as the dielectric layer by low pressure chemical vapor deposition (LPCVD) due to its better step coverage, higher dielectric constant and higher density of the deposited film. The remaining photoresist mask from the ICP process must be removed completely, and the wafer must go through RCA cleaning once more before the LPCVD process. In order to have a 500 Å thick silicon nitride on the device sidewalls, deposition time was expanded to 8 minutes. Detailed parameters are given as below.

Description Process parameters Remarks

SiH2Cl2 flow rate 85 sccm NFC LPCVD

NH3 flow rate 17 sccm NFC LPCVD

Process pressure 180 mTorr NFC LPCVD

Process temperature 850 °C NFC LPCVD

Deposition rate 75 Å/minute (12 wafer cassette) 8 minute process

Step H: Wafer dicing

Since the back side substrate will be removed by ICP deep etching to reduce parasitic capacitance, large areas of silicon will be removed and buried oxide layer will be exposed. This causes two problems. One is that the entire wafer becomes very fragile and may disintegrate in the reactor chamber. The other is that the residual stress in the oxide can damage the structures in the front side device layer. Therefore, the wafer is diced first by a Disco 2H/6T system. The front side silicon structures are protected during the dicing process by a AZ4620 photoresist coating. The subsequent back side etching will be conducted with the individual chips bonded to a carrier wafer by heat dissipation paste. This process greatly improves the fabrication yield.

Step I: Top side silicon nitride removal

Before the back side ICP process, the top side silicon nitride layer should be removed by RIE (SAMCO RIE-10N) in order to provide electrical contact to the silicon device, as shown in Fig. 3.1 (g). An etching time of 30 seconds is enough to completely remove the 500 Å silicon nitride layer. Over etching will reduce sidewall nitride thickness and device thickness. Detailed parameters are given as below.

Description Process parameters Remarks

SF6 flow rate 30 sccm RIE-10N

CHF3 flow rate 10 sccm RIE-10N

Helium back side cooling Helium flow rate about 15 sccm RIE-10N

Process pressure 50 mTorr RIE-10N

RF power 100 W RIE-10N

Etch rate 1000 Å per minute Silicon nitride

Step J: Back side deep silicon etching

After the diced chips were bonded on a carrier wafer, the back side ICP etching was performed, as shown in Fig. 3.1 (g). A thick layer of oxide was deposited on the carrier wafer to prevent it from being etched and becoming from fragile during the ICP etching. Performing ICP processes on bonded chips will degrade the helium cooling capability and spoil the selectivity and vertical profiles of the ICP process.

Fortunately, the back side structure is rather insensitive to or even benefiting from the non vertical etching profiles. The silicon oxide hard mask also alleviates the problem with decreased selectivity. Additional blocking structures are used to protect the device from the residual stress in the buried oxide layer. Severe etch rate lagging effect happens between wide and thin open areas, resulting in a rather long etching time needed to complete the entire etching process. Process parameters are identical to those for the front side ICP process.

Step K: Device release

As shown in Fig. 3.1 (h), the device is released by exposing device chips to HF vapor at 30-40°C to remove the unwanted buried oxide beneath the movable structures. HF vapor release helps prevent the stiction which may happen in SW2.

Selectivity of silicon oxide to silicon nitride in HF vapor is assumed to be very high.

The release time is 1 hour and the oxide layer is over etched in order to prevent

shortage during metal deposition. Released device is cleaned by rinsing in de-ionized water and isopropanol (IPA) solution.

Step L: Metallization

A metal layer is deposited on contact pads and the lateral contacts in the mechanical switches, as shown in Fig. 3.1 (i). Ideally, gold should be used due to its slower oxidization in contact operation. In our prototype devices, aluminum is used instead to verify the fabrication feasibility. Sputtering is used due to the better step coverage. With a shadow mask, aluminum is only applied to the contact pad and switch gap areas while the fingers are protected from the deposition.

Step M: Wire bonding and external metal mass attachment

As shown in Fig. 3.1 (j), the last two steps are to wire bond the contact pads to a PCB for further vibration test and then attach the external tungsten ball to the center hole with glue or epoxy. The tungsten ball has a mass of 4 grams and a size of approximately 4 mm in diameter. This assembly step must be done with care;

otherwise the device will be destroyed.

(a) Back side silicon oxide deposition by PECVD

(b) Silicon oxide hard mask patterning and etching by BOE

(c) Front side mask patterning by double side photolithography

Photo resist Oxide

Silicon Nitride Aluminum

(d) Front side ICP deep silicon etching

Fig. 3.1 Fabrication process flow of the SOI device

(e) Silicon nitride deposition by LPCVD

Photo resist Oxide

Silicon Nitride Aluminum

(f) Top side silicon nitride removal by RIE

(g) Bottom side ICP deep silicon etching

Blocking structures

(h) Device release in HF vapor

(guarding and blocking structures removed by rinsing)

Fig. 3.1 Fabrication process flow of the SOI device (continued)

Photo resist Oxide

Silicon Nitride Aluminum

(i) Metal deposition by sputtering with a shadow mask Shadow mask

(j) Wire bonding and external tungsten ball attachment Tungsten ball Switch gap Fingers

Fig. 3.1 Fabrication process flow of the SOI device (continued)

This is the original fabrication process. It depends heavily on ICP etching. Other important issues are: the silicon nitride sidewall must survive the whole fabrication process to provide proper electrical insulation; the metallization must be done with care to avoid shortage between electrodes.

Fabrication process was conducted in the Nano Facility Center at National Chiao Tung University, the Nano Science and Technology Center at National Tsing Hua University, the Nano-Electro-Mechanical-System Research Center at National Taiwan University and the National Applied Instrument Technology Research Center.