2.3. Flash Controller NAND
2.3.1. FCP (Flash Command Port)
flash memory page read / write or block erase command to the same order, first, to set the FCP must be set in the flash command register FCP, bank number ,
row / column address buffer address, flag options exist, such as these three registers are set to perform at the issue, the FCP is passed to WR.
FCP for a description of the three registers shown in Table 1 below. FCP This register sets the FTL flash memory when the actual IO related requests, ie the flash memory interface, LLD
(LowLeveldevice Driver) to set the stage.
0 FCP_CMD BankBank Bank1n1
FCP_ISSUE
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Table 1) FCP register set
Register Address Description FCP_CMD 0x6000_0034
NAND Flash command set to 0x00 = FC_WAIT 0x02 = FC_COL_ROW_IN 0x04 = FC_IN_PROG 0x0a = FC_COL_ROW__READ_OUT 0x0c = FC_OUT 0x10 FC_READ_ID 0x14 = FC_ERASE 0x16 =
FC_GENERIC_ADDR========
=0x01FC_COL_ROW_IN_PROG 0x03FC_IN 0x09FC_PROG 0x0bFC_COL_ROW_READ 0x0fFC_COL_OUT 0x12FC_COPYBACK 0x15FC_GENERIC 0x17FC_MODIFY_COPYBACK note: in order for a motion command code
flash. / include / flash.h to consult it. FCP_BANK
0x6000_0038 Bank number note:
NUM_BANKS)0x3F = autoselect mode(AUTO_SEL)AUTO_SEL (max:is set to, FCP command issueafter the first
the bankidle state by going to import the contents of the WR, parallelism increase canFCP_OPTION
0x6000_003C
FCP option flag setting 0x001 FC_P 0x008 = 0x020 = FO_H 0x080 = FO_B_SATA_W====FO_SCRAMBLE:
=0x006 0x010FO_L 0x040FO_B_W_DRDY 0x100FO_B_SATA_RFO_E:
FO_SCRAMBLEFO_EFO_P: 2plane mode ECC & CRC hardware enable enable data scrambler disable LOW chip FO_H: disable HIGH chip FO_B_W_DRDY: ready data to write in write buffer FO_B_SATA_W: release write buffer when FCP command is completed FO_B_SATA_R: release read buffer when FCP command is completed FO_L:note:in the description for the flash option flag the. / include / flash.h to
consult it. FCP_DMA_ADDR 0x6000_0040
DRAM to flash or flash to DRAM buffer address for the
note: buffer address must be a multiple of the 512B FCP_DMA_CNT 0x6000_0044
data size (unit: Byte, 512B must be a multiple ofFCP_COL column0x6000_0048 start position (Unit: Byte, FO_E If you useof
must be a multiple512B,max: SECTORS_PER_PAGE 1) FCP_ROW_L FCP_ROW_H
0x6000_0048
total number of pages based on the virtual page number of the target 0x6000_004C
(max: PAGES_PER_VBLK 1) in this register exist as a bank number, H / L are each upper / lower means that the chip
(typically a H / L value is set row all have the same chip)
note: bank number as the reason for the autoselect mode when operating, Each bank intended to specify the location of the target page
note: copyback command when the source row is FCP_DST_COLHas 0x6000_0118
Destinationto be the starting column location of the virtual page
(NAND flash chip when you use the command set of copyback) FCP_DST_ROW_LFCP_DST_ROW_H
0x6000_0150 0x6000_0154 beDestination virtual page number
(NAND flash chip when you use the command set of copyback)
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FCP_CMD_ID
0x6000_0158 FCP command id
used for debugging purposes as a register, WR will be passedthe hardware will
command,automatically be given a sequence numberFCP_ISSUE to WR0x6000_015C FCP command register for forwarding
write any value to this register that give FCP commands are passed to WR (ie, issue) Has
2.3.2. WR (Waiting Room)
WR, the command is passed to the flash memory, and a place to pause before FCPthe sameas
hasinformationthe flash controller performs the requested command to check the status of the bank to be idle(idle), when, on its bank to pass the contents of the WR, if the target bank is busyphase
if the WRTaeil continue to wait. Figure 9, as shown in, a WR,onlysinglepass of the FCP may be requested.
Table 2) WR register set
Register Address Description WR_STAT 0x6000_002C
WR for observing the state of the registers
note: The following conditions are to be empty meaning WR (WR_STAT & 0x0000_0001 == 0) WR_BANK 0x6000_0030
Autoselect mode to FCP anddelivered to the NAND wasflash,the command Take thebank number identifying registerfor
NOTE: WR command is transmitted to the FCP is already in a state different from the new issuethe FCP whencommand,whether to perform the command passed H / W is not predictable, so firmware will WR_STATregister
Be sure to check the is empty when the WR command to the new flashprimer.
lock the
2.3.3. (Bank Status Port) BSP
BSPAs you can see in Figure 8 in FCP is to issue a Flash command information and WR WR to issue consists of the additional information (ie, WR still contains the information passed). BSP is
present in each and every bank, 0x6000_0160 from 48 bytesa total of 32 bank BSP is 0x6000_070 up toto be continuous. default BSP is performed corresponding to the last bankon the command contains informationfor debugging purposes because it can be used very
easily, while,BSP internal flash operations are performed in addition to information on the error that occurred in the process of Table 3 are
more interrupt sources recorded in the register and that BSP_INTR bankthe current operating status informationwhich containscan be confirmed by BSP_FSM register.
NOTE: BSP_INTR register yourself clear before the firmware is not Lab.reserved.
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Table 3) & BSP_FSM registerBSP_INTR BSP_INTRRegister Address Description 0x6000_0760: 0x6000_0780
Bank interrupt information. (1Byte)
Bank exists separately for each 0x01 = FIRQ_CORRECTED 0x02 = FIRQ_CRC_FAIL 0x04 = FIRQ_MISMATCH 0x08 = FIRQ_BADBLK_L 0x10 = FIRQ_BADBLK_H 0x20 = FIRQ_ALL_FF 0x80 = FIRQ_ECC_FAIL 0x82 = FIRQ_DATA_CORRUPT BSP_FSM
0x6000_0780: 0x6000_0800
Bank FSM (Finite State Machine) information. (1Byte)
BSP_INTR register separately for each bank presence, like 0x0 = idle others = no idle