Chapter 4 JOINT SHIELD INSERTION AND BUS
5.3 Joint Shield Insertion and Bus Encoding Scheme for Power
5.3.2 Joint Shield Insertion and Bus Encoding Flow for Power Minimization
Figure 49 illustrates our overall joint shield insertion and bus encoding flow for the bus power minimization. There are four steps in our proposed flow. At Step (1), with the initial bus structure (i.e., inserted m − n extra signal wires to the original bus) and the given bus parameters, we utilize the flexible bus encoding scheme to find the valid code set with minimum total transition power (see Section 3.2 for details). Then, we will check whether the code set covers all data patterns. If not, we conduct Step (3) to generate another bus structure (see Section 4.3 for details) and then redo from the Step (1). Otherwise, the code set will be output to Step (2) (see Section 5.2 for details)
set with minimal total transition power from the outputted code set. Following, the found minimum power valid code set will be recorded together with the corresponding bus structure, and then we will check if all bus structures are tried (i.e., all m − n extra signal wires substituted by shielding wires). If not, we conduct Step (3) to generate another bus structure and then redo from the Step (1). Otherwise, the best valid code set (with minimum total transition power) will be output to map to the data patterns with the corresponding bus structure.
(4). Save the low power valid code set and bus structure (4). Save the low power valid
code set and bus structure (2). Flexible bus encoding for power minimization (2). Flexible bus encoding
for power minimization Bus parameters, working frequency, and constraints Bus parameters, working frequency, and constraints
(1). Flexible bus encoding for delay constraint (1). Flexible bus encoding
for delay constraint
Does the valid code set cover all data pattern?
Does the valid code set cover all data pattern?
Output the valid code set with minimum power and the corresponding bus structure Output the valid code set with
minimum power and the corresponding bus structure
Figure 49: The proposed joint shield insertion and bus encoding flow for bus power
5.3.3 Simulation Results
Here, we present the simulation results of reducing the power consumption of the on-chip bus subject to the delay constraint by using the proposed joint shield insertion and bus encoding scheme.
In the following, the length, width, height, pitch of signal wires, and Power/Ground-to-signal pitch are 2000μm, 2μm, 2μm, 4μm, and 13μm, respectively.
The supply voltage is 1.2V. We vary the bus working frequency from 0.5 to 5 GHz, and the simulation results of a 6-bit bus with wire overheads (m − n) varying from 1 to
5 are shown in Figures 50, 51, and 52.
From Figures 50, 51, and 52, we observe that when the wire overhead m − n is larger than 3, the average power reduction of the joint shield insertion and bus encoding scheme could be more than that of the flexible bus encoding scheme. This is because a wider bus has more significant inductance effects than a narrower one, and the inductance coupling can be effectively minimized by the optimized shield insertion technique. Therefore, for tight wire overhead constraint (≤ 3 wires), we could obtain very well average power minimization by using the flexible bus encoding scheme. However, for the wire overhead constraint larger than 3, the joint
than that of the flexible bus encoding scheme.
In addition, from Figures 50, 51, and 52, we observe that as the working frequency increasing, our proposed joint shield insertion and bus encoding scheme could also obtain better average power reduction than that of the flexible bus encoding scheme. This is due to the significant inductance effects at high working frequency.
Hence, by applying the optimized shield insertion technique first for the inductance-dominated bus, then we could obtain a better valid code set for the bus power reduction by flexible bus encoding. Therefore, our proposed scheme is very suitable for minimizing the power consumption of the inductance-dominated bus.
0.5 GHz
10.00%
12.00%
14.00%
16.00%
18.00%
20.00%
22.00%
24.00%
26.00%
m=7 m=8 m=9 m=10 m=11
average power reduction(%)
Joint shielding and coding Flexible bus coding
Figure 50: Average power reduction of the flexible bus encoding scheme and the joint
1 GHz
Figure 51: Average power reduction of the flexible bus encoding scheme and the joint shield insertion and bus coding scheme for 1 GHz working frequency.
5 GHz
Figure 52: Average power reduction of the flexible bus encoding scheme and the joint
5.3.4 Summary
In this section, by incorporating the optimized shield insertion technique with our flexible bus encoding scheme, we proposed the joint shield insertion and bus encoding scheme for bus power minimization under a given delay constraint. For loose wire overhead constraints and high working frequency, simulation results show that the new scheme can gain more average power reduction than that gained by using the flexible bus encoding only. Therefore, we can conclude that the joint shield insertion and bus encoding scheme could outperform the flexible bus encoding scheme for inductance-dominated buses.
Chapter 6
CONCLUSIONS & FUTURE WORKS
In this dissertation, we first show that the worst-case switching pattern that incurs the longest bus delay while considering the RLC effect is quite different from that while considering RC effect alone. It implies that the existing encoding schemes based on the RC model may not improve or possibly worsen the delay when the inductance effects become dominant. Then, we proposed several bus encoding schemes to minimize the bus coupling delay and the power dissipation. Simulation results are also given to show the performance of our proposed schemes.
In Chapter 1, while considering the RLC circuit model for the bus structure, our finding show that the worst-case switching pattern could be very different from that of only considering RC effects. First, when the inductance effect dominates, the
simultaneously switch in the same direction. Furthermore, we indicate that while considering the RLC effects of interconnects, the worst-case switching pattern varies from different levels of interconnect and different working frequencies. Hence, as inductance cannot be neglected in today’s high-speed circuit design, it is very important to consider the RLC effects with different bus parameters to develop the proper encoding schemes for bus delay reduction.
In Chapter 2, we proposed a bus-invert method to reduce the worst-case on-chip bus delay with the dominance of the inductance coupling effect. Simulation results have shown that our encoding method can significantly reduce the worst coupling delay of the buses with strong inductive coupling.
From our simulation results, we observe that the worst-case switching pattern could vary with given design parameters considering the RLC effects of interconnects.
However, the proposed bus-invert method can be utilized to reduce the bus coupling delay only when the inductance effects dominate. Therefore, in Chapter 3, we proposed a flexible encoding scheme for on-chip buses that can consider the given parameters to reduce the LC coupling delay. In addition, with some modification, this new encoding scheme can be utilized to predict and lengthen the signal propagation length of a bus under the given constraints. Simulation results are also given to support our claims.
In Chapter 4, to further reduce the coupling noise, we proposed a joint shield insertion and bus encoding scheme for global bus design in nanometer technologies.
With the user-given bus parameters, the working frequency, the scheme can effectively reduce the LC coupling effects and hence, minimize the bus coupling delay.
Simulation results show that the proposed scheme can significantly reduce the coupling delay.
Recently, the power consumption of on-chip interconnect is another crucial issue in high performance circuit designs. In Chapter 5, we first proposed a flexible encoding scheme to minimize the power consumption of buses under given delay constraints. To further improve the performance of the encoding scheme (further reduce the power consumption), we also utilized the joint shield insertion and bus encoding method to solve the problem. With the user-given bus parameters, the working frequency, and the delay constraint, both schemes can minimize the bus power consumption subject to the delay constraint by effectively reducing the LC coupling effects. Simulation results show that the proposed schemes can significantly reduce the coupling delay and the power consumption of a bus according to the delay constraint. In addition, the joint shield insertion and bus encoding method can gain more power reduction than that gained by only using the flexible bus encoding scheme.
In the future, we intend to incorporate the repeater insertion technique in our joint shield insertion and bus encoding scheme to further reduce the bus delay and power consumption. In addition, the ground bounce effect can also be considered and minimized in our future work. Consider the switching probabilities of the bus wires, we can also try to generate a specific code set for the bus used in ASIC to optimize the bus power and delay. If those issues can be considered, our encoding scheme will be more powerful.
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作 者 簡 介 About the Author
姓 名 中文：涂尚瑋 英文：Shang-Wei Tu
基本資料 生日：1977/04/10 籍貫：台灣省台南市
學 歷 國立交通大學電子研究所博士班 2001/09 ~ 2006/09 國立交通大學電子研究所碩士班 1999/09 ~ 2001/06 國立交通大學電子工程學系 1995/09 ~ 1999/06
經 歷 數位電路與系統助教 2006 九十四年度交通大學電子所年度論文獎佳作 2005
計算機輔助設計特論助教 2003 ~ 2005 交通大學電子研究所博士班甄試第一名 2001
程式語言助教 2000 研究所學期成績優異獎 1999 凌陽科技公司暑期實習 1999
教育部大學校院積體電路電腦輔助設計軟體製作競賽 佳作 1999
教育部大學校院積體電路電腦輔助設計軟體製作競賽 入圍 1999
研究領域 Circuit Modeling Computer-Aided Design Algorithms
專 長 EDA Algorithms
Hardware Description Language: Verilog Programming Language: C/C++
著 作 目 錄 涂尚瑋
Publication List Shang-Wei Tu
依新法記點 國外期刊(共 4 點)
(2 點，長文) 1. S. W. Tu, W. Z. Shen, Y. W. Chang, T. C. Chen, and J. Y. Jou,
"Inductance modeling for on-chip interconnects," Journal of Analog Integrated Circuits and Signal Processing, pp. 65-78, vol.
35, No. 1, April, 2003. (Invited paper for ISCAS’2002 special issue on analog and mixed signal circuits.)
(2 點，短文) 2. Shang-Wei Tu, Yao-Wen Chang, and Jing-Yang Jou, “RLC coupling-aware simulation and on-chip bus encoding for delay reduction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005. (Accepted)
國際會議(至多採計一篇)
國際會議(至多採計一篇)