Chapter 6 Conclusions and Future Work
6.2 Future Work
For the future integrated-circuit (IC) and System-on-Chip (SoC) designs, energy-efficient designs are essentially required. As the technology scale down to deep-submicron and nano-scale eras, both supply voltage (VDD) and threshold voltage (Vt) are reduced for low-power and high-performance designs.
The standby leakage is becoming more serious in deep-submicron and nano-scale technologies. In deep-submicron technologies, sub-threshold leakage is the critical component among all the leakage currents. Sub-threshold leakage increases due to the reduction of threshold voltage with the scaling of technology. In order to compensate the performance degradation of descending supply voltage, threshold voltage is scaled down to satisfy speed requirement. Therefore, the influence of leakage power is becoming significant if threshold voltage keeps on scaling down.
One more leakage source called gate-tunneling leakage (or gate leakage) is becoming important in nano-scale technologies. The increase of gate-tunneling leakage mainly results from the scaling of thickness of gate oxide. Many predictions show that gate leakage has the potential to exceed sub-threshold leakage and dominate the standby leakage current in the future. In recent years, the power-gating techniques are widely used to reduce leakage current of CMOS circuits in standby mode.
Fig. 6.1 (a) depicts a SRAM cell with a gating device between virtual GND and actual GND. As the gating device is turned off, the virtual GND vss0 is floating and charged by leakage current. Thus, the voltage increasing of virtual GND vss0 is obvious. By contrast, Fig. 6.1 (b) shows another modified SRAM cell with gating device and a diode-connected NMOS (data retention device) virtual GND vss1 and actual GND. Through adding NMOS, the voltage of vss1 will be limited. Moreover, the voltage of vss1 is determined by the size of diode-connected NMOS.
BL BL
WL
BL BL
WL
vss0 vss1
ctrl ctrl
Fig. 6.1 Modified SRAM cell. (a) without diode and (b) with diode.
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Vita
PERSONAL INFORMATION Birth Date: March. 04, 1982
Birth Place: Taipei, Taiwan, R.O.C.
Address: Department of Electronics Engineering National Chiao Tung University 1001 Ta-Hsueh Road
Hsin-chu, Taiwan 30010, R.O.C.
E-Mail Address: [email protected]
EDUCATION
B.S. [2004] Department of Electronical Engineering, Chang Gung University.
M.A. [2006] Institute of Electronics, National Chiao-Tung University.