H ALF - RATE F REQUENCY D ETECTOR

The circuit implementation of the half-rate frequency detector is shown in Fig. 4-10 [26]

[27] [28]. At every transition of the input NRZ data, the multiple clock phases of 45° spacing, clk0, clk45, clk90, and clk135 are sampled. The D flip-flops, D5, D6, D7, and D8 play a role as registers that save the two XOR outputs X1 and X2.

Fig. 4-10 Half-rate frequency detector

Fig. 4-11 shows the timing diagram for a periodic data signal with the clk0, clk45, clk90, and clk135. The notes X1 and X2 are needed to define four quadrants of phase which are 0,0, then 0,1, then 1,1, then 1,0, where high and low logic levels are represented by 1 and 0. When there is a frequency difference between input signal and clock output, the sampled quadrant will rotate around the circular phase diagram. Direction of this rotation determines whether half of the input signal frequency is faster or slower than the clock frequency as shown in Fig.

4-12.

Fig. 4-11 Timing diagram of the FD (a) Fvco < 1/2 data rate (b) Fvco > 1/2 data rate

Fig. 4-12 Circular phase diagram

It can be seen from Fig. 4-12, when the clock frequency is lower than half of the input signal frequency, the sampled quadrant rotes counterclockwise and vice versa. The direction of rotation can be detected by monitoring the two consecutive quadrants like 1,0 and 0,0. If the sampled quadrant moves from the former to later, the clock is found to be slow and an up pulse is needed to speed up the clock. On the other hand, a transition from 0,0 to 1,0 quadrant denotes a fast clock and a down pulse should be generated to slow down the frequency of the clock. The up and down signals can be implemented as Fig. 4-13.

Fig. 4-13 Up and down generator

The half-rate frequency detector has two features. First, it will turn off automatically when frequency of the VCO is close to half of the input data rate. When the frequency detector turns off, the frequency error of the two signals is within a range between ±300ppm.

Hence, the frequency detector does not affect the operation of the phase detector and there is no need to switch off the frequency detector in the lock state. It means that low jitter performance can be achieved. Second, the frequency detector has a large capture range for the NRZ input data. It can detect frequency derivation over ±30 percentage of the data rate. Thus, the tuning range of the VCO could be design larger.

4.3.3.3 Voltage Controlled Oscillator

A ring oscillator is implemented as VCO due to its wide tuning range. While LC topologies achieve a potentially lower jitter, their limited tuning range makes it difficult to obtain a target frequency without design and fabrication iterations. It is also important that the VCO must maintain a fixed frequency range under different process, temperature, and supply

control voltage must be able to tune it back to the desire frequency.

Since the CDR used in this thesis is operated at half rate with a frequency detector, the oscillator must generate four-phase output. A four-stage differential ring oscillator is used. Fig.

4-14 (a) shows the implementation of each delay stage [29]. Comparing to the VCO mentioned in section 3.2.3.4, the Kvco (Hz/V) is much lower when both VCO operate at 500MHz.

Fig. 4-14 (a) Delay cell (b) Half-circuit of the delay cell for small signal analysis An NMOS input pair is used to achieve the high transconductance-to-capacitor (gm/C) ratio to operate at high frequency. Frequency tuning is achieved by tuning the transconductance of the diode-connected PMOS device Mp2. To derive the operating frequency of the oscillator, a half-circuit of the delay cell for small signal analysis in Fig. 4-14 (b) is considered.

The transfer function of the delay cell could be given as

( ) (

)

where gm is the transconductance; gd is the channel conductance; Cgs is the gate-to-source capacitance; Cgd is the gate-to-drain capacitance; Cdb is the drain-to-bulk capacitance; Cbuffer

is the capacitance of output buffer.

To maintain the oscillation of a ring oscillator, the total phase shift of the delay cell chain is 180° and the overall gain is unity at the oscillation frequency. Therefore, the phase shift of each delay cell must equal to or more than 45° while the voltage gain of each delay cell is larger than 2. By equating the total voltage gain to be unity, the oscillation frequency of the ring oscillator can be derived as

( )

By controlling the gm of the diode-connected PMOS devices Mp2, the output frequency can be adjusted. At the maximum oscillating frequency, the negative transconductance gmp1 is just large enough to completely compensate the total load conductance (gmp1=gmp2 + GL).

At the minimum oscillating frequency, the diode-connected PMOS devices Mp2 are turned off (gmp2=0) and the drain conductance of devices Mn1 and Mp1 is much smaller than the negative transconductance (gmp1>>GL). Consequently, the maximum frequency, minimum frequency, and operating frequency range can be calculated as follows:

L

2

Besides, the duty-cycle of the VCO is another issue for half-rate CDR design. Thus, the duty-cycle corrector mentioned in section 3.2.3.4 is connected at the outputs of the VCO to ensure that the duty-cycle of the VCO will be 50%.

For linearity consideration, a linearization circuit is used and shown in Fig. 4-15 [28].

The input controlled voltage, Vctrl, is not directly applied to the VCO, but is converted to another voltage, Vtun, with a scaling-linear characteristic.

Fig. 4-15 Schematic of the linearization circuit

The product of this transfer curve with the VCO tuning sensitivity should be as constant as possible to achieve a linear overall tuning. The output voltage, Vtun, changes with the input voltage, Vctrl, which cover the linear gradation characteristic of the VCO. Fig. 4-16 shows the characteristic transfer curve of the linear circuit.

Fig. 4-16 Transfer curve of the linear circuit

The simulated transfer curve of the VCO is shown in Fig. 4-17. The VCO uses four delay buffer stages with the output frequency at 500MHz. The supply voltage is 3.3V. The gain of the VCO is -150MHz and the transfer curve is monotonic. The tuning range of the VCO is 395MHz~608MHz which falls inside the capture range of the frequency detector. It means that when power turns on, the CDR can act correctly.

Fig. 4-17 Transfer curve of the VCO