Hardware Implementation
6.2 Programmable Morphological Processor (PMP)
6.2.3 Hardware Architecture
As mentioned in the previous section, the main concept of morphological operations is based upon combining dilation and erosion operations. Based on these two operations, the hardware architecture was designed, as shown in figure 6.16.
PDEU2
Fig. 6.16 Hardware architecture of morphological operations.
In figure 6.16, the hardware architecture consists of two programmable dilation and erosion units (PDEU), one control unit (CU) and one output unit (OU). The function of PDEU is to execute the dilation and erosion operations. The OU is used to select which computation results should be outputted from the system, while the CU generates the control signals for the PDEUs and the OU.
The system function of Figure 6.16 is summarized by the following table.
Table 6.2 System function of morphological operations.
PDEU1 PDEU2 OU System Function
Dilation - ODE1 Dilation
Erosion - ODE1 Erosion
Dilation Erosion ODE2 Closing
Erosion Dilation ODE2 Opening
Dilation Erosion ODE2-ODE1 Morphological Gradient Erosion Dilation I - ODE2 Top-hat transfer
In the following section, we will introduce in detail the PDEU, the OU and the CU.
a. PDEU
The main function of the PDEU is to execute dilation and erosion operations, as shown in figure 6.17. It does so by computing the maximum or minimum value that is the convolution of image I by a structuring element of size 4x8. The PDEU must extract each element from the SE and then use those elements to determine the maximum or minimum value. The architecture of the PDEU contains two data registers of FIFO unit (First In First Out) and one SR unit (shift register) for retrieving the data from the structuring elements. In addition, there is a CN unit (compared network) that selects the maximum value or minimum value from the shift registers. The two outputs from the CN and the shift register are ODEand OBuf, respectively.
P1
Fig. 6.17 The FIFO array for PDEU, where the numbered rectangles represent shift registers (SR).
For gray-level images, the intensity of every pixel I( , )x y is passed from the input I, through a chain of shift registers where the intensity of every element is extracted and
passed to the CN via the P wire. Given that one element is extracted at every clock cycle, the system will be able to obtain the result of the dilation or erosion operation after a total of 3N+8 clock cycles.
Before sending the raw image pixel to the CN, its value must first be sent to the SSE for preprocessing, as shown in figure 6.18, where every data line to the CN from the PDEU in figure 6.17 has its corresponding SSE (selection of structuring element). The operation of the SSE has two distinct outcomes. If the control signal S is set to 1, MUX will select Pi to be POUT. This occurs when the user requires its structuring element to perform dilation or erosion. On the other hand, if the control signal S is set to 0, the user chooses not to utilize the structuring element. Meanwhile, the control signal D/E from the PDEU chooses D for the dilation (the signal is set to 1, as shown in Table 6.3), so the result of the dilation will become 0 after passing through the inverter.
P1
MAX/MIN ● ● ●
MAX/MIN
MAX/MIN
P2 P3 P4 P29 P30 P31 P32
D/E
ODE
SSE
MAX/MIN
MAX/MIN MAX/MIN
SSE SSE SSE SSE SSE SSE SSE
S
● ● ●
● ● ●
MAX/MIN
Fig. 6.18 The architecture of CN.
0 1
s O
S D/E Pi
POUT
8 8
8 MUX
Fig. 6.19 The circuit for selection of structuring element (SSE).
The CN is composed of MAX/MIN units that are used to compute the magnitude value based on the tree-based architecture, as shown in figure 6.18. If the control signal of D/E is set to 1, CN will output the maximum value of the 32 raw image pixels. However, if the control signal of D/E is 0, CN will output the minimum value.
The MAX/MIN component of figure 6.18 is composed of one multiplexer and one comparator, as shown in figure 6.20. If input D/E is set to 1, the dilation operation will be performed and the result of comparator becomes A>B, whereby the multiplexer will output A. In the same way, if input D/E is set to 0, the erosion operation will be performed, and the result of comparator becomes B>A, whereby the multiplexer will output B.
D/E
A B
Comparator
A>B
A B
s MUX
O
A B
Out
Fig. 6.20 The circuit of Max/Min.
b. Output Unit (OU)
Before introducing the architecture of the OU, we first have to discuss the data flow between the buffers of the two PDEUs required for top-hat transfer. As shown in equation 6.18, the top-hat transfer operation is obtained by subtracting the opening of image I from the original image I. We can implement this in hardware design by setting PDEU1 to perform the operation of erosion and PDEU2to perform the operation of dilation from the output of PDEU1, which will combine to give us the required operation of closing. Finally, we can subtract the output of PDEU2 from the original image I to give us the desired result from the top-hat transfer operation.
SR
Fig. 6.21 Hardware architecture of the OU.
Figure 6.21 shows the architecture of output unit (OU). The shift register, SR, is used to store the original input image I, and MUX1 is used to select the minuend for the subtraction calculator (SUB). If MUX1 selects the original input image of I and SUB completes the operation withODE2, the output becomes the top-hat transfer. Similarly, if we manipulate the outputs of PDEU1 and PDEU2 to perform dilation or erosion and choose a suitable output from the three multiplexers (MUX1-3), the system can be shown to execute any of the other morphological operations.
c. Control Unit (CU)
The control unit is use to generate the control signals for both the PDEU and the OU.
Table 6.3 shows the truth table of the CU. As we have set up the system to perform six different morphological operations—dilation, erosion, opening, closing, top-hot transfer and morphological gradient—we require a minimum of three variables, C0-2 to be able to define each operation distinctly. Figure 6.16 also shows that the PDEU requires three control signals: x, D/E1 and D/E2 to give a correct output and that according to Figure 6.20, the OU needs S0-2 to choose the output of the three multiplexers. Therefore, we can see that the CU requires six outputs to meet the requirements of the PDEU and OU.
Let’slook attheopening operation ofequation 6.16 as an example. We know that the opening operation consists of erosion followed by dilation. So, if we already know that the input of CU (C0 2)is"100”,we need to setthefollowing six outputsto control the signals to give us the opening operation. The signal of D/E1 must be set to 0 so that PDEU1 performs erosion, x must be set to 0 so that the output of PDEU1 becomes the input to PDEU2, and the signal of D/E2 set to 1 so that dilation is performed. In other words, PDEU2transforms the input image I firstly by erosion, then followed by dilation.
The signal of S1 denotes that the output of MUX1 1is ODE2, while the signal of S2 1 denotes that the output of MUX2is OMP, as shown in figure 6.21.
Table 6.3 The truth table of CU, where isdenoted as“do notcare.”
Input Ouput
C2 C1 C0 x D/E1 D/E2 S2 S1 S0
Function
0 0 0 1 0 Erosion
0 1 1 1 0 Dilation
1 0 0 0 0 1 1 1 Opening
1 0 1 0 1 0 1 1 Closing
1 1 0 0 0 1 0 0 Top-hat transfer
1 1 1 1 1 0 0 1 Morphological gradient
6.2.4. Experimental Results
To implement the system, we used a prototype board, which contained a Cyclone EP1C6Q240C8 Altera FPGA operating in the QurtusⅡ environment. The software we chose to communicate with the prototype board was Borland C++. The waiting time for the system was W+2 clock cycles, and at every clock cycle, the system computed each pixel of the morphological operation. The total execution time was therefore W+2+W*H clock cycles, where W and H represented the width and height of the image, respectively.
For an image size of 640*480, the total processing time was (640+2+640*480/50) =s 6.156ms when a 50MHz clock was used.
(a) Original input image (b) Erosion (c) Dilation (d) Closing
(e) Opening (f) Morphological gradient (g) Top-hat transfer Fig. 6.22 Experimental results for 3x3 structuring element.
Figure 6.22 shows the experimental results of the morphological operations. Figures 6.22(a), 6.23(a) and 6.24(a) show the original input image. The figures in Figure 6.22(b) to 6.22(g) show the results of erosion, dilation, closing, opening, morphological gradient and top-hat transfer for a 3x3 structuring element, respectively. We can see that compared with the erosion in Figure 6.22(b), the license plate images using larger structuring element areas, in 6.23(c) and 6.24(b) both become more blurry. However, using top-hat transfer, the images of Figures 6.22(g), 6.23(g) and 6.24(g) show that a bigger structuring
element will produce a clearer image of the license plate number.
(a) Original input image (b) Erosion (c) Dilation (d) Closing
(e) Opening (f) Morphological gradient (g) Top-hat transfer Fig. 6.23 Experimental results for 4x4 structuring element.
(a) Original input image (b) Erosion (c) Dilation (d) Closing
(e) Opening (f) Morphological gradient (g) Top-hat transfer Fig. 6.24 Experimental results for 4x8 structuring element.
6.2.5 Conclusion
This study has presented a new hardware architecture design for morphological operation, which has been successfully implemented by SOPC (System on Programmable
Chip). The experimental results have shown that the system is capable of performing the six fundamental morphological operations: dilation, erosion, opening, closing, morphological gradient and top-hat transfer, all in real-time processing.
We have also been able to increase the adaptability of this system compared to previous designs by setting up the system to handle structuring elements of arbitrary sizes and shapes. We believe that with this additional feature, our system will be able to cater for even more applications of image recognition.
7-1