Profile for dual-core P macroblock encoding module

The follow figure shows the main computation components of dual-core P macroblock processing module with the fastest mode we mentioned before.

Fig 37 Profile for dual-core P macroblock encoding module

We experimented with two different implementations of DMA control modules in this thesis. The first one transfers all memory section of the reconstructed frames from DSP to ARM. This implementation has lower complexity of DMA handler, but increases the amount of redundant transfer. The second implementation transfers memory sections of the reconstructed frames from DSP to ARM according to its encoding status. Although this approach makes the DMA handler more complex, it removes redundant data transfer.

The follow two tables show the result of transfer with redundant transfer.

Table 41 Experiment result of profile P MB encoding

Number Execution time (ms) Description 1 4261 Time in dual-core processing

2 689 Time in interrupt mode

3 357 Time in handling DMA handler

4 126 Time in handling Dual-core handler 5 727 Time in transfer data to DSP by DMA 6 1452 Time in receive data from DSP by DMA

7 523 Time in post-processing

A/D 3.11

Total time 4785

Table 42 Calculated result of profile P MB encoding

Description Execution time (ms) or Percentage

ARM core execution time 3572

DSP core execution time 1393

Dual-core execution section percentage 89%

Post processing section percentage 10%

And the follow two tables show the result of transfer without redundant transfer.

Table 43 Experiment result of profile P MB encoding

Number Execution time (ms) Description 1 3813 Time in dual-core processing

2 742 Time in interrupt mode

3 397 Time in handling DMA handler

4 136 Time in handling Dual-core handler 5 756 Time in transfer data to DSP by DMA 6 895 Time in receive data from DSP by DMA

7 526 Time in post-processing

A/D 3.74

Total time 4341

Table 44 Calculated result of profile P MB encoding

Description Execution time (ms) or Percentage

ARM core execution time 3071

DSP core execution time 1420

Dual-core execution section percentage 87%

Post processing section percentage 12%

Obviously, it shows that the implementation which transfers data without redundancy is more efficient, although the overhead of the DMA handler becomes more complex than the other method, but its overall performance gain is better than the implementation redundant transfer.

Chapter 6 Conclusions and Future Works

From these experiments, one can see that the proposed dual-core codec partitioning framework achieves better performance than using the DSP core alone. The thesis also shows that data transfer overhead between the RISC core and the DSP core is crucial to the performance of the system. Efficient use of DMA module for data transfer also plays an important role in this framework. For future improvements, instead of executing jobs at frame-level, data structures and execution flows of our codec should be modified for execution at slice-level or macroblock-level. This allows the combination of multiple function modules into one single module and reduces large data transfer overhead. Fig. 38 shows this concept, the left-hand side of the figure shows current execution flow, and the right-hand side shows the improved architecture for future work.

Fig 38 Architecture of future work

In our current design, motion compensation module is running on the RISC core alone. With the above-mentioned modification, the motion estimatin/compensation subtasks can be completely hosted on the same core (either RISC or DSP) without extra data transfer overhead.

In addition, as demonstrated by many researches, employing dual buffer mechanism on the DSP core can increase memory bandwidth greatly. This is a key technique to improve system performance. It can be expected that we can also use similar design to increase performance of our design, since one of the major bottleneck of the proposed dual-core framework is from the limited memory bandwidth between the RISC core and the DSP core.

Finally, the research conducted in this thesis is a prelude to the design of a dynamic scheduling kernel for asymmetric multiple processors (AMP) platforms. Based on the experiments conducted in this thesis and the simple shell-like DSP command processor developed for this work, one can design an AMP kernel that dispatch tasks to different processor cores on the fly.

Chapter 7 References

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