New Lambda Bipolar Transistor

Fig.8 A vertical Lambda bipolar transistor structure

The proposed new memory cell is based on Wu’s Lambda bipolar transistor (LBT) developed in 1980’s. The LBT is a highly integrated device characterized by its voltage-controlled negative differential resistance, and has been used successful in many applications [52-53]. If the LBT is to be used in static random access memory cell, the standby current in one of its storage states is relatively high. For this reason, a new LBT is proposed for low power applications.

3.1 New Lambda Bipolar Transistor

The basic structure of the new Lambda bipolar transistor and its electrical equivalent circuit connection are shown in Fig.8 and Fig.9, respectively. From Fig.8, the n-channel enhancement-mode MOSFET's are fabricated upon the base region of a vertical NPN bipolar transistor, which is called the vertical Lambda bipolar transistor (VLBT). The source of one of the MOSFET's (labeled as E') is utilized as the emitter of the vertical NPN bipolar transistor, while the p-type diffusion well and the n-type epi-layer act as the base and the collector, respectively. The equivalent circuit is shown in Fig.9 and their interconnections can be clearly seen. It could be noted that, in ordinary circuit applications, E’ is biased at a voltage level lower than B’ and C’. Therefore, E’ is the only possibly turned-on PN junction, i.e. the other three sources/drains other than E’ have no chance to act as the emitter of the vertical bipolar transistor.

Fig.9 An equivalent circuit of a vertical Lambda bipolar transistor

The vertical Lambda bipolar transistor is operated in the same way as

the conventional bipolar transistor with a fixed external base current.

From the terminal characteristics of the separate devices, the general equations for the proposed VLBT, according to the circuit model of Fig.9, can be written as where β is the dc common-emitter current gain of the NPN bipolar transistor, and ICEO=ICO(1+β) is the common-emitter collector reverse saturation current.

A certain current source load M₃ operated in saturation region is chosen for derivation. The current equation can be written as

(

V V V

)

for V

(

V V

is the power supply connected to the drain of the M₃.

In order to get analytical expressions, the body effects are assumed to be negligible. To see the quantitative operational principles of a VLBT shown in Fig.10, the six-region analyses are given as follow:

Region I: region, and Q₁ is operated in forward-active region. By solving V_B’E’, i.e.

²

we get the output current in this region:

( )

forward-active region. Solving V_B’E’ by equating (1) and (5), we obtain and the output current in this region is

( ) ( ) ( ) ( ) derived by letting 0

' operated in saturation region, and Q₁ is operated in forward-active region.

Using equations (1),(2),(4), and (8), we obtain

( ) ( )

By differentiating (11) with respect to V_C’E’, the output resistance in this region can be written as

( ) ( )

_⎥ operated in saturation region.

Assuming _VB_'E_'>_VT, Q₁ is operated in forward-active region. The output

By a chain rule, we have the output resistance

'

The output dc characteristic of the new VLBT is shown in Fig. 3-3.

3.2 Description of the New Memory Cell

The performance of a SRAM strongly depends on the design of its memory cell. Generally, a full CMOS cell is suitable for low power design with acceptable speed. However, it has a significant area penalty over a high-resistance poly load or poly-PMOS load cell. On the contrary,

the fine metal bit-lines in a high-resistance poly load or poly-PMOS load cell will induce large signal delay or high current density, causing reliability

Fig.10 The I-V characteristics of a vertical Lambda bipolar transistor

degradation. In our thesis, a new single-sided memory cell is proposed to solve these problems.

The general configuration of the proposed static random access memory cell is shown in Fig.11, which consists of a VLBT, a load element, a current source device, and an access transistor. Owing to the negative differential resistance of VLBT, the storage node SN has two dc static points (See Fig.12). Two kinds of load elements, current source-like and resistance-like, can be selected for different applications. For a current source-like load, the current flow at the static points S_C1 and S_C2 can be both small if the circuit is well-configured. On the contrary, a

resistance-like load memory cell generally suffers dc current flow at the lower static state SR2. However, it occupies a relative smaller area as compared with a current source-like load one.

Fig.11 General configuration of a new memory cell

Fig.12 The I-V characteristics of a new memory cell with current and resistive load

The new memory cell based on the proposed VLBT is presented in Fig.13. In memory cell configuration, M1, M2 and Q1 operate as a VLBT storage element, M₃ acts as a current source, M₄ acts as the load element, and M5 is the access transistor. When Vx is in the low stable-state SC1, any positive noise causes Vx to increase slightly. At this moment, I_C’ is larger than IDS4 so that Vx discharges to SC1. If any negative noise causes Vx to reduce a little, the fact that I_DS4 is larger than I_C’ will cause Vx to be charged to SC1. Previous description demonstrates why this state is stable.

The same argument can apply to the state S_C2 to verify this state to be stable.

Fig.13 A new SRAM memory cell circuit

If any positive noise is introduced as Vx in the switching state SW, the positive differential current IDS4-IC’ will charge the node X to the high stable state S_C2. The memory cell no longer stays in the state S_W. On the other hand, if negative noise is introduced as the memory cell is in the state S_W, a negative differential current I_DS4-I_C’ makes the node X to be discharged to SC1. Both types of noise (positive and negative) cause a

transition from the state S_W to either the stable state S_C1 or S_C2. The stored voltage levels are CMOS like, i.e., a full swing between ground and supply voltage is obtained.

Fig.14 shows the static noise margin (SNM) comparison between our new memory cell and [48] proposed, which is referred as a LBT configuration. The voltage of storage node at any instant is the base-emitter voltage in the LBT configuration, hence is always less than 1V. The SNM of the new memory cell (VLBT) and the LBT configuration are about 1.2V and 0.4V, respectively. The new memory cell has the larger SNM than LBT configuration. It also shows that the LBT configuration requires adequate circuit to sense the state of the cell, because the switch point of the LBT configuration is less than 1V.

Fig.14 The static transfer characteristics of the memory cells

3.3 Performance of the New Memory Cell

Extensive circuit simulations have been carried out to verify the circuit operation and the characteristics of performance. The performance of the proposed circuit is evaluated based on 5V, 0.5um BiCMOS technology. The simulation results are based on 1ns rise and fall time.

3.3.1 Write Operation

In the static memory cell, the write operation is performed by forcing high and low voltage to the bit-line. The operation cycles start at 3ns, turning on the access transistor M₅ by a word-line pulse with 1ns rise time.

Fig.15 Write “0” operation

When changing the binary state of the memory circuit from 1 to 0, the voltage level of node X rapidly decreases. Because the transistor M₁

is turned off and the transistor M₂ and Q₁ are turned on, the internal capacitor of node Y is charged very fast via the transistor M3. The simulation result is shown in Fig.15. Changing the binary state from 1 to 0 just takes about 0.5ns.

When changing the binary state from 0 to 1, the voltage level of node X increases very fast due to the fact that the current through the transistor M₄ is increased. But with increasing the node voltage Vx, the access transistor as well as the transistor M3 is turned off. Now, the internal capacitor of node X is charged more slowly via the load transistor M₄. The simulation result is shown in Fig.16. Changing the binary state from 1 to 0 just takes about 1.5ns.

Fig.16 Write “1” operation

3.3.2 Read Operation

The stored data of a memory cell selected by the word-line and the

column decoder has to be read nondestructively. For the read operation, the bit-line capacitor CBL is precharged to the reference voltage level Vref

and then is left floating. The bit-line voltage versus time during the reading cycle is calculated by assuming that the memory cell has to charge a bit-line capacitor C_BL of 1pF.

Reading a binary 0, the bit-line capacitor has to be discharged via the transistor Q₁. The current flowing from the bit-line into the circuit should be low enough so that the voltage level of node X does not cross the switching point S_W. This current will increase with an increasing precharge voltage level on the bit-line. It means that the precharge voltage has an upper limiting voltage. For a precharge voltage level higher than the upper limiting voltage, the circuit becomes unstable and switches into the opposite binary state. The information in the memory cell will then be destroyed during readout. The reading "0" operation is shown in Fig.17.

Fig.17 Read “0” operation

Reading a binary 1, the bit-line capacitor is charged via the transistor M₄, and the load current will cause the node voltage Vx to full. To avoid the voltage level of node X crossing the switching point SW, the load current level should be higher. Therefore, during reading a binary 1, the precharge voltage level has a lower limiting voltage. The reading "1"

operation is shown in Fig.18.

Fig.18 Read “1” operation

3.3.3 Comparisons

Fig.19 shows comparisons of the transient analysis of read "0"

operation with respect to different load capacitances on the bit-line. Since the bipolar transistor is operated from cut-in to forward-active region, the proposed memory cell does not make too much difference on the delay time from conventional single-side CMOS memory cell for a small

bit-line capacitance. However, for a large bit-line capacitance, the proposed memory cell is superior to the conventional one because it owns large cell current. What can be noted is that for a heavily-loaded bit-line, the conventional memory is destructively read, i.e. its storage state is changed from "0" to "1" after read operation. On the contrary, the proposed memory cell maintains its trend on delay time toward a bit-line capacitance. Because the charges required for changing the state of the proposed cell from "0" to "1" are relatively large as compared with the conventional one, which are important for nondestructive read operation.

Fig.19 Sensing delay versus bit-line capacitance

Chapter 4

New Current-Mode Sense Amplifier

During the reading access cycle, the sense amplifier is one of the most critical element of memory circuit. The conventional sense amplifier is based on the voltage-mode technique, but its sensing time increases as the bit-line capacitance increases and its AC operation power consumption is very large. Several design techniques had been proposed to reduce the power dissipation of static RAM [54] in the past. On the other hand, several current-mode sensing circuits [55-57] had been proposed to overcome the problem of possible speed degradation due to larger bit-line or data-line capacitances.

4.1 Introduction

Due to their great importance in memory performance, sense amplifiers have become a very large class of circuits. Their main function is to sense or detect stored data from a read selected memory cell. Fig.20 shows a typical use of a sense amplifier.

Fig.20 Typical use of a sense amplifier

The memory cell being read produces a current "IDATA" that removes some of the charge (dQ) stored on the pre-charged bit-lines. Since the bit-lines are very long and are shared by other similar cells, the parasitic resistance "R_BL" and capacitance "C_BL" are large. Thus, the resulting bit-line voltage swing (dVBL) caused by the removal of "dQ" from the bit line is very small, i.e., dV_BL=dQ/C_BL. Sense amplifiers are used to translate this small voltage signal to a full logic signal that can be further used by digital logic.

The need for increased memory capacity, higher speed, and lower power consumption has defined a new operating environment for future sense amplifiers. Below are some of the effects of increased memory capacity and decreased supply voltage:

1) Increasing the number of memory cells per bit-line increases CBL, while an increase in length of the bit-line increases R_BL.

2) Decreasing memory cell area to integrate more memory cells in a single chip reduces the current I_DATA that is driving the heavily loaded bit-line. This coupled with increased CBL causes an even smaller voltage swing on the bit-line.

3) Decreasing supply voltage results in smaller noise margins which in turn affect sense amplifier reliability.

In this Chapter, new current-mode sense amplifiers will be presented and its ability to deal with these newly imposed operating conditions examined.

4.2 Voltage Sensing and Current Sensing

Current-sensing or current-mode as the name suggests is the sensing technique which determines the logic value present on a wire based on the current through the wire. The difference between current-sensing and voltage sensing is very subtle for conventional CMOS. As for MOS transistors, there is no current-threshold but they have a voltage threshold and hence, conventionally they determine the signal state by sensing the voltage.

4.2.1 Theoretical Model

Theoretically, a voltage-mode signaling can be modeled as shown in Fig.21. In the voltage mode, the driver drives interconnect and is terminated with an open circuit (RL≈∞). This allows the voltage at the destination to change based on the input voltage. The sensing circuit at the destination has to then figure out the signal state using this voltage value.

Fig.21 Theoretical voltage-mode signal model

However, in the case of current-sensing the signal is transmitted by a current pulse. The theoretical representation for current sensing would be shown in Fig.22. In a current-sensing, the driver drives a line which is terminated by a short (RL≈0). Hence, there exists a path for the current to flow and the sensing circuit at the end of the line has to detect this current to determine the signal value.

Fig.22 Theoretical current-mode signal model

As shown in Fig.23, the conventional way of signaling is voltage-mode. An inverter acting as a driver drives interconnect which builds up a voltage at the end of the line. Since the line ends in the gates of the transistors, R_L≈∞. The voltage sensing circuit is another inverter and since the MOS transistors have voltage thresholds to turn them on or off, the output of the inverter depends on the voltage at its gate. The

biggest challenge in current-mode signaling is to design an efficient sensing circuitry, which detects the change in current. A normal driver

can be used to drive interconnect and to drive current instead of voltage,

Fig.23 CMOS representation for a voltage-mode signal model

and the end of the line should provide a path to ground. Thus, a current-mode sensing setup would look like the one in Fig.24.

Fig.24 CMOS representation for a current-mode signal model

The main difference between the current-mode and voltage-mode signaling is the termination of interconnect. In the case of current-mode, the termination resistance is very small; while in the case of voltage-mode, it is very large. Since current is used as a mode of signaling in current-mode and there should be a path to ground from driver, static power dissipation is expected in current-mode signaling.

Also the receiving (sensing) circuit is complex in current-mode as MOS

transistors don't have a current threshold.

Also since there is a low impedance path to the ground at the end of the line, the capacitance of interconnect is not charged to Vdd but to an intermediate value. Since the sensing current in MOS is not very trivial, most of the current-mode sensing is done differentially. This may require some synchronizing (precharging or pre-equalizing) signal.

4.2.2 Voltage-Mode and Current-Mode Signal Delay

The use of current sensing amplifiers has a number of benefits over voltage sensing amplifiers. The most important ones are significant reductions in bit-line voltage swing and major reductions in sensing delays [58]. These benefits translate to lower dynamic power consumption and increased sensing speed. The key to these improvements lies in the low input resistance of the current sensing amplifier. This becomes evident when examining the equivalent sensing circuit in Fig.25.

Fig.25 A long interconnect model

In this model, we assumed that the output current is a linear-ramp signal as shown in Eq. (4-1), i.e.,

i

o=

p

o(

t-

^δ

t

) (4-1) where io is the output current, po is the constant slope, and δt is the delay.

The analysis shows that the delay for a line is given by the following equation:

where RT and CT are the total bit-line resistance and capacitance.

A voltage mode signal path, the RC line modeled in the above circuit is open circuit, it means that the resistor RL is extremely large. When RL

>> R_B, it can be assumed to be infinite in the above equation. Therefore, the time constant can be given by：

When we consider a current mode signal path behavior, the output loading of the long interconnect line is always a low resistance (ideally zero). Therefore, the RL modeled in Eq. (4-1) can be ignored, so the time constant can be given by：

δ

t ^{( )}

Fig.26 shows a comparison of voltage-sensing and current-sensing, Eq. (4-3) and Eq. (4-4). The figure shows that the current-sensing has less delay as compared to the voltage sensing. Actually, the load resistance for

current-sensing is not zero and so the effect of non zero load resistance should be studied. Fig.27 shows a comparison of the current-sensing with different load resistances.

Fig.26 Comparison of voltage sensing and current sensing

Fig.27 Comparison of voltage sensing and current sensing with different values of load resistance

As expected, an increase in load resistance increases the delay in the current-sensing technique, but the increase is not very significant for low resistance of interconnect and/or low resistance of the driver. The plots show that the delay in both current-sensing and voltage-sensing technique increases quadratically with respect to the length of the line (represented by the resistance of the line in the plots).

When we consider the long interconnect line signal path delay, we assume the source resistance is 1kΩ, and total capacitance distributed in the line is 1pF, and the total resistance of the line is 100Ω. The time constant of voltage mode signal path is 1.05ns. For the same assumption in current mode signal path, the time constant can be estimated to be 0.047ns.

We makes another approximation, since R_B>>R_T, the delay for voltage-mode can be approximated as RBCT. Also, the delay for current-mode can be approximated as R_TC_T/2 and since R_B>>R_T current-mode is faster than voltage mode.

A plot for comparing the voltage-mode and current-mode delay is shown in Fig.28.

Based on the above analysis, if the capacitance loading is independent, the time constant of long interconnection line can be reduced by reducing the loading resistance R_L. When the next stage is a voltage-mode circuit, it is always working as a capacitance loading.

Based on the above analysis, if the capacitance loading is independent, the time constant of long interconnection line can be reduced by reducing the loading resistance R_L. When the next stage is a voltage-mode circuit, it is always working as a capacitance loading.

在文檔中 以電流模式操作之低功率和高速率的靜態隨機存取記憶體 (頁 31-0)