Layout and Post Simulation Result

In this section I will present the layout diagram with UMC 90nm CMOS technology. It illustrate in figure 3.22. Note that I draw the layout by standard cell, so there has many restrictions like cell height and usable metal and position of input pin, output pin, even the Vdd and Gnd pins also exacting regulations. The standard cell restriction height in UMC 90nm CMOS technology is 2.5μm. The usable metal is only the metal one. Because of the restrictions of standard cell, it makes the layout more difficulties.

The layout view illustrate in figure 3.22, which is based on UMC 90nm CMOS standard cell rules. The total area is 2.5*5.32μm².

The table 3.4 showed post simulation results of power in LCSFF.

The table 3.5 and figure 3.23 showed post simulation of setup time and hold time of LCSFF.

Technology UMC 90nm CMOS Standard Cell

Supply Voltage 1.0

Clock Frequency 1GHz

Width 5.32μμμm μ

power00= 7.2492µW (previous data is 0 , new data is 0 ) power11= 6.9723µW (previous data is 1 , new data is 1 )

(compare with presimulation result +29.5%)

power01= 10.425µW (previous data is 0 , new data is 1 ) power10= 9.9499µW (previous data is 1 , new data is 0 )

(compare with presimulation result +34.2%) Table 3.4 the simulation result of LCSFF

Fig 3.22 The layout view of LCSFF in UMC90nm standard cell

Data low to

Table 3.5 The post simulation of setup time and hold time of LCSFF

Note that setup time result with FF (that means both NMOS and PMOS are fast type) in pre-simulation is negative numeral, but in the post simulation result, the numeral becomes positive after layout.

Fig 3.23 The post simulation of setup time and hold time

Chapter 4

Low Clock Swing Flip-Flop Design for Serializer/Deserializer in Network on Chip

4.1 Introduction

System-on-chip (SoC) designs provide the integrated solution to the challenging design problems in the multi-IP. System-on-Chip designs become more complex with numbers of transistors grow exponentially.[1-3]

Fig 4.1 Traditional Synchronous Bus

Traditional on-chip bus platform showed in Fig 4.1. The shared bus architecture will limit the development factor for increasing Internet Protocol (IP) blocks. The required on-chip communication bandwidth is growing beyond that provided by standard on-chip buses [4]. Existing bus architectures and techniques are unable to meet

leading edge complexity and performance requirements. In nanoscale technologies, increased coupling effect for interconnects not only aggravates the power-delay metrics but also deteriorates the signal integrity due to capacitive and inductive crosstalk noises. Several options were proposed to reduce the inter-wire capacitances:

1. To wide the pitch between bus lines.

2. Using P&R (place & route) tools to avoid routing of the bus lines side by side.

3. Changing the geometric shape of bus lines.

4. Adding a shielding line (VDD/Ground) between two adjacent signal lines.

5. Reducing power is through bus encoding schemes [5-7].

However, in SoC design, the interconnection and the routing is complex and is hard to do minimize the coupling capacitances. And the disadvantages of these methods are the increasing area since the cross-sectional area of a bus line is fixed.

On-chip physical interconnections will present a limited factor for performance and energy consumption. The encoding schemes for low power and reliability issues are proposed in [8][9]. Both the system design and performance are limited by the complexity of the interconnection between the different modules and blocks into single clocked design. Different data transfer speeds are required, as well as parallel transmission. The traditional system buses may not be suitable for such a system. The solution to above problems

is a segmented bus design combined with the concept of the globally asynchronous local synchronous (GALS) system architecture [10-12].

Asynchronous design can make the circuits resilient to delay variation.

The Network-on-Chip architecture as shown in Fig 4.2 is based on a homogeneous and scalable switch fabric network. The motivation of establishing NoC platform is to achieve performance using a system perspective of communication. The core of NoC technology is the active switching fabric that manages multi-purpose data packets within complex, IP laden designs. The most important characteristics of NoC architecture can be summarized as packet switched approach, flexible and user-defined topology and global asynchronous locally synchronous (GALS) implementation.

Fig 4.2 Network-on-Chip Architecture

A simple architecture of Network on Chip showed in Fig 4.3. Focus on physical layer and data-link design of NoC protocols. The goal is to achieve a low latency, low power and reliable interconnect

architecture. The architecture will apply to each transmission stages between two adjacent switches in network interface. The design of NoC protocols should consider each stage properties together to achieve better performance. Based on this concept, we adopt serialization technique to implement packet-based

transmission, which is the most significant difference of Network-on-Chip architecture to other architectures.

The traditional rail-to-rail voltage signaling will no longer suitable for low power interconnect design. Reducing signal swing can significantly reduce power consumption on link wires. However, as the technology led us to smaller voltage swings and larger coupling capacitances effect, it means power will be the most important issue in future. It should carefully design and tradeoff

Fig 4.3 A simple architecture of Network on Chip

PE

each metrics. To guarantee the reliability is a necessary and important issue especially in future nanometer design. According to this concept, we want to save more energy on link wires. The whole architecture should tolerant of process-variation and make sure the circuit’s functional work in different cases.

According to the ITRS (International Technology Roadmap for Semiconductors) prediction illustrated in Fig 4.4, the gate between the interconnection delay and the gate delay will increase to 9:1 with the 65nm technology [13]. Increasing of power dissipation by charging and discharging the interconnect wires on a chip. Soon the interconnect will domain the performance such as power consumption, speed, and area. It means that interconnection will affect the system more in future SoC design rather than logic circuits on a chip.

Fig 4.4 Interconnect delay and gate delay under different technology 100

Gate Delay (Fan Out 4) Local (Scaled)

Global with Repeaters Global w/o Repeaters

180 130 90 65