Logical effort model

The convention of a register-transfer level description of a design into an implementation in silicon starts with logic synthesis, which consists of technology independent optimization, followed by technology mapping. In the latter step, the design is mapped to cells belonging to the target library while optimizing one or more performance metrics, such as delay, area, or power.

High-performance designs use rich libraries, with multiple instances of each cell, which have various delay, area, and drive capabilities. Technology mapping has to identify not only the best logic functionalities of cells to be used to implement some logic but also the best instance of each selected cell.

Since the library cells may be repeated thousands of times during the digital design process, their quality determine the final product performance. The number of driving strengths available for each cell also, have a crucial impact on the design performance.

For instance, when a design is implemented by a single driving strength library, its performance degrades by up to 27%. This is compared to its performance when it is implemented using a library that uses three levels of driving strengths.

Hence, there is a need for multiple libraries for each technology process, which is impractical. The situation is exacerbated when there is a need for a diversity of libraries from different suppliers where each one has its own tools and documentations. As a result, virtual library concept has emerged as a solution for this problem.

Virtual library or library-free mapping terminology means, mapping the design’s Boolean functions to the transistor level directly instead of using pre-characterized cells. Usually, the Boolean functions in this mapping technique are realized using

Static CMOS Complex Gates (SCCGs). The number of SCCGs (Boolean functions) in a virtual library is determined by the allowed number of serially connected transistors.

The logical effort method is widely recognized as a pedagogical way allowing designers to quickly estimate and optimize single paths by modeling equivalently propagation delay and transition time.

4.2.1 Logical effort and gate sizing

In themethod of logical effort, the delay of a gate is estimated by modeling it as a linear function of the load being driven as

(4.1)

where g is the logical effort, h = CL/Ci is the electrical effort, CL is the path load capacitance, f = gh is the effort delay and p is the parasitic delay of the gate. This formulation separates the different components that contribute to the delay of a gate.

More importantly, it leads to a natural extension for estimating the minimum delay, ^D, of a path of logic as

^D = NF^1/N + P (4.2)

where F = GBH is referred to as the path effort, P as the path parasitic delay, and N as the number of gates on the path under consideration1. The path logical effort, G, is the product of the logical efforts of the gates on the path, and the path electrical effort, H, is the product of the gate electrical efforts. The minimum delay of (2) is obtained by distributing the path effort F equally to each gate on the path.

For the networks with loads off logical path, as shown in Fig.

4.6, branching effort b should be introduced. The branching effort b at the output of a logical cell.

(4.3)

where Con-path is the load capacitance of a logical gate along the considered path, and Coff-path is the load capacitance of a logical gate(s) off the path. The branching effort along an entire path B is the product of the branching effort at each of the stages along the path.

(4.4)

The path electrical effort can also be calculated as the ratio of output and input capacitances of the path. Consider Fig. 4.7, which shows a simple path of four gates—A, B, C, and D. Each of these gates have input capacitances CinA, CinB, CinC, and CinD and drive output capacitances CoutA, CoutB, CoutC, and CoutD,

respectively. The input capacitance of the path Cin is the input capacitance of gate A, and the output capacitance of the path CL is the output capacitance of gate D. The path electrical effort, H, the product of the gate electrical efforts, telescopes, since

Fig. 4.6: A logical path with branching

the input capacitance of each gate is the load capacitance of its input (e.g., cinC = coutB). Thus

(4.3)

The logical effort approach is well suited for estimating the minimum delay that can be achieved by sizing a path of logic if the electrical effort, H, of the path is known. The individual gate sizes that are required to achieve this minimum delay can be calculated as follows: Each gate is assigned a gate effort of f

= F^1/N . Starting with the gate at the output that drives a known load of CL, the size of each gate is successively determined. Since the logical effort g of a gate is fixed, if an effort delay f is assigned to a gate, the input capacitance cin that meets this effort delay can be calculated as

(4.4)

where cl is the load begin driven by the gate under consideration.

Fig. 4.7. Calculating the electrical effort of a path.

4.2.2 Logical effort design steps

There are a three-step process to size a logical path to a achieve a required time with minimized area.

First, determine the input capacitance of the logical path and calculate H and, F, and the optimal number of gates N. If N is greater than the actual number of gates, add buffers to the path to match N.

Second, Calculate pi and gi for each gate. Third, calculate and roughly estimate fanout for each gate. The calculation should start from the last gate towards the first gate (at the input). This allows a rough estimation of the transistor sizes for each gate where Ci is the input capacitance of the current gate and Ci+1 is the input capacitance of the next gate that is closer to the path output.

qi can also be calculated at this stage.

Cell- or library-based technology mapping is the process of binding a technology-independent logic level description of a circuit to a library of gates in the target technology. A dynamic programming algorithm based on tree covering has served as the basis of later technology mapping algorithms. This is a two-step algorithm.

In the matching step, matches for all gates are generated in an input-to-output traversal of the circuit, and the optimum match (based on its cost and the cost at its inputs) and the corresponding matches at the inputs are stored as the solution for that gate.

In the covering step, the solution for the entire circuit is generated by an output-to-input traversal of the circuit. At the primary outputs, the best match is selected, and the covering recurses on the inputs of this match.