6.1 Basic concept for proposed algorithm
Because the voltage of virtual-VDD mesh does not decrease as expected, patterns generated from our own ATPG will be inserted after the clock gated and power switches turns off. The patterns are the two time-frames test vectors. The values of the patterns for primary inputs are able to be different in two time-frames while the values of the patterns for pseudo primary inputs have to be equal in two time-frames since the clock is gated when testing the retention flip-flops. The test vectors of first time-frame cause some values of interconnects to become 0 and some values of interconnects to become 1. The test vectors of second time-frame make the values on the interconnects to rise if the test vectors of the first time-frame makes the values to 0 and the test vectors of the second time-frame make the value to 1.
The charges on virtual-VDD mesh are forced to those interconnects with rising value as Figure 6.1(a) shows. Similarly, the test vectors of second time-frame make the values on the interconnects to fall if the test vectors of the first time-frame make the values to 1 and the test vectors of the second time-frame make the values to 0.
The charges on those interconnects with falling value are forced to ground as Figure
17
18 6.1(b) shows. Repeat these two time-frames test vectors for a period of time; the values on interconnects will transit with the repeated test vectors. Therefore, the voltage of virtual-VDD mesh drops each time as the two time-frames test vectors repeated.
0 →1 Virtual-V
TT
+++
(a) VVDD to loading
1 →0 Virtual-V
U U
+++
(b) Loading to ground
Figure 6.1: Examples of discharge path for virtual-VDD mesh to ground.
From our observation that if the voltage of virtual-VDD mesh drops to about the threshold voltage, the transitions that are close to the primary inputs influence the virtual-VDD mesh’s voltage drop much effectively. The reason is that the values in the circuit become weaker accompany with the voltage drop of virtual-VDD mesh.
However, the voltage of the primary inputs are still integrated which makes the transitions of the primary inputs become the major sources for forcing the voltage drop of virtual-VDD mesh. Therefore, there are two steps for our approach. Before the voltage of virtual-VDD mesh drops to about the threshold voltage will be the first step, and after the voltage of virtual-VDD mesh drops to about the threshold voltage will be the second step. Generate a pair of test vector for the first step with our own SAT based ATPG in our approach. Moreover, regenerate a pair of test vector which all the primary inputs are transited for the second step with our own SAT based ATPG. Base on the problem formulation, the test vectors generated from these two steps are objective to maximize the total capacitance of the nets toggled.
19
Step 1 SAT Based ATPG
Simulation
.cnf
.spf
.tr0 .cap
.bench
.tr0 .pttn
Step 2 SAT Based ATPG
Simulation
.cnf
.spf .cap .bench
.pttn
Figure 6.2: Overview of SAT Based ATPG.
6.2 Overview of SAT Based ATPG
Since the SAT Based ATPG separate to two steps, the SAT based ATPG will require two constraint files (.cnf). In the first step, the constraint file only needs to describe all the pseudo primary inputs are not able to transit. However, in the second step not only all the pseudo primary inputs must be same as the first time-frame vector’s value, but all the primary inputs are set to transit. Therefore, the patterns generated in the first step as well as the constraint file are needed in the second step. Furthermore, in order to acquire the time for the voltage of virtual-VDD mesh reaches about threshold voltage, the waveform file generated from the first step is also needed in the second step. Figure 6.2 shows the overview of SAT Based ATPG, which indicates the overall flow of generating pattern needed.
20
• From power supply voltage to about threshold voltage:
– Step 1. Set the constraints for the SAT based solver (.cnf in step 1) to ensure that all the values of pseudo primary inputs will be solved to 0 or 1 in two time frames.
– Step 2. Using our algorithm with SAT based solver to solve a pair of patterns which maximize the total loading capacitance with transitions.
– Step 3. Fix all the values of pseudo primary inputs for the second iteration optimization.
• From about threshold voltage to very low voltage:
– Step 4. Add the constraints all the values of primary inputs needs to transit in two time frames (.cnf in step 2).
– Step 5. With the previous constraints, using our algorithm with SAT based solver again to acquire the optimized pattern.
6.3 Algorithm for maximizing the loading capacitance with transitions
Since we need to maximize the loading capacitance with transitions, we de-velop the greedy approach for our algorithm. For all interconnects in the circuit, sort all interconnects except the input ports in descending order. Pick the intercon-nect with the largest capacitance and try whether the value of this interconintercon-nect is able to be set to rising or falling with SAT solver or not. If yes, add the constraint of this interconnect to the SAT solver. If not, give up this interconnect and choose interconnect with the second large capacitance. Repeat the step mentions above until all interconnects except the input ports in the circuit are selected. Eventually,
21 with the solvable SAT constraints determined by the previous selection, many bits will be specified for the two time-frames test vector. For those bits of primary inputs are not specified in the first step will be set to 0 and in the second step will be set to transit (rising or falling). For those bits of pseudo primary inputs are not specified in both step will be set to 0. Figure 6.3 is the pseudo code for our algorithm.
01 begin
02 Add all Vs(Gates) to the Queue except primary inputs 03 Sort Vs’ capacitance in the Queue in descending order 04 for(i=0; n <= Queue.size(); i++)
05 Add V with rising value in SAT constraint 06 Solve the SAT constraints with SAT solver 07 if(not SATed)
08 Pop V with rising value out of SAT constraints 09 Add V with falling value in SAT constraint 10 Solve the SAT constraints with SAT solver 11 if(not SATed)
12 Pop V with falling value out of SAT constraints 13 end
Figure 6.3: The algorithm of maximizing the total loading capacitance with transitions.
Table 6.1: Result for proposed algorithm and exhaustive approach.
# of Selected Gate / Proposed Exhaustive Execution Circuit # of Gate Approach (pF) Approach (pF) Time (s)
s1196 10(50%)/358 0.282588 0.306928 18
s5378 93(75%)/1043 0.201127 0.210979 7267
s9234 115(75%)/1379 0.233793 0.233793 50379
s13207 57(75%)/2142 0 0 27
s15850 27(75%)/2711 0.473389 0.473389 3592
s35932 16(50%)/8243 1.42019 1.5117 7640
s38417 126(75%)/8256 0.236587 0.236587 977
s38584 18(50%)/9542 2.09441 2.09441 10520
Table 6.1 shows that the different between our algorithm and the exhaustive
22 approach for the capacitance of interconnects which larger than 0.75×(maximum capacitance+capacitance) or 0.5×(maximum capacitance+capacitance).
The capacitance of interconnects solved by our algorithm is closer to the exhaustive approach. Moreover, the column of execution time shows the exhaustive approach is very inefficiently.
Chapter 7
Experimental Results on Benchmark Circuits
7.1 Experiment setup
The benchmark circuits used in our experiments are the ISCAS benchmark circuits. The 65nm MTCMOS library is used in our experiment and the voltage of true-VDD is 1.2V. We set 0.5V for the voltage dividing two steps of generating patterns. Since we would like to observe the influence of the voltage of virtual-VDD
mesh with our test vectors, the waveform for the benchmark circuits-s13207 is pro-vided in Figure 7.1. Furthermore, we also provide other two methods of generating test vectors. For the first method(2 random values), we assign rising or falling to the primary inputs randomly. However, since the clock is gated when testing the reten-tion flip-flops, the pseudo primary inputs are only able to be set to value 0 or value 1 randomly. For the second method(4 random values), we assign value 0, value 1, rising or falling to the primary inputs and value 0 or value 1 to the pseudo primary inputs randomly. We random one thousand times based on these two approaches and select the best solution for the test vectors.
23
24
0 600 1200 1800 2400 3000 3600
voltage (volt)
time (ns)
Proposed approach 2 random values 4 random values
Second Step First Step
Figure 7.1: Waveform of 1.2V to the specify voltage with various ap-proaches.
7.2 The efficiency of our approach compares to the ran-domly assignment approaches
Table 7.1 shows the result for the total capacitance of interconnects with transitions that our SAT Based ATPG is able to solve. Some benchmark circuits show that the total capacitance interconnects with transitions of the second step will be less than the one of first step. This is due to the values of pseudo primary inputs of the second step must same as the first step while all values of primary inputs need to transit in the second step. From the last column shows that more primary inputs transit will not relate to higher total capacitance of interconnects with transitions.
Table 7.2 shows the comparison between our approach and two kinds of random value assignment approach above mentioned. The symbol (2) in the Table 7.2 represents the approach of assign value 0 or value 1 to the primary inputs and pseudo primary inputs randomly. Besides, the symbol (4) in the Table 7.2 represents the approach of assign value 0, value 1, rising or falling to the primary inputs and value 0 or value 1 to the pseudo primary inputs randomly. The solutions solved
25 from our approach are much better than any randomly assignment method in most ISCAS benchmark.
7.3 Improvement for speeding up the voltage drop of virtual-VDD mesh
Since as the voltage of virtual-VDD mesh drops to threshold voltage, the pMOS no longer makes the charges on the virtual-VDD mesh to interconnect, we present the result for the voltage of virtual-VDD mesh drops to 0.3V. Figure 7.1 shows the waveform simulation for benchmark circuits of s5378, s9234, s13207 and s15850. Note that using HSPICE[10] to simulate a test vector on the complete circuit of s15850 takes around 72 hours. To run similar SPICE simulation on a larger ISCAS circuit (such as s35932, s38417, or s38584) may take weeks or even months. Thus, we have already generated the test vector and computed the effect on capacitance of interconnects with transitions for s35932, s38417, and s38584 but we do not have the SPICE result for these three circuits. As Figure 7.1 shows that the test vector generated by SAT based ATPG performs better than the test vector which primary inputs and pseudo primary inputs assign randomly. Note that since the simulation time for without any test vector’s waveform is too long to reach the low voltage, this waveform is not shown in Figure 7.1. However, Table 7.3 shows the exact time for the voltage of the virtual-VDD mesh from 1.2V to the specify voltage including all primary inputs fix to value 0 or value 1 (without test vector). From Table 7.3, it is obvious that maximizing the loading capacitance with transition indeed reduces the time that the voltage of virtual-VDD mesh to the lower voltage.
The proposed algorithm performs much better than the patterns generated with inputs and pseudo inputs randomly assign. From Figure 7.1 and Table 7.2, we are able to observe that more capacitance of interconnects with transitions, the voltage
26 of virtual-VDD mesh drops to lower voltage much rapidly. Moreover, if all primary inputs fix to value 0 or value 1 (without test vector), the voltage of virtual-VDD
mesh drops extremely slow which leads the assumption of once the power switches turn off, the voltage of virtual-VDD mesh becomes 0 wrong.
27
Table 7.1: Experiment Result on ISCAS benchmark circuit with proposed algorithm.
Total Capacitance of Total Capacitance of Transition Bits /
# of # of # of Interconnects with Interconnects with Execution Time Execution Time Total Bits Circuit Switches FFs Gates Transition (pF) (1st step) Transition (pF) (2nd step) (s) (1st step) (s) (2nd step) (Primary Inputs)
s1196 2 18 385 0.842 0.816 1.24 1.38 0.571429
s5378 3 179 1043 0.783 0.567 9.6 12.1 0.828571
s9234 3 211 1379 1.067 0.777 18.77 22.04 0.777778
s13207 9 669 2142 0.466 0.466 23.86 82.54 0.903226
s15850 9 597 2711 2.175 2.175 72.83 123.32 0.714286
s35932 24 1728 8243 11.605 11.605 803.17 1271.61 0.457143
s38417 13 1636 8256 1.579 1.579 283.65 854.69 0.321429
s38584 24 1451 9542 15.245 15.245 904.19 1390.14 0.916667
Table 7.2: Comparison with primary inputs assign randomly method.
Random Test Vector(2) Random Test Vector(4) Average Average Proposed method/ Proposed method/
Circuit(Total Capacitance) (pF) (Total Capacitance) (pF) capacitance(2) (pF) capacitance(4) (pF) Random Test Vector(2) Random Test Vector(4)
s1196 0.745 0.634 0.573 0.431 1.13 1.328
s5378 0.387 0.392 0.26 0.21 2.023 1.997
s9234 0.496 0.409 0.349 0.231 2.151 2.609
s13207 0.14 0.103 0.1 0.05 3.329 4.524
s15850 1.13 1.154 0.92 0.468 1.925 1.885
s35932 11.446 11.402 10.736 5.582 1.014 1.018
s38417 1.109 1.009 0.713 0.355 1.424 1.565
s38584 13.76 13.675 13.433 6.83 1.108 1.115
Avg. - - - - 1.763 2.005
28 Table 7.3: Time for 1.2V to the specify voltage with various approaches.
s5378
Voltage of Virtual- Proposed Algorithm Random Test Random Test Without Test Random Test Vector(2)/ Random Test Vector(4)/ Without Test Vector/
VDD mesh (V) Test Vector (ns) Vector(2) (ns) Vector(4) (ns) Vector (ns) Proposed Algorithm Proposed Algorithm Proposed Algorithm
0.7 42 62 71 31100 1.476 1.69 740.476
0.6 54 98 97 42000 1.815 1.796 777.778
0.5 77 125 125 53900 1.623 1.623 700
0.4 132 202 242 68300 1.53 1.833 517.424
0.3 355 538 803 86700 1.515 2.262 244.225
Avg. - - - - 1.592 1.841 595.981
s9234
Voltage of Virtual- Proposed Algorithm Random Test Random Test Without Test Random Test Vector(2)/ Random Test Vector(4)/ Without Test Vector/
VDD mesh (V) Test Vector (ns) Vector(2) (ns) Vector(4) (ns) Vector (ns) Proposed Algorithm Proposed Algorithm Proposed Algorithm
0.7 40 71 82 34400 1.775 2.05 860
0.6 48 82 110 45600 1.708 2.292 950
0.5 64 92 150 59600 1.438 2.344 931.25
0.4 119 200 310 76200 1.681 2.605 640.336
0.3 550 780 1250 96100 1.418 2.273 174.727
Avg. - - - - 1.604 2.313 711.263
s13207
Voltage of Virtual- Proposed Algorithm Random Test Random Test Without Test Random Test Vector(2)/ Random Test Vector(4)/ Without Test Vector/
VDD mesh (V) Test Vector (ns) Vector(2) (ns) Vector(4) (ns) Vector (ns) Proposed Algorithm Proposed Algorithm Proposed Algorithm
0.7 140 494 660 38400 3.529 4.714 274.286
0.6 182 639 850 51100 3.511 4.67 280.769
0.5 251 820 1100 66000 3.267 4.382 262.948
0.4 481 1320 1740 84100 2.744 3.617 174.844
0.3 1780 4000 4220 106000 2.247 2.371 59.551
Avg. - - - - 3.06 3.951 210.48
s15850
Voltage of Virtual- Proposed Algorithm Random Test Random Test Without Test Random Test Vector(2)/ Random Test Vector(4)/ Without Test Vector/
VDD mesh (V) Test Vector (ns) Vector(2) (ns) Vector(4) (ns) Vector (ns) Proposed Algorithm Proposed Algorithm Proposed Algorithm
0.7 41 71 64 35600 1.732 1.561 868.293
0.6 51 94 88 47500 1.843 1.725 931.373
0.5 74 129 120 61600 1.743 1.622 832.432
0.4 293 433 379 78500 1.478 1.294 267.918
0.3 1690 2600 2330 987000 1.538 1.379 58.402
Avg. - - - - 1.667 1.516 591.684
Chapter 8 Conclusion
In this thesis, we point out two issues in testing retention flip-flop. First, since the characteristic of retention flip-flop, the value saved in the balloon must opposites to the value of pin Q before the retention flip-flop sleeps in order to cover the faults of the retention flip-flop. Second, we have proposed a SAT based ATPG for forcing the voltage of virtual-VDD mesh to reach the low voltage without redundant device.
The experimental results based on a current MTCMOS technology demonstrated testing for retention flip-flops are able to be more robust and efficient with proposed ATPG framework.
29
Bibliography
[1] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, ”Low-Power CMOS Digital Design,” IEEE Journal of Solid-State Circuits, vol. 27, No. 4, pp. 473-484, Apr., 1992.
[2] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, ”Leakage Current Mecha-nisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits,”
Proceeding of the IEEE, vol. 91, No. 2, pp. 305-327, Feb., 2003.
[3] J. Kao, S. Narendra, and A. Chandrakasan, ”Subthreshold Leakage Modeling and Reduction Techniques,” IEEE/ACM International Conference on Computer Aided Design, pp.141-148, Nov., 2002.
[4] S.-P. Mu, Y.-M. Wang, H.-Y. Yang, Mango C.-T. Chao, S.-H. Chen, C.-M. Tseng, T.-Y. Tsai, ”Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs,” IEEE/ACM International Conference on Computer Aided Design, pp.155-161, Nov., 2010.
[5] S.K. Goel, M. Meijer, and J. Pineda de Gyvez, ”Efficient testing and diagnosis of faulty power switches in SOCs,” Computers & Digital Techniques, IET, vol. 1, No.
3, pp. 230-236, May, 2007.
[6] S. Khursheed, S. Yang, B. M. Al-Hashimi, X. Huang, D. Flynn, ”Improved DFT for Testing Power Switches,” European Test Symposium(ETS), pp. 7-12, May, 2011.
[7] N. B. Zain Ali, M. Zwolinski, B. M. Al-Hashimi, ”Testing of Level Shifters in Multiple Voltage Designs,” IEEE International Conference on Electronics, Circuits and Systems, pp. 435-438, Dec., 2007.
[8] P. Girard, N. Nicolici, X. Wen, ”Power-Aware Testing and Test Strategies for Low Power Devices,” Springer, 2009.
[9] B.-C. Bai, A. Kifli, C.-M. Li, K.-C. Wu, ”Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs,” Asia and South Pacific Design Automation Conference, pp. 684-689, Jan., 2009.
[10] Synopsys, HSPICE, version C-2009.03-SP1.
[11] Synopsys, DC version C-2009.06-SP5-2.
30
31
[12] Cadence, Encounter version 8.1.
[13] Synopsys, Hercules, version B-2008.09.SP3.HF3.24036.
[14] Synopsys, StarRCXT, version 2007.06.SP1-5.