Chapter 4 Fabrications
4.2 Making the alignment marks for EB lithography
4.2.1 Background
As mentioned before, the delay distance between PCs and IDTs is a critical factor to the performance of the resonator, thus the alignment of the two times of EB lithogra-phy (i.e. IDT and PC) should be executed precisely. Our substrate was a 20 mm × 20 mm × 0.5 mm quartz wafer. As shown in Fig. 4.3 , 4 copies of the same layout were on it. Each of them contained 4 different layouts; each of them will be called a “chip” in the following. So we had 16 chips on a single wafer, which the chip had a size 2.5 mm
× 2.5 mm. As reported [56], with alignment to a set of global wafer marks, the align-ment tolerance is about 0.5 µm. However the tolerance was required to be less than or-der of 10-1 of the wavelength, or, less than 0.3µm, and the less the better. Also knowing that the best tolerance (< 0.1 µm) can be achieved when the alignment marks are within several hundred micrometers of the critical region [56], thus alignments should be car-ried out for every single chip writing, with alignment marks around each chip.
Unlike the optical alignment for photolithography, there were requests for align-ment marks used in EB lithography. Since the instrualign-ment detected the mark position by emitting EB and receiving scattered electrons, the marks should be made by materials with high atomic numbers such as tungsten, platinum, or gold, or, made by deeply etched patterns [56]. Unfortunately, the IDT layer which made by 100nm thick of alu-minum was inadequate for alignment marks, so a “0th layer” with alignment marks only should be fabricated before any actual device structure was made. The mark material
was chosen to be 150-nm-thick gold, which provided a strong reflection signal when being scanning.
The wafer marks were large crosses of width 3 µm and length 1000 µm, placed at the top, bottom, left, and right sides of the wafer. They were used to correct overall po-sition shift, rotation, and gain of the wafer, and helped finding the smaller chip marks, while the chip marks corrected shift, rotation, and gain for individual chip exposure.
We found that the alignment marks scanned in IDT layer alignments became un-usable after deposition of SiO2. The reason was that the EB resist on scanned region was exposed (by scanning EB), aluminum remains after lift-off, and after high temper-ature SiO2 CVD process, aluminum and gold formed intermetallic compounds, so the marks could not be used anymore as shown in Fig. 4.17, Fig. 4.18 . To address this, 3 sets of chip marks were made. One for IDT alignment, one for PC alignment, and a backup, as Fig. 4.18.
4.2.2 Process and parameters
The alignment marks was made by lift-off technique with EB lithography. The reason of lift-off but not etching method was that a much shorter EB writing time was required. The procedure is detailed as below, and the process chart is shown in Fig. 4.4.
1. Cleaning
The quartz wafer received from the supplier was first cleaned by 1:1 mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) solution, left to stand for several hours, then rinsed by de-ionized water (DI water) for several times. After that, the wafer is spin-dried and baked in a 145 °C oven for more than 20 minutes to remove the water.
2. Spin coating of OAP, EB resist, and ESpacer
Before coating of the chemicals, a dehydration baking at 180 °C for 3 minutes on a hot plate was applied. After cooling, OAP (also known as HMDS, 1,1,1,3,3,3-Hexa-methyldisilazane) was spin-coated at 3000 rpm and then baked at 180 °C for 3 minutes on a hot plate. It acted as an adhesion promoter between the EB resist and the quartz substrate. After cooling, EB resist ZEP520A was coated at 3000 rpm, and pre-baked at 180 °C for 3 minutes to remove the solvent from the resist. ZEP520A is a high resolu-tion positive EB resist with high dry etching resistance. But here it was used for a lift-off purpose. After cooling down, the anti-charging layer ESpacer 300Z was coated at 2000 rpm, and then baked on a 70 °C hot plate for 3 minutes.
3. EB writing
The coated wafer was then sent into the chamber of EB lithography. Before enter-ing the clean room, a job deck file, a schedule file, and the CAD file in GDSII format were already prepared, where the job deck file and the schedule file contained the EB writing parameters such as the arrangement of the patterns, the dose time, the mark in-formation, the cyclic calibration setup, and the electron optical system type, while the CAD file contained the writing patterns. After the file conversion and a rigorous cali-bration of the instrument including adjusting the beam current, correction of focus and astigmatism, etc., the patterns were written on the substrate with the EB. The exposure current was set to be 100 pA, and the acceleration voltage was 50 kV. The best dose value determined to write this pattern under this conditions is 71.2 µC/cm2, or, in words of actual writing parameters, pixels with a pitch 0.00125 µm and a skip number 4 are exposed by the EB for 178 ns. The total writing took about 2.5 hours.
4. Development
After exposure, the sample was rinsed by DI water in a beaker 30 seconds for 3
times (with clean DI water every time) to remove the ESpacer on the EB resist, then developed in the developer ZED-N50 at 23 °C in a temperature controlling water bath for 2 minutes shown in Fig. 4.25. It was then rinsed in methyl isobutyl ketone (MIBK) for 1 minute to purge it from the developer. After, the sample is blow-dried with a com-pressed N2 gun and baked on a 110 °C hot plate for 3 minutes. The Scanning electron microscope (SEM) pictures of a developed pattern are shown in Fig. 4.19.
5. Deposition of Au/Ti
Before the metal deposition, 30 seconds of O2 plasma ashing (operation pressure:
200 Pa, RF power: 130 W) was applied to ensure no residual resist on the developed area. After, the sample was put into the deposition chamber; a cryopump vacuumed the chamber to a high vacuum (less than 8×10-6 Torr). Then the metal was deposited by EB evaporation method – which has bad ability of stage coverage compared with sputtering method, but it becomes an advantage in lift-off purpose. A calibrated AT-quartz vibra-tion thickness gage was used to monitor the deposited metal thickness. 100 Å of titani-um was first deposited on the chip as an adhesion layer; 1500Å of gold is then deposited.
The acceleration voltage of the EB is controlled from 2.5 kV to 3 kV, and the current ranges from 20 mA to 100 mA to adjust the deposition rate. Photographs of the EB evaporator are shown in Fig. 4.26.
6. Lift-off
The sample was immersed in Microposit Remover 1165 (contains 95% of
N-Methylpyrrolidinone (NMP)) at room temperature for more than 12 hours (or heated
to 70 °C, with agitation, shorten to 1~2 hours) for lift-off. ZEP520A was dissolved and therefore the metal on the resist is removed. Then the sample was cleaned by isopropyl alcohol (IPA) with ultrasonic vibration. Before it dries, it was cleaned by IPA and waterjet spray to prevent metal particles from reattaching to the wafer.