CHAP 3. A 0.35-µm SiGe BiCMOS 5.25 GHz LNA
4.2 Measurement Consideration
The network analyzer only could execute 2 port measurements. Measurement condition must connect the Balun and transfer two differential ports to one port for differential mixer testing. This chip is bonded wires to microwave circuit board for testing. The Balun blocks split the input power to differential signal and the loss of cable, Balun, SMA connector and board must be taken account. Layout of PCB and reality PCB circuit with SMA connectors are shown as Fig4.2.1 and Fig4.2.2.
Fig 4.2.1 PCB layout
Fig4.2.2 Reality PCB circuit
Each measurement setup is shown in figure 4.2.3. They are output power;
50 Ohm Line
RF
LO IF
We use RFIC measurement system in CIC to complete. The wide band Balun blocking (4GHz-8GHz) is provided by CIC.
(a)
(b)
(c)
Fig 4.2.3 Measurement setup of (a) Conversion Gain (b) Two-tone IIP3 testing (c) Input return loss testing
The reality measurement picture is shown in Fig 4.2.4 which include of the mixer, PCB, Balun and cables.
Fig 4.2.4 Measurement picture
To find out the loss of each component, and confirm if the loss would affect the circuit performance, we utilize the 50 Ω line testing board to do the loss testing. The loss of board and SMA connectors are about 0.3dB. The reality picture and measurement result are shown in Fig4.2.5 and Fig 4.2.6, respectively. Furthermore, the cable and Balun loss data could be sum up in CIC RFIC measurement system.
Fig4.2.5 Loss testing board
Fig 4.2.6 The measurement results of loss; about 0.3dB
4.3 Simulation and Measurement results comparison
Fig4.3.1 is showed the simulation and measurement results of input return loss.
(a) The simulation of input returns loss
(b) The measurement of RF port input returns loss
(c) The measurement of LO port input returns loss
The measurement input return loss of the RF port and LO port are 12.9dB and 13.1 dB, which are closed to the simulation result; 15.4dB and 17.6dB, respectively.
One of an important reason should that we use several bonding wires to reduce the variation of the inductance, the impedance of matching network does not have obvious shift, Fig 4.3.2 is illustrated the bonding wires.
Fig 4.3.2 The bonding wire And the mixing test is showed as Fig 4.3.3.
Fig 4.3.3 RF power =-35dBm @5GHz, LO power = 0dBm@ 4.99GHz, IF=10MHz Differential LO PAD Each pad 2 bond wires
Differential RF PAD Each pad 3 bond wires
Fig 4.3.4 and Fig 4.3.5 are illustrated the conversion gain versus the LO input power and the conversion gain versus the RF input power, respectively.
Fig 4.3.4 Conversion gain versus the LO input power
Fig 4.3.5 Conversion gain versus the RF input power
Fig 4.3.6 is shown the two-tone testing (5.001GHz and 5GHz) and IIP3.
Fig 4.3.6 Comparison between simulation and measurement of IIP3
The measurement performance of conversion gain is not good as simulation. The difference is about 7dB, we take the analyses into two parts; Gm and output impedance matching. A simplified amplifier circuit is illustrated as Fig4.3.7.
Fig 4.3.7 A simplified circuits; Vbias means lowest layer device bias voltage (bias current is domain by lowest layer active device; BJT), Gm means the total transconductor of core circuits, 50Ω is the instrument impedance.
Fig 4.3.8 and Table 4.3.1 are shown the characteristic of bias voltage versus the current; we could obtain the Gm value.
Fig 4.3.8 The characteristic of bias voltage versus the current
Bias Voltage (v) Simulation Current (mA) Measurement current (mA)
0.9 0.73 0.74
0.92 0.87 0.95
0.94 1 1.16
0.96 1.14 1.39
Table 4.3.1 The bias voltage versus the current
This transconductor effect would attenuate about 4dB conversion gain performance.
dB
Av ) 4.0
83 . 10
83 . log(6
20⋅ =−
= (4.12)
Subsequently, we would discuss the output matching. If the output impedance is not equal to 50Ω, even larger than 50Ω, the output power could not deliver to load efficiently. Fig 4.3.9 is shown the consideration of output impedance.
Simulation Gm = (1.39-0.74) (mA)/ (0.96-0.9) (V) = 10.83 m (1/Ω) Measurement Gm = (1.14-0.73) (mA)/ (0.96-0.9) (V) = 6.83 m (1/Ω)
Fig 4.3.9 The buffer output impedance consideration;
Rout = 1gm
The simulation value and measurement is as follow table 4.3.2, and we obtain process parameter;
Table 4.3.2 Comparison between simulation and measurement of Rout
The impedance of instrument is about 50 Ω; the larger output impedance would affect the power deliver (A diagram in Fig4.3.10). From the equation, this mismatch would attenuate about 0.9dB conversion gain performance.
dB
Fig 4.3.10 A diagram of Rout and 50ohm load Table 4.3.1 is the summary of the performance of this circuit.
Specifications Simulation Measurement
Supply Voltage (V) 2.5 2.5
core 2.04mA / 5.1mW 2mA / 5mW
buffer 2.42mA / 6mW 1.9mA / 4.8mW
Power Consumption
( mA/mW ) total 11.1mW 9.8mW
DSB_NF (dB) 6.8 N/A
RF Input Power (dBm) -35 -35
LO Input Power (dBm) -3 1
1MΩ Load 18 N/A
Conversion
Gain (dB) 50Ω Load 6.3 -0.9
RF Input Return Loss(dB) 15.4 12.9
LO Input Return Loss(dB) 17.6 13.1
IF Input Return Loss(dB) 14.6 N/A
P1dB (dBm) -25.1 -16
IIP3 (dBm) -15 -5
LO-RF Leakage -70 <-30
Table 4.3.3 The summary of performance
The loss of cable, connector and Balun would be account in CIC RFIC measurement system. From the above discuss of transconductor and output matching impedance, we could find out the reasons between the different of simulation and measurement results.
6.3dB (simulation conversion gain) – 4dB (transconductor effect)
– 0.9dB (output matching impedance) – 0.3dB (loss of board and connectors)
= 1.1dB ≒ -0.9 dB (measurement conversion gain)
There are a little different from the above equation, because we could not consider the 50Ω high frequency signal impedance matching of bonding wires effect, illustrated in fig4.3.11.
Fig4.3.11 The bonding wires effect
Besides, the experimental 1dB point and IIP3 are greater than the simulation. The trade-off between power gain and the linearity under fixed biasing condition is the criterion for amplifier design. Because the gain of measurement is lower than the expected, the performance of linearity is greater than expected one. The simulation P1dB and IIP3 are -25dBm and -15dBm, respectively, and measurement results are -16dBm and -5dBm.
The follow table 4.3.4 shows the comparison of recently papers. Table 4.3.4 Comparison of recently papers
The performance of gain is not as good as recently reports, because the output load of this work is 50 Ω, the others are not; the circuits connect with other stage, load is larger than 50 Ω. This work is a directly down conversion topology, and we set the IF is 10MHz for conveniently measurement.
Chapter 5
Conclusion
5.1 Conclusion
This thesis contents two works. The first work is a SiGe 0.35um 5.25GHz cascode LNA. The second work presents a SiGe concurrent 5GHz LNA and mixer. In this thesis, we have presented the design concepts and simulation verse experimental comparison results.
Nowadays, there are several papers provide the RF front-end circuits around the 2.4GHz and even up to 5GHz band. We try to upgrade the RF front-end circuits to 5GHz band and prove that it works at high frequency well. The difficult key points of this circuit are high frequency operation and the integration. However, we have faced these difficulties and design a signal stage LNA and concurrent front-end circuits in this work. We can see this fact in the simulation and measurement comparison results in chapter3. Although the performance does not meet our expectation, we can improve it by modeling the passive components or replacing by off-chip elements.
The full-integrated single chip LNA circuit consists: 7.5mW power consumption, a 4.6dB power gain, a 9.3dB NF, a 3.8dBm IIP3, -6.5dBm Pout-1dB, an 8.3dB input return loss and 10.9dB output return loss. The LNA design concepts and experimental results are proposed here. Besides, we also discuss the reasons about the differences between simulation and measurement results in each circuit. All of the performance was simulated by Eldo-RF at 5.25GHz. This IC has been fabricated using TSMC 0.35-µm BiCMOS SiGe foundry through CIC. And the measurement was done using on-wafer testing at RF probe station at NDL.
A concurrent SiGe LNA and mixer with low power are presented at 5GHz. It designed with off-chip inductors to approach measurement conveniently. The circuits has a -0.9dB gain, a -5dBm IIP3, a -16dBm Pout-1dB, a 12.9dB RF input return loss, a 13.1dB LO input return loss and about 10mW power consumption.
We can compare the simulation and experimental results and we can find its differentia and the reasons. Simulation results present better performances than measurement results. It may because buffer output matching impedance and the transconductor effect to cause the variations. This IC has been fabricated using TSMC 0.35-µm BiCMOS SiGe foundry through CIC and measurement is done by on-board testing at CIC.
5.2 Future Progress
At 5GHz high frequency application, we must build up more RF BiCMOS components’ models such as the large capacitance MIM capacitors, spiral inductors and different inductance spiral inductors for exactly matching in future design. We would try to improve the differentia between the simulations and measurement results by more accurate components models. And we will integrate the 5.25GHz front-end with other RF or Mixed-signal parts such as filters, switch, and synthesizer of the receiver to make progress to SOC target.
In the second work, concurrent LNA and mixer, the performance is not as good as simulation. To implement large inductance and capacitance values, the multi-layers stacked spiral inductors and MOS varactor capacitors are employed. [6] We could increase the passive components models to forward the circuits performance. And we could change the architecture to reduce a number of passive large value components such as inductors and capacitors [26] (shown in Fig 5.2.1).In the original topology, the bypass large capacitor is coupling the RF output voltage signal to mixer. The LNA stage transfers input RF voltage signal to current and mix with LO signal without more passive components in proposal architecture. This one could redeem the insufficient passive models to achieve better performance.
Fig 5.2.1 A merged LNA and mixer
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