Spread Spectrum Clocking
5.3 Measurement Environment Setup
The testing environment setup is shown in Figure 5.7. All DC supply sources are given from Keithley 2400 Source Meter. Agilent N4903A Serial J-BERT provides the jittery and spread spectrum clock receiver data for CDR testing. It also
(a) 1st-order Σ∆ modulation
(b) 2nd-order Σ∆ modulation
(c) 3rd-order Σ∆ modulation
Figure 5.3: Period of VCO output waveform vs. time.
Figure 5.4: The spectrum of VCO output under different order modulation.
Figure 5.5: Spectrum of VCO output clock with and without spread spectrum modulation.
Figure 5.6: Layout view of test chip.
Table 5.1: Design summary of proposed CDR
Process 90nm 1P9M CMOS
Data Rate 6Gb/s
Supply 1V
Power
CDR 6mW
(digital: PD.Filter Proportional/Integral path)
CDR 41mW
(analog: interpolator.sampler.Mux.)
Active Area 220 × 320(µm × µm)(digital)
Gate Count : 24946 240 × 380(µm × µm)(analog)
Recovered 54.420ps @PJ, Amp=0.18UI(P2P), Freq=1 MHz
Clock Jitter 17.516ps @RJ, σ=0.02UI
Frequency Tolerance +/−1000ppm
SSC Tracking +/−5000ppm 33KHz
Table 5.2: Design summary of proposed SSCG
Modulation Frequency 33KHz
Max. Frequency Deviation 4983ppm
Active Area 240 × 180(µm × µm)(SSCG and PLL) 270 × 220(µm × µm)(Loop filter)
EMI reduction 20.6dB
Jitter performance 1.3ps (P2P)
Power 7.57 mW
provides the reference clock for PLL in spread spectrum clock generator. In order to measure BER, we use a BIST in the test chip that generates a waveform whose duty cycle is proportional to the accumulated error bits. This signal is the Error Signal. Tektronics TDS6124C Digital Storage Oscilloscope is used to measure the waveform of Error Signal. Tektronics TDS6124C Digital Storage Oscilloscope also measures the waveform and jitter of CDR recovered clock and recovered data. Agilent E4440A Spectrum Analyzer is used to measure the spectrum of CDR recovered clock and the output result of spread spectrum clock generator.
Agilent E4440A Spectrum Analyzer Keithley 2400
Source Meter
Agilent N4903A Serial BERT
DC Supply
RX Data
PLL Ref
Error signal
Recovered Data Recovered
Clock
SSC Clock
Tektronics TDS6124C Digital Storage
Oscilloscope
Figure 5.7: Test Environment Setup.
Chapter 6 Conclusions
Schemes improving CDR loop bandwidth stabilization includes Majority Vote, M-AES, and Gain Compensation are proposed. The CDR conforms to SATA gen-eration 3 specifications. The CDR is a dual loop architecture that is suitable for multi-channel integration without the need of extra PLLs for different channels.
The 2nd-order digitally implemented phase tracking algorithm is programmable for different jitter conditions and can track spread spectrum clock transmission.
The proposed Gain Compensation technique eradicates the unwanted side effects of binary phase detection and enhance the performance during various data tran-sition density. The CDR meets the specification of jitter quantity and spread spectrum clock of SATA-III and the specification of jitter tolerance mask of SDH STM-64 interface. The CDR is implemented in UMC 1P8M 90nm 1.0V Regular-Vt CMOS technology.
The other objective of this thesis is the effect of different order of Σ∆ mod-ulation. Our theoretical results have shown that, once the phase resolution of the interpolator is high enough, the difference of the jitter from different order modulators is so insignificant that can be neglected. Whereas the resolution of interpolator in our work is high enough, in an effort to reduce the hardware com-plexity, there is no reason to choose the higher-order Σ∆ modulator to control the amount of the phase rotator. The result indicates that, unlike other cases,
the effect of higher-order modulation does not apply in our work. Table 6.1 shows the comparison with other SSCG.
Table 6.1: Design summary of proposed SSCG
Proposed SSCG ISSCC2005 ISSCC2005 ISSCC2006
(Simulated) [33] [41] [30]
Technology 90nm 0.18µm 0.15µm 0.15µm
Modulation Phase Phase Modulation Modulation
Mechanism Rotation Selection on Divider on Input
Divider Ratio 12 60 37.5/75 —
Operating 1.2GHz 1.5GHz 1.5GHz 27MHz
Frequency (ref. clock)
Frequency 5000ppm 5000ppm 5000ppm 30000ppm
Deviation (6MHz) (7.5MHz) (7.5MHz)
EMI Reduction 20.6dB 9.8dB 20.3dB 14dB
EMI Reduction/BW 3.43dB/MHz 1.3 dB/MHz 2.7 dB/MHz
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