Chapter 2 Experimental of the Novel Structure of LTPS
2.3 Methods of Device Parameter Extraction
In Fig. 2-2(a), we could see clearly the top-view of the proposed structures.
LMC, Lo,d and Lo,s represent the length of main channel , gate-overlap in the drain and gate-overlap in the source, respectively. We suggest that the current transmission mechanism might have another path of current transmission compared with conventional sample. Because it’s width would be increased by staggered source/drain regions (W’>W), the novel TFTs appear to be promoted more effectively on-state current.
In Fig. 2-2(c), we see that the B-B’ cross section of the novel structures compared to the conventional would increase additional poly channel.
2.3 Methods of Device Parameter Extraction
Many methods have been proposed to extract the characteristic parameter of
Poly-Si TFT. In this section, the methods of parameter extraction used in this research are described.
2.3.1 Determination of Threshold Voltage (Vth)
The threshold voltage Vth is an important MOSFET parameter required for the channel length-width and series resistance measurement. However, Vth is a voltage that is not uniquely defined.Various definition exist and the reason for this can be found in the ID-VGS curves. One of the most common threshold voltage measurement technique is the linear extrapolation method with the drain current measured as a function of gate voltage at a low drain voltage of typically 50-100 mV to ensure operation in the linear MOSFET region [2]. But the drain current is not zero below threshold and approaches zero only asymptotically. Hence the ID
verus VGS curve is extrapolated to ID=0, and the threshold voltage is determined from the extrapolated or intercept gate voltage VGSi by
V = th VGSi 2 VDS
− (Eq. 2.1)
Equation (2.1) is strictly only valid for negligible series resistance. Fortunately series resistance is usually negligible at the low drain currents where threshold voltage measurement are made. The ID-VGS curve deviate from a straight line at gate voltage below Vth due to subthreshold currents and above Vth due to series resistance and mobility degradation effects.
It is common practice to find the point of maximum slope on the ID-VGS curve by maximum in the transconductace fit a straight line to the ID-VGS curve at that point and extrapolate to ID=0.
2.3.2 Determination of Subthreshold Swing
Subthreshold swing S.S (V/dec) is a typical parameter to describe the control ability of gate toward channel. That is the turn on/off speed of a device. It is defined as the amount of gate voltage requires to increase/decrease drain current by one order of magnitude.
The subthreshold swing should be independent of drain voltage and gate voltage.
However, in reality, the subthreshold swing might increase with drain voltage due to short channel effect such as charge sharing, avalanche multiplication, and punchthrough effect. The subthreshold swing is also related to gate voltage due to undesirable and inevitable factors such as serial resistance and interface state.
In my thesis, the subthreshold swing is defined as one-third of the gate voltage required to decrease the threshold current by three orders of magnitude. The threshold current is specified to be the drain current when the gate voltage is equal to threshold voltage.
2.3.3 Determination of Field Effect Mobility (µFE)
Usually, µFE is extracted from the maximum value of transconductance (gm) at low drain bias (VDS=1V). The drain current in linear region (VDS<VGS-Vth) can be approximated as the following equation:
where W and L are width and length, respectively. C is the gate oxide capacitance. ox Thus, gm is given by
FE ox DS
2.3.4 Determination of On/Off Current Ratio
On/Off current ratio is one of the most important parameters of poly-Si TFTs Since a good performance means not only large On current but also small Off (leakage) current. The leakage current mechanism in poly-Si TFTs is not like it in MOSFET. In MOSFET, the channel is composed of single crystalline and the leakage current is due to the tunneling of minority carrier from drain region to accumulation layer located in channel layer region.
However, in poly-Si TFTs, the channel is composed of poly crystalline. A large amount of trap densities in grain structure attribute a lot of defect state in energy band gap to enhance the tunneling effect. Therefore, the leakage current due to the tunneling effect is much larger in poly-Si TFTs than in single crystalline devices. When the voltage drops between gate voltage and drain voltage increase, the band gap width decrease and the tunneling effect becomes much more severe. Normally we can find this effect in typical poly-Si TFT ID-VG
characteristics where the magnitude of leakage current will reach a minimum and then increase as the gate voltage decrease/increase for n/p-channel TFTs.
There are a lot of ways to specify the On and Off current. In my thesis, take n-channel poly-Si TFTs for examples, the On current and Off current is defined as the drain current when gate voltage equal to 15V and drain voltage is 1 V(linear operation mode). The Off
current is specified as the minimum leakage current in linear operation mode for usual cases.
[1] I. W. Wu, “Low temperature poly-Si TFT technology for AMLCD application,” in Tech.
Dig. AMLCD, 1995, pp. 7-10.
[2] Dieter K. Schroder, “Semiconductor Material and Device Characterization,”
Wiley-INTERSCIENCE, 1998.
Chapter 3
The Characteristics of Novel Gate-Overlapped Low-Temperature Poly-Si TFTs with Stagger
Source/Drain Regions
In this paper, we will discuss the device performances of Poly-Si TFTs with different structures including traditional TFTs as shown Fig 3.1 and Novel TFTs we proposed. In addition, we make three different ranges in overlapped gap about novel TFTs we proposed. In later sections, Long (OL) and small (OS) size gate overlap length have been compared. We define gate-overlapped length Lo. N&k analyzer, and the I-V characteristics of Poly-Si TFTs by HP4156 semiconductor parameter analyzer measured the thicknesses of the films.
3.1 The Electrical Properties of Novel TFTs and Conventional