Mobility Measurement by Split CV

Split CV is one of the most commonly used techniques for measuring MOSFET inversion layer mobility. The effective inversion channel electron mobility (µ_eff ) and

the effective field (E ) were extracted from current-voltage and capacitance-voltage _eff measurements using the equations below：

¹ inversion channel respectively, I_ds is the source-to-drain current, Q_inv is the

inversion charge, Q_dep is depletion charge, 1

η= 2 for electron, ε_si is the permittivity of the silicon.

Fig 2.4 shows the measurement setup we used for mobility measurements of advanced VLSI devices at room temperature. Usually C_gc and hence Q_inv are obtained at V_ds = 0 V in the split CV method. In order to avoid significant error in the mobility value, small voltage values V_ds = 20 mV、40mV have been used for the measurement of I_ds while Q_inv is still obtained at V_ds = 0 V. With suitable controlled bias condition during measurement, the channel mobility versus effective field curve will be extracted.

Fig 2.1 Inversion layer electron mobility as a function of E_eff with T_ox of 3.5–1.5 nm. The solid line denotes the universal mobility.

Gate

Fig 2.2(a) Illustration of fixed charges in HK dielectric MOSFETs.

Gate

Fig 2.2(b) Illustration of remote charges in SONOS flash memories.

AlGaAs GaAs

Fig 2.3 Band diagram in HEMT and SONOS.

Probe

Fig 2.4 The block diagram of measurement setups for split CV

Chapter 3

Characterization of Mobility Degradation in HK Dielectric MOSFETs

3-1 Introduction

High-k dielectrics will be introduced in the 45nm node to achieve the EOT specifications of ITRS. But high-k stacked transistors were reported with low mobility.

The main cause for the low mobility has been proposed to be remote Coulomb scattering caused by charges in the high-k dielectric. Stress induced additional bulk traps in high-k dielectric will be reviewed first. After introducing the HK MOSFETs we used in this work, channel mobility-effective field curves will be measured before and after stress.

3-2 Devices

The gate stack in our measured devices consists of a poly-Si gate electrode, HfSiON as high-k layer with physical thickness of 2.5nm, and an interfacial SiO₂ layer with thickness of 1.4nm. The transistors have an equivalent oxide thickness (EOT) of 1.8nm, a gate length of 0.6 µm , and a gate width of 100 µm .

3-3 Bulk Traps Generation after Stress in HK Dielectric MOSFETs

High-k traps will be generated after a certain stress time. Charge pumping(CP) is usually used to measure the dielectric interface trap density. By modifying the CP

frequency, we can estimate the growth of HK bulk trap density. At higher frequency(f=1MHz), only fast Si/SiO2 interface traps are sensed, but at lower frequency, deeper traps in HK bulk are also pumped. The high-k trap density is obtained by subtracting trap density measured at lower frequency(f=2kHz) and at higher frequency(f=1MHz). Therefore, high-k trap growth can be characterized by a two-frequency charge pumping technique [10]. The experimental procedure is described in Fig 3.1. As shown in Fig 3.1 and Fig 3.2 made by Chien-Tai Chan [11].

We can see bulk trap generation after stress from a charge pumping measurement.

Here we generated different HK bulk traps in devices by stressing the HK dielectric MOSFETs for different time. The HK bulk-defect density was checked by two-frequency charge pumping measurement. The device gate area was 100× 0.6µm²(W×L) in order to avoid geometric effect. NHK value has been deduced from the variation of the defects pumped at low (f=2kHz) and at high (f=1MHz) frequencies. The obtained bulk HfO₂ trap density is calculated by means of the equation below:

where N_HK in the above equation denotes the number of traps per unit area.

N_it value has been extracted from charge pumping measurement at sufficiently high (f=1MHz) frequency. The values of NHK and Nit before stress, after 100s stress and after 500s stress with stress voltage V_g=2V have been reported in Table 3.1. The post-stress device has a higher bulk-defect density than the pre-stress device and the interface state density has almost no difference between the post-stress and the pre-stress devices. We notice that for PBTI stress, the interface trap generation is very

controlled bias condition, we can generate only HK bulk traps.

3-4 Mobility Degradation due to RCS in HK Dielectric MOSFETs

In order to confirm whether the mobility lowering in HK MOSFETs is related to the charged defects located in the HK dielectric layer, the mobility in HK MOSFETs after different stress was examined by split CV method. In the previous section, we characterize the HK bulk-defect density (N_HK) and the interface state density (N_it).

Now, we observe the impact on the peak mobility for the devices after different stress.

All measurements reported were performed at room temperature(~300K). For CV measurement, the frequency was 100kHZ. The source-to-drain current curves were measured at V_ds =20mV. The device gate area was 100×0.6µm²(W×L).

The effective mobility is plotted in Fig 3.3 as a function of the effective field for devices before stress, after 100s stress and after 500s stress with stress voltage V_g=2V.

A difference of approximately 18% in peak mobility is observed between the samples.

As expected, the peak mobility decreases as stress time increases. Since N_it value is the same between the samples, the experimental results mean that the observed µ_eff lowering becomes more significant with an increase in NHK, which is consistent with the existing theoretical model of remote coulomb scattering.

The reduced mobility in MOSFETs with HK gate dielectrics was previously reported for an earlier stage of integration. The natural interpretation of this reduction is that it is due to charging, whether by interface traps or fixed charges. A recently developed theory for RCS solves this problem [13] and agrees well with the results of experiments [14]-[15] and quantum Monte Carlo simulations [12]-[16].

Fig. 3.1 The characterization procedure of the two-frequency charge pumping technique and mobility extracted by split CV.

10 100 1000 1

10

Additiona l I d D egrad at ion ∆ I d,l

in (%)

Stress Time (s)

Fig 3.2 The drain current degradation rate after different stress time.

The stress condition is Vg=2.2V, T=25C.

100 1000 10000 1

10

Ge ne ra te d HK T ra p De nsi ty N HK (t)-N HK (0) ( x1010cm -2 )

Stress Time (s)

Fig. 3.3 Generated high-k trap density versus stress time from the two-frequency CP techniques. The stress condition is Vg=2.2V, T=25C.

0.4 0.6 0.8 1.0 1.2 1.4 0

50 100 150 200 250 300

Effective mobility (cm

2 /V-s)

Effective field (MV/cm)

fresh stress 100s stress 500s

stress condition:Vg=2.2V universal curve

Fig 3.4 Electron effective mobility measured in HK dielectric MOSFET as a function of Eeff under different stress times.

Stress time(s) 0 100 500

Peak μ(^cm2⋅^V-1⋅^s-1) 221 198 183

Nhk(×10 cm^{10 -2}) 3.57 3.86 5.49

Nit(^{×10 cm10 -2}) 3.29 3.38 3.45

Peak ^µ/ Peak µ₀ 89.6% 82.8%

Nhk/Nhk0 1.08 1.54

Nit/Nit₀ 1.02 1.04

(@ 2 ) (@1 )

1 [ ]

2 1

cp cp

HK

I kHz I MHz

N = Aq kHz − MHz

Table 3.1 Interface trap sheet densities and bulk trap sheet densities for different stress times extracted from CP measurement.

Chap 4

Characterization of Mobility Degradation in SONOS Flash Memories

4-1 Introduction

To get a clearer picture of RCS mechanism, we will measure mobility-effective field curves in SONOS flash memories after different FN programming. Furthermore, to study the spacer thickness dependence of remote coulomb scattering, we perform mobility measurement at different programming window in SONOS flash memories with bottom oxide 30A and 20A, respectively. Then a comparison between the experimental and calculated RCS mobility will be presented.

4-2 Mobility Degradation in SONOS Flash Memories

The SONOS cell is made of nMOSFET with an oxide-nitride-oxide stack gate dielectrics. Charges can be stored in the nitride layer by uniform injection as shown in Fig 4.1. Uniform injection(FN injection) has uniform electron storage. Here we use FN injection to program uniform charges in the nitride layer which is the same as the remote charges distribution in our RCS model.

It should be noted here that, in addition to remote charges, interface states can be Coulomb scattering centers influential to the inversion-layer mobility. Interface state density has been checked by charge pumping measurement on devices with bottom oxide=30A, W=10 mµ and L=1 mµ (in order to prevent geometric effect) as shown in Fig. 4.2. It shows that the interface traps density of the devices under FN

programming is about the same.

The device in our experiment are SONOS flash memories with a top oxide of 40A, a nitride layer of 30A, a gate length of 10 mµ and a gate width of 10 mµ . Two devices with different bottom oxide thickness (30A and 20A, respectively) are measured.

Fig. 4.3 and Fig. 4.4 show the E_eff dependence of the inversion-layer mobility for bottom oxide 30A and 20A, respectively. As programmed charges increases, the mobility degradation is more significant in both cases as predicted in the RCS model.

Assuming that Nfix is much smaller than programmed charges, we can take fresh device as reference sample without RCS. Peak mobility degradation in various programmed conditions has been reported in Table 4.1. Programmed charge density can be estimated from threshold voltage shift by N_n ; C_ox⋅ ∆V_th A t⋅ _nitride. The Peak mobility are 296 cm Vs and ² 303 cm Vs for the fresh devices with bottom ² oxide thickness 30A and 20A, respectively. A degradation of approximate 20% in peak mobility is observed in a SONOS cell with bottom oxide 30A at threshold voltage shift 0.7V. A degradation of approximate 40% in peak mobility is observed in a SONOS cell with bottom oxide 20A at threshold voltage shift 0.8V. Comparing the mobility degradation in SONOS flash memories with different bottom oxide thickness, we can see that the mobility degradation is more severe in SONOS flash memories with thinner bottom oxide.

4-3 Comparison between the Experimental and the Calculated Data

In this section, the experimental and calculated results are compared. The

1 1 1

( )

rmt

eff ref

µ ⁼ µ ⁻µ ⁻ Eq (4.1)

following Mathiessen’s rule, where µ_ref is the fresh sample mobility taken as reference. From the equation above, we can extract µ_rmt from measurement data.

The calculated mobility of 2DEG limited by the remote charged defects evaluated from the Eq (2.9) that has been mentioned in section 2-3.

For the calculation, we need to know four parameters: ds(bottom oxide thickness), d_n(distributed programmed charge thickness), N_s(channel electron surface density which can be extracted from split CV measurement), Nn(programmed charge volume density; C_ox⋅ ∆V_th A t⋅ _nitride where t_nitride is the thickness of nitride layer). The only fitting parameter is dn, the thickness where the remote charges is uniformly distributed.

The experimental RCS mobility is extracted by taking the fresh device as reference sample and using Mathiessen’s rule. The calculated RCS mobility as a function of Nn

for bottom oxide 30A is plotted in Fig. 4.5 with N_s =3.14 10× ¹²cm⁻², and fitting parameter 40d_n = A, while the experimental data are plotted by the solid circles, where µ_rmt=5398 cm Vs² for N =1.34 10 cm_n × ^{18 -3} , µ_rmt=1810 cm Vs² for

18 -3

N =2.69 10 cmn × and µ_rmt=1022 cm Vs for ² N =3.77 10 cm_n × ^{18 -3} . The calculated RCS mobility as a function of Nn for bottom oxide 20A is plotted in Fig.

4.6 with N_s =2.55 10× ¹²cm⁻² , and fitting parameter d_n =40A , while the experimental data are plotted by the solid circles, where µ_rmt=1737 cm Vs ² for N =1.39 10 cm_n × ^{18 -3} , µ_rmt=606 cm Vs² for N =3.49 10 cm_n × ^{18 -3} and

2

µrmt=367 cm Vs for N =5.51 10 cm_n × ^{18 -3}.

The calculated RCS mobility, with the assumption of N_s = ×3 10 cm^{12 -2} ,

12 -2

2 10 cm

Ni = × and d_n =20A can be plotted as a function of bottom oxide thickness from 0.5 to 3.5nm as shown in Fig. 4.7. RCS mobility is a strong function of the bottom oxide thickness, and RCS mobility decreases when the thickness is reduced, as expected. We can see that as device scaling down, RCS may be a serious limitation for low-EOT achievement.

n+ n+

Gate

nitride

oxide Drain

Source

oxide

Fig 4.1 Schematic representation of the SONOS structure and uniform charge storage.

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 -0.5

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Icp (nA) @ f=1MHz

Vg _high -Vth (V) fresh

∆

Vth=0.8V

Fig 4.2 Charge pumping current versus the gate overdrive voltage in CP measurement for fresh device and the device with programmed 0.8V threshold voltage shift.

The value of Dit has almost no difference.

0.2 0.4 0.6 0.8 1.0 1.2 0

100 200 300 400

Effective mobility (cm

2 /V-s

)

Effective field (MV/cm)

fresh

Vth shift 0.25V Vth shift 0.5V Vth shift 0.7V universal curve

Fig 4.3 Electron effective mobility measured as a function of Eeff in SONOS flash Memories with bottom oxide 30A

after different programmed threshold voltage shift.

0.2 0.4 0.6 0.8 1.0 1.2 0

100 200 300 400 500

Effective mobility (cm

2 /V-s)

Effective field (MV/cm)

fresh

Vth shift 0.2V Vth shift 0.5V Vth shift 0.8V universal curve

Fig 4.4 Electron effective mobility measured as a function of Eeff

in SONOS flash Memories with bottom oxide 20A after different programmed threshold voltage shift.

0 2 4 0

4000 8000

M obility µ rmt (c m

2 /V-s)

Nn (

^×

1018 cm-3 )

Calculated mobilityµrmt

N_s=3.14×1012 cm-2,d_n=40A,d_s=30A Experimental

Fig 4.5 Calculated mobilityµ_rmtof 2DEG limited by the remote coulomb scattering in SONOS flash memories is plotted as a function of programmed charge density Nn.

The circular dots are measurement data from SONOS flash memories with bottom oxide thickness Tox=30A.

0 1 2 3 4 5 6 400

800 1200 1600 2000

M obilit y µ rmt (cm

2 / V-s)

Nn (

^×

1018 cm-3 )

Calculated mobilityµrmt

Ns=2.55^×1012 cm-2,dn=40A,ds=20A Experimental

Fig 4.6 Calculated mobilityµ_rmtof 2DEG limited by the remote coulomb scattering in SONOS flash memories is plotted as a function of programmed charge density Nn.

The circular dots are measurement data from SONOS flash memories with bottom oxide thickness Tox=20A.

5 10 15 20 25 30 35 0

500 1000 1500 2000 2500 3000 3500

4000

Calculated mobility µrmt

Ns=3^×1012 cm-2,dn=20A Nn=2^×1018 cm-3

M ob ilit y µ rmt (cm 2 /V-s)

ds (A )

Fig 4.7 Calculated remote coulomb mobility as a function of oxide thickness(ds) with assumption of N_s = ×3 10 cm^{12 -2} , N_i = ×2 10 cm^{12 -2} and dn=20A.

△Vth=0 △Vth=0.25 △Vth=0.5 △Vth=0.7

Table 4.1 Peak mobility in SONOS flash memories with bottom thickness 30A, 20A after different programmed charge density.

Chapter 5

Characterization of Random Telegraph Signal in SONOS Flash Memories

5-1 Introduction

Trapping of a single carrier charge in defect states near the Si/gate dielectric interface and related local modulation in carrier density and mobility will have a profound effect on the drain current in such devices. This problem will be exacerbated by the higher defect density in high-k dielectric materials, which are expected to replace SiO₂ in the gate stack somewhere between the 65 and 45 nm technology nodes.

Current fluctuations on such a scale will become a seriours issue, not only as a source of excessive low-frequency noise in analog and mixed-mode circuits, but also in dynamic random access memory and static random access memory and other digital application.

Depending on the device geometry, a single or few discrete charges trapped in hot carrier, radiation or bias temperature stress created defect states will be sufficient to cause significant performance degradation in nanometer scale MOSFETs. For MOSFETs with very small channel area, it is possible to have only one oxide trap in the vicinity of surface Fermi level over the entire channel. Thus, individual traps can be observed in their neutral or charged state and the current fluctuation between two discrete levels. The study of random telegraph signal (RTS) noise in submicrometer MOS transistors offers the unique opportunity of studying the trapping/detrapping behavior of a single interface trap.

From the previous chapters, we observe the large influence of RCS effect on mobility degradation in high-k MOSFETs and SONOS devices. However, it is still unclear that how RCS effect affects RTS amplitude. By easily controlling program window in SONOS devices, it provides a good opportunity to investigate these interesting phenomena. First, the RTS theory will be discussed. Second, RTS measurement setups will be shown. Finally, RTS noise in SONOS flash memories under different FN programming will be characterized.

5-2 RTS Theory

Fig 5.1 displays a typical time domain trace of the drain current illustrating the three main RTS parameters. In small enough devices, normally, only trap energy level within a few kT from the Fermi level would make current fluctuation. k and T are the Boltzmann’s constant and equilibrium temperature, respectively. Traps with energy levels several kT below the Fermi level would be permanently filled while traps with energy levels several kT above the Fermi level would be permanently empty, resulting in negligible noise power.

Up to now, the discrete change in current has generally been modeled as the superposition of two effects that occurs when the trap changes its state: the effect of number fluctuation of free channel carriers ΔN, and the mobility fluctuation Δμ described as [17] in strong inversion. Here, N is the channel carriers per unit area. It is assumed that the mobility is limited by oxide charge scattering with a coefficient α. The sign in front

attractive scattering center. For an acceptor trap, the high level corresponds to the trap in a neutral state while the low level corresponds to the negatively charged state.

Therefore, the RTS are completely determined by the up and down times and its amplitude.

5-3 Measurement of RTS Noise

RTS noise is characterized by three parameter：the average of the high and low time constants and magnitude of the current fluctuation, the range of the time constants is from mili–seconds to seconds. In order to obtain a reasonable estimate of high and low states of RTS, a micro–second measurement system is needed. Fig 5.2 shows the basic circuit we used for our measurements of nano–scaled MOSFETs at room temperature. Fig 5.3 shows the photograph of our micro–second RTS noise measurement system. The MOSFET bias voltage（V ,_D V_G）are all controlled by batteries with tuning resistor, V_SUB is connected to Agilent-4155C Semiconductor Parameter Analyzer, and V is connected to a virtual grounded amplifier and will be _S converted to source current with a 100kΩ feed back resistor. With fast enough circuit sampling rate, the current fluctuation will be extracted and shown on oscilloscope.

5-4 RTS Measurement under Different FN Programming

The device in our experiment are SONOS flash memories with a top oxide of 4nm, a nitride layer of 4nm, a bottom oxide of 3nm, a gate length of 0.12 mµ and a gate width of 0.09 mµ .

Utilizing the fast transient measurement setups [18], RTS pattern under different program window is shown as Fig 5.4. We can see that as the FN programming Vth

increasing, the RTS amplitude will decrease. The read current level is controlled near 7µA in the strong inversion region for the same channel carrier number.

The fractional RTS amplitude for different programmed Vth shift were listed in Table 5.1. From Eq 5.1, we know that the fractional RTS amplitude was contributed by correlated fluctuation in channel carrier number and mobility. In the linear region of operation, above threshold, N ≈C_ox(V_gs−V_th) /q ,where C_ox is the oxide

capacitance per unit area, V is the gate-to-source voltage and _gs V is the threshold _th voltage. In our experiment, V_th ; 1.4V , the carrier number in the entire channel is about 362 and the number fluctuation ; 0.28%= 3.71%. So in our experiment, the component of number fluctuation can be almost ignored. This suggests that the fractional RTS amplitude is attributed to mobility fluctuation.

The amplitude of RTS at a lager program window is smaller. This means that the

contribution of ^eff

eff

µ µ

V is smaller. The mobility measurement we made in Chap 4

shows that the channel mobility will be reduced after FN programming. We can deduce that the degradation of Δμ caused by RCS effect is more severe than the degradation of μ induced by RCS effect. This result may be explained from the degree of RCS. Single charge plays less and less contribution to mobility fluctuation as the program charge increases. Thus, the program charge plays a relative larger part on the degradation of channel mobility at larger programming window. The detailed model is still puzzling and more investigation is needed.

0 300 600

Fig 5.1 Typical time domain plot of the drain current for RTS noise.

Illustration of the three major parameters of RTS noise.

Digital Osc.

OpAmp R=100kΩ

S G

D

Vg

Vd Vo=100kΩ × Id

Digital Osc.

OpAmp R=100kΩ

S G

G D

Vg

Vd Vo=100kΩ × Id

Fig 5.2 Block diagram of experimental setup used for the measurement of RTN in MOSFETs

Fig. 5.3 The photograph of our micro-second measurement system

0.8s 0.8s 0.8s

Fig 5.4 Comparison of RTN amplitude in three different programmed Vth shift in a SONOS cell.

Base current RTN amplitude Id fluctuation

Fresh sample

6.933μA 257nA 3.71%

Program 0.5V

6.914μA 154nA 2.23%

Program 0.8V

6.931μA 103nA 1.49%

Table 5.1 The fractional RTN amplitude under different FN programmed threshold voltage shift observed at almost the read current ; 7 Aµ .

Chapter 6

Conclusion

The study has characterized RCS induced mobility degradation in advanced devices. With suitable bias condition, we can generate only HK bulk traps in HK dielectric MOSFETs. Interface trap density and HK bulk trap density have been extracted by a two-frequency charge pumping method. We have shown that the mobility is reduced as HK bulk trap density increases in HK dielectric MOSFETs.

An experimental evidence of RCS induced mobility degradation is obtained in SONOS flash memories with different bottom oxide thickness. In order to simulate the RCS mobility dependence of bottom oxide thickness, a RCS mobility calculated by 2DEG theory is compared with experimental data. We find that the mobility will be significantly reduced as bottom oxide is further scaled.

To find the relation between RCS and mobility fluctuation on RTS, RTS measurement in SONOS flash memories was characterized. The fractional RTS amplitude corresponding to mobility fluctuation decreases after FN programming.

The model is still puzzling and more investigation is needed.

42

Reference

[1] F. Stern and W. E. Howard, “Properties of semiconductor surface inversion layers

[1] F. Stern and W. E. Howard, “Properties of semiconductor surface inversion layers

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