Multiple Supply Voltage (MSV)

Multiple-Supply Voltage (MSV) is a popular and effective way to power reduction. The basic idea is that assign high voltage to cell on timing critical paths to maintain performance and assign low voltage to cell on timing non-critical paths to reduce power. As the Fig. ??, assign low voltage to the gate with ”slow” label for power reduction due to it can work without oper-ating at high voltage, another one gate with ”fast” label must be operated at high voltage so it is assigned high voltage for maintain performance.

Fig. 2.4: Schematic of Multiple-Supply Voltage Method [B. Sarker, cadence 2005]

In MSV design, voltage assignment is a very important phase because an undesirable voltage assignment result makes the power-supply system complex and cause higher design cost such as more routing resource and heavy human intervention. Beside, another important issue must be concerned in voltage assignment is level shifter (LS). LS is an essential interface between low and high voltage for voltage conversion when a gate with lower supply voltage drives a gate with higher supply voltage. A example is shown in Fig. 2.5. In Fig. 2.5, the right inverter is operated at high voltage and this inverter is driven by a gate with low voltage. Because the voltage of the input signal of the inverter will not be higher than VDDL even when the input signal is at the HIGH level, the pMOS in this inverter may not be cut-off. In this way, a static current flow from drain to source through the pMOS to nMOS. Therefore, LS is needed between a low and a high voltage gate to avoid the phenomenon of a static current. However, the additional LS would increase the cost in area, delay and power; hence, the number of LS must be controlled.

The Fig 2.6 shows an example of an LS.

Existing works [17] propose clustered voltage method to reduce LS overhead. Clustered voltage scaling (CVS) [17] limits the LS position only at sequential element output to reduce

Fig. 2.5: Illustration of the static current flow in a VDDH gate when it is directly connected to a VDDL gate. [B. Sarker, cadence 2005]

Fig. 2.6: Schematic of Conventional level Shifter [B. Sarker, cadence 2005]

the number of LS. Extended CVS (ECVS) [18] relaxes CVS topological constraint and LS is allowed anywhere. Thus, ECVS can provide more power saving than CVS but the delay penalty tends to be larger too. Another effective solution to LS overhead reduction: voltage island generation technique [19, 20], a group gates with same supply voltage is located on a contiguous space, can effectively reduce the number of LS and complexity of power-supply system.

Many previous works addressed on voltage assignment problem [20, 2, 23, 9]. Considering timing-constrained and voltage island aware voltage assignment algorithm is proposed in [20]

present, but it does not consider LS cost such as area, delay and power. In [23], they construct a general formulation of voltage assignment problem, and integrate it into floorplanner phase.

[9] provide a new voltage assignment algorithm based on ECVS to further improve the power

optimization. In [2], a two-phase voltage assignment algorithm on gate-level is proposed. Al-though [23] works consider the effect of LS into their voltage assignment procedure, the number of LS is limited to voltage assignment result. Moreover, those assignment methods only focus on power variation, but they ignore the temperature-related power consumption.

MSV has been studied in different design phase. In the physical design, MSV is consid-ered at various stages, include during floorplanning [6]; floorplanning [12]; and post-placement [19, 3]. [12] propose voltage assignment and voltage island partition method to optimize power consumption and traditional floorplanning objectives such as chip area and wire length, but [6] is limited to core-based SOC design. The idea of post-placement voltage island generator [19] is utilized in our work.

Although MSV has been studied comprehensively for power reduction in 2D ICs, it still has fewer studies of MSV in 3D ICs so far. Intuitively, we can extend any MSV technique of 2D ICs to 3D ICs and utilize MSV technique to do voltage scaling considering tier by tier.

However, without considering every tier in voltage assignment procedure simultaneously would make the power consumption distribution of each layer unbalance; hence, it would cause the thermal problem.

Based on [22], we apply this grid-based total power optimization approach for 3D ICs to our work and extend this idea to explore more improvement and more flexibility in voltage assignment method. Therefore, we propose a grid-based 3D IC Voltage Assignment method considering each tier at the same time to deal with the interaction of voltage assignment with above mentioned problem.

In [10], they propose a two phase voltage scaling algorithm to minimize the total power, which is composed of a greedy voltage assignment phase and an iterative voltage re-assignment refinement phase. LS is determined by voltage assignment results, it would not effectively reduce LS overhead. Besides, the voltage assignment criterion is only determined by power dif-ference between VDDH and VDDL, without considering temperature-related timing and leakage power. Therefore, our voltage assignment method considers the LS overhead before assigning voltage and our main voltage assignment criterion is determined by modifying [9] sensitivity for considering the above mentioned concerns at the same time.

Chapter 3

Power Optimization in 3D ICs

Fig. 3.1: Flowchart of the proposed power optimization for 3D ICs

3.1 Problem Formulation and Flowchart

The proposed a grid-based dual supply voltage assignment design flow for power reduction in 3D ICs is shown in Fig. 3.1. Given a known design placement of 3D ICs, design netlist, cell library and timing/leakage power cell library. For grid-based procedure, we partitioned each tier into n grids as the Fig. 3.4(a) and the number of grid is user definition. Firstly, the initial temperature of chip is obtained by 3D Thermal Analysis. Then, a Thermal Aware Static Timing Analysisis performed with the temperature-related gate delay got from the initial temperature in

circuit has timing violation due to aggressively assigning low V_DD to all gates, and then a grid-based procedure is developed for the 3D ICs Voltage Assignment which assign an appropriate supply voltage for minimizing power saving penalty while enjoying delay gain. After executing voltage assignment procedure once, the power consumption and the delay of gates are changed;

hence, the thermal and timing analysis should be done again to update the temperature-related gate delay and leakage power. After updating the temperature and timing, 3D ICs Voltage Assignmentis executed until no grid can be selected or timing violation is rescued. After voltage assignment, our voltage assignment can be applied to any voltage island generation in 2D ICs design. In the following, we will present the procedure of the proposed power optimization for 3D ICs in detail.

3.2 3D Thermal Analysis

Generally, the dynamic power is independent to temperature but the leakage power is signifi-cantly affected by temperature. Based on the empirical models [8, 4], the gate leakage current Igateis related to the oxide thickness and the subthreshold current Isubis related to the channel length and temperature. Fixing the oxide thickness and the channel length, and the subthreshold current model of gate can be built by utilizing the least square fitting method to the estimated results of HSPICE under the 90 nm technology as follow.

I_sub = s₀exp (s₁T ) (3.1)

where s_i’s are fitting constants, L_{ef f} is the effective channel length and T is the temperature of gate. Because the fitting constants and V_DD are dependent, we fit two pairs of coefficients for the high supply voltage (V_DDH)/low supply voltage (V_DDL), respectively. A look-up table is set up to store them for V_DDH and V_DDL. The gate tunneling and the subthreshold leakage power are

P_gate = V_DDI_gate, (3.2)

P_sub = V_DDI_sub. (3.3)

Based on 3D ICs statistically thermal simulator [22], obtain 3D ICs deterministically thermal simulator, and combines the 3D ICs thermal simulator with the electro-thermal iterative updat-ing loop.