Default Values
All the parameters have default settings at delivery. These defaults, which are suitable for a whole range of standard applications, mean that the S7-400 can be used immediately without the need for further settings.
You can find the CPU-specific default values using “Configuring Hardware” in STEP 7.
Parameter Blocks
The behavior and properties of the CPU are defined using parameters that are stored in system data blocks. The CPUs have a defined default setting. You can change this default setting by modifying the parameters in the hardware
configuration.
The following list gives you an overview of the configurable system properties available in the CPUs.
• General properties (e.g. Name of the CPU)
• Startup (e.g. enabling of a restart)
• Clock synchronous interrupts
• Cycle/clock memory (e.g. cycle monitoring time)
• Retentivity (number of memory markers, timers and counters that are maintained)
• Memory (e.g.local data)
Note: If, for example, you set greater or smaller values than the default values for the process image, the number of diagnostic buffer entries and the
maximum number of ALARM-8 blocks (SFB 34 and SFB 35) and blocks for S7 communication, the working memory available for the program code and for data blocks will be reduced or increased by this amount.
• Assignment of interrupts (process interrupts, delay interrupts, asynchronous error interrupts) to the priority classes
• Time-of-day interrupts (e.g. start, interval duration, priority)
• Watchdog interrupts (e.g. priority, interval duration)
• Diagnostics/clock (e.g. time synchronization)
• Protection levels
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Parameter Assignment Tool
You can set the individual CPU parameters using “Configuring Hardware” in STEP 7.
Note
If you make changes to the existing settings of the following parameters, the operating system carries out initializations like those during cold restart.
• Size of the process image of the inputs
• Size of the process image of the inputs
• Size of the local data
• Number of diagnostic buffer inputs
• Communication resources These initializations are:
– Data blocks are initialized with the load values
– Memory bits, times, counts, inputs and outputs are deleted regardless of the retentive settings (0)
– DBs generated via SFC are deleted
– Permanently configured, base communication connections are established – All the priority classes start from the beginning again
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1.9 Multicomputing
Chapter Overview
Section Description Page
1.9.1 Peculiarities 1-28
1.9.2 Multicomputing Interrupt 1-29
1.9.3 Configuring and Programming Multicomputing Operation 1-29
What is Multicomputing Operation?
Multicomputing operation is the operation of several (max. 4)
multicomputing-capable central processing units at the same time in a central rack (central device) of the S7-400.
The CPUs involved automatically change their modes synchronously. In other words, they start up together and change to STOP mode together. The user program runs on each CPU irrespective of the user programs in the other CPUs.
This makes it possible to execute controller tasks in parallel.
When Do You Use Multicomputing?
It is advantageous to use multicomputing in the following cases:
• If your user program is too large for a single CPU and storage space is becoming scarce, distribute your program over several CPUs.
• If a certain part of your system is supposed to be processed quickly, remove the relevant program section from the overall program and have it processed by a separate, “quick” CPU.
• If your system consists of several different parts that can be easily separated from one another and can therefore be controlled relatively independently, let CPU1 process system part 1, CPU 2 system part 2 and so on.
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Example
The figure below shows a programmable controller that is working in
multicomputing mode. Each CPU can access the modules assigned to it (FM, CP, SM).
Figure 1-7 Multicomputing Example
The Difference Between Multicomputing Operation and Operation in the Segmented Rack
In the segmented CR2 rack (physically segmented; cannot be done by parameter assignment), only one CPU is allowed per segment. However, this is not
multicomputing. The CPUs in the segmented rack each make up an independent subsystem and respond as separate processors. There is no shared logical address area.
Multicomputing operation is not possible in segmented racks (see also the Installation Manual).
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1.9.1 Peculiarities
Slot Rules
In multicomputing operation, up to four CPUs can be inserted at the same time in a central controller (CC) in any order.
If you use CPUs that can only handle module start addresses that are divisible by 4 (usually CPUs before 10/98), you must keep to this rule for all the configured CPUs when you assign addresses! The rule applies should you also use CPUs that allow the bytewise assignment of module start addresses in single-computing operation.
Bus Connection
The CPUs are connected to one another via the communication bus (K bus). In other words, if configured appropriately, all the CPUs can be reached by the programming device via an MPI interface.
Behavior at Startup and During Operation
At startup, the CPUs involved in multicomputing operation automatically check whether they can synchronize with each other. Synchronization is only possible if:
• All the configured CPUs (but only those) are inserted and not defective.
• Correct configuration data (SDBs) have been created and loaded for all the inserted CPUs.
If one of these prerequisites is not met, the event is entered in the diagnostic buffer with ID 0x49A4. You can find explanations of the event IDs in the reference
information for standard and system functions.
When STOP mode is exited, a comparison of the types of startup (COLD
RESTART/REBOOT (WARM RESTART/RESTART) is carried out. If their startup type differs, the CPUs do not go into RUN mode.
Assignment of Addresses and Interrupts
In multicomputing operation, the individual CPUs can each access the modules that were allocated to them during configuration with STEP 7. The address area of a module is always assigned exclusively to a CPU.
Each interrupt-capable module is assigned to a CPU. Interrupts originating from such a module cannot be received by the other CPUs.
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Interrupt Processing
The following applies to interrupt processing:
• Process interrupts and diagnostic interrupts are only sent to one CPU.
• When a module fails or is removed or inserted, the interrupt is processed by the CPU that was assigned to the module at parameter assignment with STEP 7.
Exception: A module insertion/removal interrupt that starts from a CP reaches all the CPUs even if the CP was assigned to a CPU at configuration with STEP 7.
• In the event of a rack failure, OB 86 is called on each CPU, including CPUs that were not assigned a module in the failed rack.
You can find further information on the OB 86 in the reference information on organization blocks.
Typical I/O Application Specification
The typical I/O application specification of a programmable controller corresponds in multicomputing operation to the typical application specification of the CPU with the most resources. The relevant CPU-specific or DP master-specific typical application specifications cannot be exceeded in the individual CPUs.
1.9.2 Multicomputing Interrupt
Using the multicomputing interrupt (OB 60), you can respond synchronously to an event in multicomputing on the corresponding CPUs. In contrast to the process interrupts triggered by signal modules, the multicomputing interrupt can be output only by CPUs. The multicomputing interrupt is triggered by calling SFC 35
“MP_ALM“.
You will find more information in the System Software for S7-300/400, System and Standard Functions manual.
1.9.3 Configuring and Programming Multicomputing Operation
Please refer to the manual Configuring Hardware and Communication Connections with STEP 7 V5.2 to find out how to configure and program the CPUs and the modules.
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