Chapter 3 Design and Implementation
3.2 Peak Detector
Utility of a peak detector is amplitude acquisition; the peak amplitude of the VGA output swing will be acquired in it and compared to a reference at the succeeding comparator. Because what is emphasized in this design is not the exact DC value of the VGA output voltage but the amplitude of swing, a peak hold circuit and a bottom hold circuit are adopted in this work to get peak and bottom value of the output; and the total amplitude will be represented by the difference of peak and bottom.
Diode is a useful component to get the peak value of a swing, because it can just be forward-conducting; if there is a diode connected with a capacitor, the peak value of voltage can be kept in the capacitor without a significant loss. A larger size diode commonly has a better charge ability due to its small equivalent resistance; however, larger leakage current may occur when the size is large.
Considering the driving capability of the VGA, a large size diode may lead to large output capacitance and degrade the bandwidth,. As a result, a transconductance stage is adopted to drive the diode and capacitor, and the model of peak hold circuit in this design is shown in the following figure.
Fig. 3-14 Model of peak hold circuit
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Fig. 3-15 Schematic of peak hold circuit
Peak value of VGA output swing will be kept on CH in Fig. 3-14. Due to negative feedback path, the transconductance stage will charge CH through the diode again if there is a more large swing. A buffer is added behind the connection of diode and capacitor to drive the succeeding low pass filter. A simple RC low pass filter is required here to reduce the voltage glitch caused by the leakage and non-ideality of the diode.
Schematic of this peak detector is shown above in Fig. 3-15; the resistor R between M3 and M4 will generate a zero to the Gm and enhance the bandwidth of this transconductance stage. M5 is drain-gate connected as a diode and M6 is the source follower, both of them are implemented by low threshold device due to DC voltage concern.
Due to the generated zero, the effective Gm can be presented as:
)
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and total transfer function can be derived as:
LPF
Another detail that should be specified is the timing control and settling time of this circuit, the acquired peak value should be reset when another gain mode searching is started because the coming value may be smaller than this one. Before discussing that control, the schematic of the bottom hold circuit should be given first, as in Fig. 3-16.
Contrasted to node A and Vpeak in Fig. 3-15 is the node B and Vbottom in Fig.
3-16. In order to speed up the processes of reset, the charging capacitor CH and CLPF will not reset to Vdd or ground but to the contrasted point, and get an average voltage when reset, and this signal is generated by control unit.
Fig. 3-16 Schematic of bottom hold circuit
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The utility of “reload” duration has been explained in section 2.2.2; noise performance and settling time is a trade-off for the effective low pass filter here;
in order to speed up the settling time with a comparable noise performance, the resistor RLPF will be short by a switch during reload time, and just charging the capacitor CLPF without concerning the noise. After the reload duration, the switch will open, and the low pass filter can suppress the noise and glitch generated by the diode non-ideality, giving a clean DC voltage to the succeeding comparator. Due to the reload mechanism, it seems that the critical settling time will not depend on the RC low pass filter, so the buffer driving capability and the -3dB frequency of the low pass filter is easy to design to fit the specification.
For a 100 MHz clock rate, it will take 10ns for reload and 10ns for LPF duration in this design; using first order RC charging concept, if the time constant generated by CLPF and the buffer output resistance is less than 2ns, CLPF will be charged to more than 99% buffer output voltage in this 10ns reload duration, and it will ease the design difficulty of this RC low pass filter.
By (34), it’s obviously to know that the settling time performance will critically depend on the time constant generated by the transconductance stage Gm and its charged capacitor CH. A small CH will lead to a great glitch due to the leakage of the diode, but it will spend less settling time; and there is a trade-off between bandwidth and gain in the transconductance stage. To charge CH to 90%
VGA output swing in 10ns reload time, this time constant is set to be 4ns with about 5 GHz Gm bandwidth . Under this determination, glitch on CH is still severe in reload duration, but the noise performance will be improved after the low pass filter, and can be ignored if the succeeding comparator has noise immunity.
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In this design, the bandwidth of the Gm amplifier (open loop gain) is about 2GHz, so the data rate of preamble signal should be less than that of the normal data, which is 5GHz; or the settling time of the peak detector should be further long. The bandwidth of the closed loop (including Gm cell, diode, charged capacitor, and buffer) is set to be 250MHz for 90% accuracy in 10ns, and the simulation results is shown below.
Fig. 3-17 Peak detector Simulation Results
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