Performance Summary

The performance summary of the proposed CDR with improved MCML latch is given in Table 4-1. The parameters in the system design are listed. The CDR performance between using improved MCML latch and using common MCML latch are also provided in this table.

Table 4-1 Performance summary

Technology TSMC 0.18μm RFIC 1P6M+ process

Power supply 1.8V

Chip Size 1.05mm × 0.797mm

Power consumption 130mw(including output buffers) Input bit rate 10.71Gb/S (OC-192) Output bit rate 10.71 Gb/s

Kpd 75

mVrad

Kvco 650 MHz/v

VCO phase noise -103dBc@1Mhz

Lock time < 6us

Retimed jitter 7.5ps(peak-to-peak) CDR Spec

Power 40.7 mw

CDR with common

Retimed jitter 11.2ps(peak-to-peak)

Chapter 5

Conclusion and Future Research

The simple CDR circuit was presented in this thesis. This is a first attempt by the author and still has much room for improvement. The simple CDR uses the proposed MCML architecture to incorporate the Alexander phase detector. The proposed MCML architecture can reduce the output signal level fluctuation. These realizations may improve the jitter performance. The techniques for high-performance CDR design remain a challenging and a promising task.

In Chapter 2, a simple CDR with Alexander phase detector is presented. The system behavior and loop performance have been analyzed. The approximate second-order model, which imitates the analytical of linear PLL model, was derived to validate the stability and to assist in system parameters design.

In Chapter 3, a 10GHz simple CMOS CDR circuit has been realized in 0.18μm standard CMOS process. In order to operate at high-speed frequency in the Gb/s range reliably, we must use the MCML architecture circuit which can operate correctly with smaller input signal voltage swing at high frequency. We proposed an improved MCML circuit which can reduce the output signal level fluctuation drawback of original MCML. We use the full-rate Alexander bang-bang phase detector for a phase tracking state. The output of phase detector drives a V/I converter. The V/I converter

change the VCO oscillating frequency. Finally, we compare the system performance between the improved MCML latch system and the common MCML latch system.

The proposed improved MCML latch can reduce the CDR jitter and has more opened eye diagram than the common MCML latch.

In Chapter 4, there are some discussions on the layout techniques. The common centroid layout structure is used to reduce layout mismatch. Finally, the CDR circuit as presented in this thesis occupies a 1.05mm × 0.797mm chip area in TSMC 0.18um 1P6M technology. The total power consumption of this chip is about 130mw under a 1.8V supply voltage (two output buffers included).

This CDR structure is quite fundamental. With the proposed MCML latch, we can improve the common MCML circuit drawback to get a better jitter performance.

In this proposed CDR circuit, we can additionally add a frequency detection circuit in the future research. The frequency detection drives the VCO frequency toward the desired value by a frequency-locked loop. When the frequency error reaches a sufficiently small value, the PLL takes over and performs phase locking. This frequency detector can improve the typical PLL drawback of small capture range, especially if it operates with random data.

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Appendix A

Testing Strategies

The chip testing consists of three steps, namely, DC power supply and ground, print circuit board (PCB) layout, and closed-loop CDR testing.

Firstly, the DC operating point is measured to make sure that all of the biasing current and DC points are in the vicinity of the original designs. Since the CDR system has a high frequency LC-tank VCO, we partition the DC power supply and ground-reference net on the PCB into 2 parts to isolate the noise coupling. Hence, the VCO and other circuit ground planes is separated on the PCB and connected by a inductor. This inductor shorts the DC voltage of the VCO and other circuits grounds, while preventing the high-frequency noise coupling. The power supply and bias voltage are generated by LM 317 adjustable regulators as show in Figure A-1[28].

The input of the regulator circuit is connected to a 6V battery instead of a general power supply, because the noise of general power supply is much larger than the battery. The regulator circuit is easy to use and could be predicted by the Equation A.1.

where the I_ADJ is the DC current that flows out of the adjustment terminal ADJ of the regulator. The capacitor C1 can be added to improve transient response at the output.

The output of the regulators are bypassed on the PCB with another bypass filter

10uF、1uF、0.1uF and 0.01uF capacitors as shown in Figure A-2.

Figure A-1 LM 317 regulator

Figure A-2 Bypass filter at regulator output

Measurement must performed with raw die mounted on the PCB to prevent the parasitic effect of the package, which is illustrated in Figure A-3(a), and the testing PCB layout was shown in Figure A-3(b). High-frequency signal traces such as NRZ, NRZB, R_CLK, R_CLK, R_NRZ and R_NRZB are mode as short as possible to reduce signal exhaustion and the length of differential signal traces are made close to each other reduce the parasitic clock skew. Each high-speed traces use the SMA(Surface Mount Adaptor) connector. High-speed output lines can easily couple the large output swing onto the sensitive input line. Another challenge is in placing the discrete components and terminations match to the chip to reduce associated parasitic and signal reflections.

Figure A-3(a) Off-chip bonding wire test

Loop filter

Bare Die

Retimed Data VCO GND NRZ

Circuit GND

Retimed Data_B NRZB

R_CLK R CLKB

Figure A-3(b) The testing PCB

The testing schematic of the closed-loop CDR is shown in Figure A-4. In order to avoid the substrate noise coupling from VCO block to sensitive other circuit blocks and thus degrade the jitter performance, the VCO ground is separated from the other circuit block ground. The VCO tuning range can be measured by the Spectrum Analyzer(Agilent E4440A PSA Series Spectrum Analyzer) with the tuning voltage generated by DC power supply(Agilent E3610A power supply). The PRBS non-return-to-zero fully differential input data is generated by the Pattern

voltage swing can be set by this instrument. After the loop is locked, the resulting eye diagram is monitored by the Oscilloscope(Tektronix TDS6124C Digital Storage Oscilloscope).

Figure A-4 Experimental test setup

We measure the CDR chip with above setup method. The first important parameter to test is the VCO’s tuning range. The measurement of the VCO result is showed in Figure A-5. The VCO tuning range is 9.0641GHz ~8.9532GHz. It is not in our required range. We conjecture that the circuit layout has heavy parasitic capacitance. The heavy parasitic capacitance lowers the VCO oscillation frequency and the ratio of the varactor capacitance to total capacitances. Thus, the VCO tuning range is more smaller than simulation. The signal spectrum is showed in Figure A-6.

The signal power is about -40dBm and the VCO output spectrum is not pure. The signal power is too small to let the CDR system work correctly. The failure of experiment reminds us that the layout of the high-speed VCO circuit should be more

symmetrical to reduce high frequency signal coupling. The LC-tank VCO should have effective guard ring to cut off the noise coupling form the inductor and varactor.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

8.94 8.96 8.98 9.00 9.02 9.04 9.06 9.08

measure result

Frequency (GHz)

control voltage (V)

Figure A-5 VCO tuning range experimental result

Figure A-6 VCO signal power

In order to reduce the bond wire parasitic inductor, the chip pad of the high frequency signal should be arranged symmetrically. As showed in Figure A-7, where two transmission lines carry differential signals to the bond wire pads. The bond wire parasitic can be represented by L1 and L2, and mutual coupling between the inductors, M, yields the following voltage drops across each:

Ms

Figure A-7 Bond wire parasitic

The key observation here is that mutual coupling reduces the transient drop across each inductor, thus lowering the effective inductor that appears in each signal line. At 10GHz domain, the signal path characteristic likes transmission line. The transmission line whose length is a significant fraction of the wavelength of interest or, equivalently, whose end-to-end delay is not negligible with respect to other time scales in the environment. Each resistance mismatch of connector will make signal reflection which disturbs the original signal. The testing PCB must be manufactured exactly by special company instead of etching by yourself to have better circuit characteristic.