Physical Verification

Physical design for deep submicron is most difficult in SoC. The most important issue is timing closure. Timing of the design is not easy to meet in physical level. To solve this question, robust Electronic Design Automation (EDA) tools and good coding style are needed.

In physical verification, we do Automatic Placement and Routing (APR), on-line Design Rule Check (DRC) and Layout Versus Schematic (LVS) using Synopsys^® Astro; off-line DRC and LVS using Mentor Graphics^® Calibre. Finally, we pass the Post-layout Simulation (Post-Sim.) using ModelSim.

4.3 Results

Judging from the above, verification will be completed as far as possible in system level in SoC, especially create a correct FPGA prototyping. This prototyping will be compared with the result of other layer. Thus we can decrease the loading of verification in physical level.

The Figure 4-7 below illustrates that implementation of JPEG2000 coprocessor.

In this chip, CMOS UMC 0.18um (1P6M) technology is used. The chip size contains 335K gate count is . The operation frequency can reach 50 MHz. With the operation frequency, power consumption is 100 mW. Moreover, on-chip memory is 8.4 Kbytes.

3mm×3mm

Figure 4-9 Chip feature of JPEG2000 coprocessor.

Here is a diagram which illustrates the platform-based architecture for JPEG2000 encoding system. Figure 4-8 shows an overview of our JPEG2000 encoder platform.

Mainly, it includes an ARM9 CPU for the data flow control and generating packet header production. The CPU communicates with the JPEG200 coprocessor via a 32-bit AHB bus.

PC

Figure 4-10 The proposed AMBA-based JPEG2000 encoder architecture.

The Figure 4-9 below illustrates that implementation of an SoC design case. In this chip, CMOS UMC 0.18um (1P6M) technology is used. The chip size contains 2M gate count is . The operation frequency can reach 50 MHz. With the operation frequency, power consumption is 150 mW (ARM core excluded). Moreover, on-chip memory is 16.6 Kbytes.

5mm×5mm

Figure 4-11 An SoC design case with JPEG2000 coprocessor.

C ^{HAPTER 5}

C ONCLUSIONS AND F ^UTURE W ^ORKS

JPEG2000 is the superior still image compression standard due to its excellent compression efficiency and numerous novel features. One of important features of JPEG2000 is accurate rate-control scheme but it is not suitable for hardware design.

As for other rate-control schemes such as quantization, they suffer the serious PSNR degradation and inaccurate rate control although their implementation is quite simple.

In this thesis, we proposed a configurable rate control architecture. In traditional DWT, we can use Real-Time Rate-Distortion Optimized (RTRD-Opt) method to reduce computation of EBCOT Tier-1. In addition, it is more appropriate to use Imitative Post-Compression Rate-Distortion Optimized (IPCRD-Opt) method in QCB-based DWT architecture.

In addition to this, we design JPEG2000 coprocessor not only an IC but also an IP.

It is fact that IP design is more time-consuming than IC design. But if we design a complete IP, it is saving more development cycle when second time reuse. Finally we transplant the ARM integrator system to an SoC. The most difficult things are complete verification.

Here is a figure which shows the final objective of RTL design. To begin with,

the RTL code should be synthesizable. Then, it is better to write reusable RTL code.

The reason is why we design a JPEG2000 IP but not an IC. Finally, if the RTL code is verifiable, we can integrate and verify the IP easily. It is very important when design a VLSI system.

Verifiable

Reusable Synthesizable

Figure 5-1 The final objective of RTL design.

The Figure 5-2 below illustrates that design layer of an IP. Bottom layer is fundamentals which everyone can study while he is a college student. Top layer is domain-spec., technology know how which everyone can research while he is a graduate student. But it is also very important that the middle layers (implementation skills for ICs/IPs) which everyone may ignore easily. That is to say if we want our design better, these two layers are key points.

Figure 5-2 Design layer of an IP.

IP reusability has been a key issue in SoC design for many years. We have faced many situations where IP have being developed for a specific application but with the emphasis on reusability. Formal verification results a key approach to guarantee the correctness of the IP versus the specification.

R ^EFERENCES

[1] ISO/IEC JTC1/SC29 WG 1 N1684, “JPEG2000 Part I Final Committee DraftVersion 1.0.”

[2] Te-Hao Chang, Chung-Jr Lian, Hong-Hui Chen, Jing-Ying Chang, Liang-Gee Chen, “Effective hardware-oriented technique for the rate control of JPEG2000 encoding”, IEEE International Symposium on Circuits and Systems(ISCAS’03), Vol. 2, pp. 25-28, May 2003.

[3] Yeung Y.M., An O.C., Chang A., “Successive bit-plane rate allocation technique for JPEG2000 image coding”, IEEE International Conference Acoustics, Speech, and Signal Processing(ICASSP '03), Vol 3, pp. 6-10 April 2003.

[4] Masuzaki T., Tsutsui H., Izumi T., Onoye T., Nakamura Y., “JPEG2000 adaptive rate control for embedded systems”, IEEE International Symposium on Circuits and Systems(ISCAS’02), Vol 4, pp. 26-29 May 2002.

[5] B. F. Wu and C. F. Lin, “Analysis and Architecture Design for High Performance JPEG2000 Coprocessor,” in Proc. IEEE International Symposium on Circuits and Systems, vol. 2, pp.225-228, May, 2004.

[6] Wei-Chang Tsai, Chun-Ming Huang, Jiann-Jenn Wang, Chen-Yi Lee,

“Infrastructure for education and research of SOC/IP in Taiwan”, IEEE International Conference Microelectronic Systems Education, pp. 150-151, June 2003.

[7] T. H. Chang, “Efficient JPEG2000 Encoder Design With Novel Rate-Distortion Optimizing Techniques,” Master’s Thesis, Dept. of EE, National Taiwan University, June 2003.

[8] C. W. Huang, “AHB-based JPEG2000 Coprocessor System Design,” Master’s Thesis, Dept. of ECE, National Chiao Tung University, June 2004.

[9] P. C. Chen, “Design of the efficient Pass-Parallel Context Formation Codec for JPEG2000,” Master’s Thesis, Dept. of ECE, National Chiao Tung University, July 2004.

[10] Virtual Socket Interface Alliance (VSIA); VSIA Homepate; 2001;

http://www.vsi.org

[11] IP Qualification Alliance “IP Qualification Guidelines(Verilog Version)” Version 1.0, Release Date: Dec. 19, 2003.

[12] IP Qualification Alliance “IP Qualification Guidelines(VHDL Version)” Version 1.0, Release Date: Oct. 22, 2004.

[13] Keating, M.; Bricaud, P.; Reuse Methodology Manual for System-on-a-Chip Designs; Third Edition; Kluwer Academic Publishers; 2002.

[14] 黃俊達, IP Core Design 上課講義, 2004 Fall, Dep. of EE, National Chiao Tung University.

[15] 張添烜, SOC Design Lab 上課講義, 2005 Spring, Dep. of EE, National Chiao Tung University.

[16] CIC(Chip Implementation Center)寒暑期上課講義。

[17] 吳炳飛 胡益強 瞿忠正 蘇崇彥，JPEG2000 影像壓縮技術，全華科技書股 份有限公司，2003 年 4 月初版。

[18] 戴顯權 陳政一，JPEG2000，紳藍出版社，2002 年 11 月。

[19] ARM Documents http://www.arm.com

[20] JPEG2000 Information http://www.jpeg.org/jpeg2000/index.html [21] JasPer Software http://www.ece.uvic.ca/~mdadams/jasper/