Program Sequence Control Unit

The program sequence control unit (PSCU) is a main component in the DSP kernel. Ba-sically, we can regard it as the combination of the control path and the instruction path.

The control path affects the program counter updating, address fetch, pipeline control, hardware context shadowing, interrupt handling, exception handling, etc., according to the input control signals from elsewhere in the PACDSP. In addition, the instruction path is responsible for fetching, dispatching, and decoding of the instruction packets.

Figure 3.1: Architecture of the PACDSP [2].

Figure 3.2: PACDSP instruction set architecture [4].

Figure 3.3: Pipeline stages of the PACDSP [4].

Table 3.1: Pipeline Stages and Their Jobs

Stage Job

IF Instruction Fetch

IMEM Instruction Memory Access IDP Instruction Dispatch ID Instruction Decode RO Read Operand EX1 Execution One EX2 Execution Two EX3 Execution Three WB Write Back

3.3.1 Branch Instructions

Branch instructions can be grouped into two categories, conditional branches and uncon-ditional branches. There are three addressing modes defined in the PACDSP v3.0 for generating the branch target address:

• PC-relative

Add up to 32-bit signed immediate offset to the address in the PC register, and take the result as the branch target address, i.e.,

TA = PC + OFFSET

where TA is the target address, PC is the address in Program Counter, and OFFSET is the immediate value defined in branch instruction.

• Register

Take the value in the register as the target address, i.e.,

TA = Rs

where TA is the target address and Rs is the source register defined in branch in-struction.

• Register-relative

Add up to 32-bit signed immediate offset to the address saved in the register and take the result as the branch target address, i.e.,

TA = Rs + OFFSET

where TA is the target address, Rs is the source register defined in branch instruc-tion, and OFFSET is the immediate value defined in branch instruction.

In some circumstances, a branch operation may need to save the return address to en-sure correct working of the program when it returns. The branch instructions defined in the PACDSP support saving of the return address into the assigned register. The program-mer should take care of the return addresses of nested loops. There are five branch delay slots in the PACDSP, and the programmer could put the branch-independent instructions in the delay slots.

There are some constraints about instructions in the delay slots. Reference [4] gives the details of the programming constraints.

3.3.2 Loops

The programmer can use the LBCB or B instruction to describe program loops. LBCB is similar to branch, but instead of checking a predicate register (P0–P15), LBCB checks a general purpose register (R0–R15) to decide whether to branch or not. Since there are 16 general purpose registers (R0–R15), up to 16 levels of nested loop can be supported with the use of the LBCB instruction.

There is a constraint in using LBCB to control a nested loop. The outer loop should fully contain the inner loop. No exception will be generated if the constraint is violated, but the program behavior may be different from expectation.

However, conditional branches can be used inside the nested loop to implement some special branch behaviors in higher level languages, for example, “break” and “continue”

in C.

3.3.3 Customized Function Units (CFUs)

The PACDSP provides Customized Function Unit Interface for extension usage. The user can attach co-processors or customized function units to PACDSP and handle them through the scalar instructions. If error happens in a customized function unit, it can inform the PACDSP and the PACDSP can process it based on the particular configuration.

If the given work has finished successfully, the PACDSP can use its results and continue to work. It is recommended that if a co-processor is used, communication with it be made through this interface, or the user will have to pay much more effort to handle it.

3.3.4 Exception Handling

Unpredictable exceptions may occur during program execution. The exceptions need to be handled correctly for correct execution results. Exceptions may be caused by hard-ware (e.g., overflow), softhard-ware, internal (e.g., undefined instruction), or external (e.g., co-processor exception). When an exception happens whether PACDSP is running a program or not, PACDSP will check for mask information. If the exception is masked, PACDSP will ignore the exception and return to normal execution. If the exception is unmasked, it will be taken. PACDSP will freeze its pipeline, finish the instructions before the PC which introduced the exception, and recover the states for consistence. After the state is recov-ered, PACDSP will issue exception handling ISR to inform the MPU and the Embedded ICE, waiting for different commands to resolve the exception.

3.3.5 Interrupt Handling

Two types of interrupt are supported by the PACDSP. One is fast interrupt request (FIQ), which has the higher priority, and the second is interrupt request (IRQ). The difference between them is that the FIQ has fixed ISR address and IRQ needs ISR to check the IRQ source to obtain the proper ISR address.

In the PACDSP, the minimum latency from interrupt request to the first ISR instruction to be executed is 4 cycles for both types of interrupt, and it may be postponed when the ISR experiences cache miss.