Redundant Via Insertion under Timing Constraints

Chi-Wen Pan, Yu-Min Lee

National Chiao Tung University, Hsinchu, Taiwan [email protected], [email protected]

Abstract— Redundant via insertion is a useful technique to allevi-ate the yield loss and elevallevi-ate the reliability of VLSI designs. While extra vias are inserted into the design, the electronic properties of designed circuit might be altered, and the circuit timing might be changed and needs to be efﬁciently re-analyzed. Therefore, a fast timing (incremental timing) analyzer is required to assistant the redundant via insertion procedure.

This work develops an efﬁcient redundant via insertion method under timing constraints. Firstly, an effectively incremental circuit timing analysis method is developed, and the redundant via insertion task is transformed into a mixed bipartite-conﬂict graph matching problem. Then, the insertion problem is solved by a timing-driven minimum weighted matching algorithm.

The experimental results show that the developed algorithm can achieve3.2% extra insertion rates over the method without consid-ering timing effects, which all redundant vias would be removed if the timing of that net does not meet the timing requirements, in average. In addition, the developed incremental timing analysis mechanism can speed up the runtime of redundant via insertion procedure under timing constraints by over34 times in average.

I. INTRODUCTION

As the feature size continuously scales down, yield becomes an important issue for the current modern design. Yield-loss comes from many physical factors, and via failure is one major factor caused by electromigration, thermal stress and random defects.

Partial via failure increases circuit resistances that result in the unexpected timing delay, and complete via failure can break the net connection and lead to the inaccurate signal that makes the circuit fail. Without violating any design rules, inserting a redundant via (RV) adjacent to a single via as a safeguard is a widely recommended method for improving the circuit yield and reliability [1], [2]. With the double vias, the via failure rate can be dramatically reduced as reported in [3].

Many researches performed the RV insertion procedure during the routing stage [4]–[6]. Xu et al. [4] developed a maze routing with considering RV insertion for the yield enhancement. Yao et al. [5] minimized the via usages and inserted redundant vias in the routing stage to improve the multilevel routing framework.

Chen et al. [6] proposed a full-chip gridless routing method with considering double-via insertion based on the bipartite matching graph algorithm. However, they stacked the vertical vias as one stack via that the solution space was reduced. Besides, many researches worked on the post-routing stage [7], [8]. Lee et al. [7]

proposed a zero-one integer linear program to solve double-cut via insertion problem and handle the via density constraint. Lei et al. [8] transformed the RV insertion task into a mixed bipartite matching graph and presented a heuristic minimum weighted matching algorithm to solve the problem. They also developed the wire spreading method to insert redundant vias for dead vias.

Inserting RV into the circuit might vary the timing characteris-tic of design. Luo et al. [9] created a set of untouched nets such as the timing critical nets or the nets speciﬁed by customers etc.,

and utilized the geotopological technology to insert redundant vias. Although they considered the timing issue, the insertion algorithm cannot guarantee whether the circuit timing is degraded or not after the insertion. Chiang et al. [10] developed a two-phase insertion approach method with considering timing constraints.

However, they only checked the timing behavior after executing the insertion procedure and simply got rid of inserted redundant vias violating timing constraints. In other words, they didn’t immediately update the timing behavior during the RV insertion procedure. Therefore, the insertion rate is degraded.

Recently, Lin et al. [11] pointed out that “How to tackle the timing issue more accurately during double-via insertion is still worthy further study.”. The experimental results illustrated in TABLE IV also show that the ratio range of net sink node delay differences after performing the conventional (without considering the timing effects) redundant via insertion method [8]

on test circuits can be35% ∼ 58%. Therefore, it is necessary to develop timing-driven redundant via insertion methods.

Because the timing information should be frequently predicted and updated during the RV insertion process, a fast timing analysis method is required. In this work, ﬁrstly, an incremental analysis method is developed to effectively perform the timing analysis and predict the timing behavior for the RV insertion process. The developed incremental analysis method does not need to recalculate the entire net timing to predict the timing effect of adding an extra via. It only needs to analyze the timing inﬂuence induced by the modiﬁed circuit parts. Therefore, the computational load of timing analysis can be dramatically reduced. After that, the proposed incremental timing analysis method is incorporated with the mixed bipartite-conﬂict (MBC) graph [8] for developing a timing-driven minimum weighted matching (t-MWM) algorithm to solve the RV insertion task.

To the best of our knowledge, this is the ﬁrst redundant via insertion method that truly considers the timing effects of inserted vias during the insertion procedure.

The paper is organized as follows. The redundant via insertion problem under timing constraints is formulated in section II.

Then, an efﬁcient incremental timing analysis method for the redundant via insertion problem is detailed in section III, and the MBC graph [8] is brieﬂy presented in section IV. After that, the developed t-MWM algorithm and the experimental results are presented and discussed in section V and section VI, respectively.

Finally, the conclusion is given in section VII.

Fig. 1. A simple RC tree. (a) An original RC tree. (b) A locally modiﬁed RC tree.

II. PROBLEMFORMULATION

Given a post-routing design, its routed netlist and each net tim-ing constraint¹, the RV insertion problem under timing constraints is to simultaneously insert extra vias as many as possible to the design and satisfy the given timing constraints. The problem can be formulated as follows.

N is the number of nets in the given design, Miis the number of single vias on neti, D_jⁱ is the propagation delay from the source of net i to its sink j, and D_jⁱ is the timing constraint of sink j on net i.

III. INCREMENTALTIMINGANALYSIS

A. Incremental Timing Formula

A simple RC tree shown in Fig. 1 is used to describe the closed form of the incremental timing formula. Given an original RC tree shown in Fig. 1.(a) and its locally modiﬁed RC tree shown in Fig. 1.(b), their Elmore² delay values from node0 to node n can be calculated as

Here, their timing differencetn can be derived as

t_n = C₂²

1In this work, the main issue is how to consider the timing effects during the redundant via insertion procedure. Hence, we simplify the problem with the net timing constraint; however, our developed method also works with the circuit timing constraint.

Here, each ΔC_i is the difference value of nodal capacitance at node i after and before via insertion, and each ΔR_j is the difference value of branch resistance on branchj after and before via insertion. The expression of (1) consists of three types. Each term in the ﬁrst line is the product of a delta nodal capacitance and its original upstream common path equivalent resistance.

The original upstream common path equivalent resistance is the sum of original overlapped segment resistances between the paths from source node 0 to the nodal-capacitance changed node and from source node 0 to node n in Fig. 1.(a). Each term in the second line is the product of a delta branch-resistance (on the path from source node0 to node n) and its original downstream equivalent capacitance. Each term in the last line is an interactive term that is the product of a delta branch-resistance (on the path from source node 0 to node n) and its delta downstream equivalent capacitance.

With (1), the timing differencetnfor each noden after a RC tree is locally modiﬁed can be generally formulated as follows.

Δtn=

Here, Rni is the original upstream common path equivalent resistance between P_n and P_i, and P_n/P_i is the routed path from source node to node n/i. Cj∗ is the original equivalent downstream capacitance seen from branch j, and ΔC_j∗ is the difference value of equivalent downstream capacitance seen from branchj after and before via insertion.

By utilizing the timing difference formula of noden shown in (2), it can be very efﬁcient to predict each speciﬁc net sink node delay without recalculating all node delays of a speciﬁc net.

B. Redundant Via Shapes

According to the connection between wires and the single via, the structures of redundant vias can be categorized into two different shapes. If a single via only connects two wire segments, it is called an L-shape since this structure looks like an alphabet letter ‘L’. If a single via connects more than two wire segments, it is called a T-shape since it looks like an alphabet letter ‘T’.

Moreover, according to the characteristic of redundant vias, they can be divided into two types, on-track RV and off-track RV.

The on-track RV is placed on the original net and needs only one extra wire segment, and an off-track RV is placed out of the original net and needs to add two extra wire segments.

Since L-shape RVs and T-shape RVs are cyclic circuits, in order to effectively calculate their Elmore delay values, several fundamental circuit transformation techniques are utilized to make them acyclic. The equivalent acyclic RC circuits of each L-shape RV and each T-shape RV are derived as follows to incrementally update the circuit timing efﬁciently.

B.1. L-shape

The L-shape RVs contain three templates that two types are on-track RVs, and one type is off-track RV. These templates and their corresponding RC trees are shown in Fig. 2. Fig. 3 shows the equivalent acyclic RC circuits of above three L-shape RV templates, and their related ΔR values and ΔC values are summarized in TABLE I.

B.2. T-shape

TABLE I

ΔR^{VALUES AND}ΔCVALUES OF THE EQUIVALENT ACYCLICRCCIRCUIT OFL-SHAPERVAND SIMPLET-SHAPERV.

L-shape RV ΔR ΔC

ΔR1 ΔR2 ΔR3 ΔC0 ΔC1 ΔC2 ΔC3

on-track type I −rw1x ^(r^w1_(r^x+r_w1_+r^v^l_w2^v^)(r_)x+2r^w2^x+r_v_l_v^v^l^v⁾− rvlv 0 −^c^w1₂^x ^c^w2^x+c₂ ^v^l^v ^c^w1^x+c^w2₂ ^x+c^v^l^v 0 on-track type II 0 ^(r^w1_(r^x+r_w1_+r^v^l_w2^v^)(r_)x+2r^w2^x+r_v_l_v^v^l^v⁾− rvlv −rw2x 0 ^c^w1^x+c^w2₂^x+c^v^l^v ^c^w1^x+c₂ ^v^l^v −^c^w2₂^x

off-track type 0 ^(r^w1_(r^x+r_w1_+r^v^l_w2^v^)(r_)x+2r^w2^x+r_v_l_v^v^l^v⁾− rvlv 0 0 ^c^w1^x+c^w2₂^x+c^v^l^v ^c^w1^x+c^w2₂ ^x+c^v^l^v 0

Fig. 2. L-shape RV. (a) on-track type I. (b) on-track type II. (c) off-track type.

Fig. 3. The equivalent acyclic RC circuit of L-shape RV.

RVs precisely. The simple T-shape RVs contain three templates that two are on-track RVs, and one is off-track RV. Utilizing the similar circuit transformation techniques as L-shape RV templates, they can be transformed to corresponding equivalent RC tree structures. The simple T-shape RV templates and their equivalent RC trees are shown in Fig. 4. Fig. 5 represents equivalent acyclic RC circuits of simple T-shape RV templates.

Although the equivalent circuit structure of simple T-shape RV is different with that of L-shape RV, they have the same delta RC values as shown in Fig. I because the extra wire segment in each simple T-shape RV has no impact on the equivalent circuit transformation.

The delta-wye transformation is needed for transforming the rest T-shape RV templates to be acyclic circuits with extra resistance and capacitance parameters. Their equivalent RC tree structures are more complicated than those of simple T-shape RV templates. We call them complicated T-shape RVs. The complicated T-shape RV templates and their equivalent RC trees are shown in Fig. 6. Fig. 7 is the equivalent acyclic RC circuit of complicated T-shape RV templates, and their related ΔR values andΔC values are summarized in TABLE. II.

Fig. 4. Simple T-shape RV. (a) on-track type I. (b) on-track type II. (c) off-track type.

Fig. 5. Two equivalent acyclic RC circuits of simple T-shape RV.

C. Fast Sink Node Timing Check

To efﬁciently check whether the timing of each related sink node will violate its timing constraint or not if a related RV is inserted, the timing difference formula t_n shown in (2) and the related ΔR values and ΔC values for L-shape RVs and T-shape RVs presented in TABLE. I and TABLE. II, respectively, are integrated to build a fast sink node timing check algorithm shown in Fig. 9. By executing the algorithm shown in Fig. 9, the timing of sink node as if adding an RV candidate can be fast checked.

Remark: The developed fast sink node timing check algo-rithm can be easily extended to perform the path delay check by using the static timing analysis method to calculate each gate’s require arrival time (RT), arrival time (AT), and slack. By setting each gate’s slack to be non-negative as a timing constraint during the RVI algorithm, one inserted redundant via might change the gate’s RT or AT on the net that can be veriﬁed by the fast sink node timing check method. After that, the

TABLE II

ΔR^{VALUES AND}ΔCVALUES OF THE EQUIVALENT ACYCLICRCCIRCUIT OF COMPLICATEDT-SHAPERV.

Complicated ΔR

T-Shape RV ΔR1 ΔR2 ΔR3 ΔR4 ΔR5 ΔR6

on-track type I −rw1x _(r^(r_w1^w2_+r^x+r_w2^v_)x+2r^l^v^)r^w1_v^x_l_v _(r_w1_+r^r^v^l_w2^v^r_)x+2r^w1^x _v_l_v _(r^(r_w1^w2_+r^x+r_w2^v_)x+2r^l^v^)r^w1_v^x_l_v − rvlv 0 0 on-track type II 0 _(r_w2_+r^r^v^l_w3^v^r_)x+2r^w3^x _v_l_v _(r^(r_w2^w2_+r^x+r_w3^v_)x+2r^l^v^)r^w3_v^x_l_v _(r^(r_w2^w2_+r^x+r_w3^v_)x+2r^l^v^)r^w1_v^x_l_v − rvlv −rw3x 0 on-track type III 0 _(r^(r_w1^w1_+r^x+r_w2^v_)x+2r^l^v^)r^v_v^l^v_l_v − rvlv rvlvrw2x

(rw1+rw2)x+2rvlv

(rw1x+rvlv)rw2x

(rw1+rw2)x+2rvlv 0 −rw2x

Complicated ΔC

T-Shape RV ΔC0 ΔC1 ΔC2 ΔC3 ΔC4 ΔC5 ΔC6

on-track type I ^−c^w1₂ ^x ^c^w2^x+c₂ ^v^l^v ^−c₂^v^l^v ^c^w1^x+c₂ ^v^l^v ^c^w2^x+c₂ ^v^l^v 0 0 on-track type II 0 ^c^w3^x+c₂ ^v^l^v ^−c₂^v^l^v ^c^w2^x+c₂ ^v^l^v ^c^w2^x+c₂ ^v^l^v ^−c^w3₂ ^x 0 on-track type III 0 ^c^w1^x+c₂ ^v^l^v ^−c₂^v^l^v ^c^w2^x+c₂ ^v^l^v ^c^w1^x+c₂ ^v^l^v 0 ^−c^w2₂ ^x

Fig. 6. Complicated T-shape RV. (a) on-track type I. (b) on-track type II. (c) on-track type III.

Fig. 7. The equivalent acyclic RC circuit of complicated T-shape RV.

delay effect is passed to the upstream and downstream path, and the circuit delay is calculated and checked.

With this method, we can effectively update the circuit timing, keep the slack being non-negative, and has no any timing violation.

D. Runtime Complexity Analysis

The incremental timing analysis method can analyze the timing difference in O(n_sink) time if a relation topology table between

Fig. 8. An example of look-up table. (a) A RC tree. (b) The related look-up table.

be easily analyzed by using the look-up table. For example, after a redundant via has been inserted to via v1 shown in Fig. 8, the timing inﬂuence on each sink can be analyzed by ﬁnding the common path between the via v₁ and each sink node.

ncp(v1, S1) = v1 (3) ncp(v1, S2) = v1 (4) ncp(v1, S3) = n1 (5) ncp(v1, S4) = S0 (6) ncp(v1, S5) = S0 (7) Here,n_cp(v, S) is the node that its upstream path is the common path of the viav and sink S. With the formulas (2) and (3)–(7), the timing information can be efﬁciently predicted and updated.

The conventional timing analysis method reanalyzes the timing values of all nodes on the net and needs to recalculate the downstream capacitance of each node. The runtime complexity of the conventional method is O(n), andn is the number of nodes o the net. Therefore, compared with the conventional method, the developed method is more efﬁciency.

IV. MBCGRAPH MATCHING PROBLEM

Lei et. al [8] proposed and deﬁned the MBC graph matching problem with three essential deﬁnitions. The ﬁrst deﬁnition constructs a via-candidate bipartite graph that includes the set of single vias on one side and the set of corresponding RV candidates on the other side. The second deﬁnition constructs a candidate relative graph that shows the relationship between RV

Algorithm: Sink Node Timing Check for Adding RV Candidate Input:

CRV: a redundant via candidate on neti S1, · · · , Sn_i: sink nodes of neti

tS1, · · · , tS_ni: original sink delays atS1, · · · , Sni, respectively Output:

Satisfaction or Violation

01 Find the delta RC values of equivalent acyclic RC circuit of CRV by utilizing Fig. I or Fig. II

02 For sink nodes fromS1toSn_i

Fig. 9. Sink Node Timing Check for Adding RV Candidate Algorithm

constructed by deﬁnition one and deﬁnition two to become a MBC graph.

Fig. 10 illustrates the above three stages for constructing a MBC graph. Given a postrouting design with RV candidates shown in Fig. 10.(a), the via-candidate bipartite graph is shown in Fig. 10.(b), and Fig. 10.(c) displays the conﬂicts between RV candidates. Combining the graphs shown in Fig. 10.(b) and Fig. 10.(c), the MBC graph is shown in Fig. 10.(d).

The goal of MBC graph matching problem is to ﬁnd the maximum matching RVs in a given MBC graph.

Fig. 10. An example of MBC graph. (a) A postrouting design with RV candidates. (b) Via-candidate bipartite graph. (c) Candidate relative graph. (d) MBC graph.

V. TIMINGDRIVENREDUNDANTVIA INSERTION

Based on the MBC graph, the relationship between the single via set and RV candidate set are well connected. Here, we are going to present the developed timing-driven minimum weighted matching (t-MWM) algorithm to solve the MBC graph matching problem and use the timing check algorithm shown in Fig. 9 to efﬁciently check the sink node timing as if an RV candidate is inserted on a speciﬁc net.

A. Edge Weight Assignment for the MBC Graph

Given a constructed MBC graph, an edge weight value ω(e) between a single via and its speciﬁc RV candidate needs to be assigned. This edge weight is determined by several properties between this single via and its relative RV candidates as follows.

ω(e) = ρ · (α × F.N. + β × C.D. + γ × C.T.) (8) Here, α, β and γ are user-deﬁned constants. The ρ is a timing violation indicator which is equal to inﬁnity (i.e., this RV cannot be a candidate) if inserting the RV candidate will violate the timing-constraint, and it is equal to1 if inserting the RV candidate won’t violate the timing-constraint. The key factors,F.N., C.D.

andC.T. are

1) Feasible number (F.N.): It is the number of feasible RV candidates that a single via has, and the maximum number is4.

2) Conﬂict degree (C.D.): It is the number of conﬂicts be-tween one RV candidate and the rest RV candidates.

3) Candidate type (C.T.): For the manufacturing reason, we prefer to insert on-track RVs rather than off-track RVs. The value ofC.T. is equal to 0 if it is an on-track RV candidate;

otherwise, the value ofC.T. is assigned to be 1.

B. Two Phase t-MWM Algorithm for a MBC Graph

The HMWM algorithm was used for solving the RV in-sertion problem in [8] but it is not suitable for the timing-driven redundant via insertion. To deal with timing constraints, we propose a two phase t-MWM algorithm that utilizes the properties of HMWM algorithm and considers timing issues.

Fig. 11 shows the individual phase ﬂowchart of the proposed two phase t-MWM algorithm. For each phase, similarly with HMWM algorithm [8], ﬁrstly, t-MWM algorithm assigns a suitable weight for each edge in the MBC graph and sorts the edge weights in the increasing order. Then, t-MWM algorithm picks up the RV candidate connected with the minimum edge weight, and the MBC graph is updated. Finally, above steps are repeated until there is no more RV candidate.

Compared with HMWM algorithm, the primary differences are that the edge weight assignment step considers the timing effect in t-MWM algorithm, and t-MWM algorithm re-analyzes the timing of modiﬁed circuit while performing the “edge weight update”

step. Owing to inserting an RV will alter the net timing behavior, the timing effect on the same net should be recalculated. However, estimating the timing effects frequently is time-consuming and exhausted. To alleviate the computation load of updating timing effects, t-MWM algorithm utilizes the proposed timing check algorithm shown in Fig. 9 to check and update the sink-node timing for adding an RV candidate.

Phase 1 of t-MWM algorithm simpliﬁes the problem and handles RV candidates that have no conﬂicts. In this phase,

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