Chapter 1 Introduction
1.3 Introduction to Resistive Random Access Memory
1.3.4 Resistive Switching Mechanisms
Although the exact resistive switching mechanism is a controversial issue, the filament model is often used and accepted extensively [20]. The filament model explains that the RS happened because of the formation and
rupture of the conducting filaments. The conducting filaments are confined, local and so tiny that is hard to be analyzed, and therefore, lots of nanoscale analysis instruments are necessary for filament studying. The electrical observations of filamentary conductions for RS are proposed by current bias method as well. By this method, the intermediate resistance states and anomalous resistance fluctuations between resistance states are observed during the transition from HRS to LRS, which is interpreted to be associated with filamentary conducting paths with their formation and rupture for the RS memory switching.
The oxygen migration near the interface of electrode layer and resistive layer is also a very popular way to explain the bipolar RS mechanism.
Because the oxygen ions migrate by applied voltage bias, the oxygen vacancies are generated to allow electrons go through the insulator easier.
The oxygen vacancy generation switches the device into LRS. As the opposite bias applied, the oxygen ions are pushed back into the insulator to fill the oxygen vacancies and switch the device back into HRS. This oxygen migration model usually combines with SCLC carrier conduction mechanism.
Chapter 2
Experimental Details
2.1 Fabrication of Resistive Switching Memory Devices
2.1.1 Sample Preparation
The Indium Tin Oxide (ITO) -coated glass was used for the TRRAM substrate. The ITO-coated glass was cleaned by the standard cleaning process. The cleaning procedures for ITO-coated glass substrate are as the following steps：
Step 1：ITO-coated glass substrate is taken into DI (de-ionized) water bath with ultrasonic oscillator environment for 10 minutes to remove the particles.
Step 2：Using nitrogen gun to dry the ITO-coated glass substrate, and repeat step 1.
Step 3：ITO-coated glass substrate is taken into acetone liquor bath with ultrasonic oscillator environment for 10 minutes to remove the organic residues.
Step 4：Using nitrogen gun to dry the ITO-coated glass substrate, and repeat
step3.
Step 5：ITO-coated glass substrate is taken into isopropyl alcohol liquor bath with ultrasonic oscillator environment for 10 minutes.
Step 6：120℃ baking for 15 minutes.
After the standard cleaning process, the substrate with bottom electrode was well prepared and ready to the next process. A 25-nm-thick HfO2/Al2O3
multi-layer stack resistive switching film was deposited on the cleaned ITO-coated glass substrate by atomic layer deposition (ALD) system.
2.1.2 Atomic Layer Deposition of Resistive Switching Layer
After the standard cleaning process, the resistive switching layer is going to be deposit on the bottom electrode. Atomic layer deposition is a chemical vapor deposition (CVD) method of self-limiting thin film deposition. (the amount of film material deposited in each reaction cycle is constant), continuous surface chemistry that deposits conformal thin-films of materials onto substrates of varying compositions. By keeping the precursors separate throughout the coating process, atomic layer control of film growth can be obtained as fine as ~0.1 Å (10 pm) per monolayer. Separation of the precursors is accomplished by a purge gas (typically nitrogen or argon) after each precursor pulse to remove excess precursor from the process chamber and prevent 'parasitic' CVD deposition on the substrate.
The HfO2/Al2O3 multi-layer stack resistive switching film is deposited
by Savannah 100 ALD system (Cambridge Nanotech Inc.) with 100℃
deposition temperature. During the deposition, the chamber base pressure is set at 0.1 torr and the carrier gas for the precursors was high-purity N2 gas (flow rate＝20 sccm). The precursors of Al2O3 are trimethylaluminum (TMA) and H2O and the precursors of HfO2 are Tetrakis (dimethylamino) hafnium (TDMAHf) and H2O. The sequence of pulses for one cycle deposition of Al2O3 is TMA (0.03s)/ purge (5s)/ H2O (0.05s)/ purge (5s), and the TDMAHf (1s)/ purge (5s)/ H2O (0.05s) purge (5s) sequence is defined as one cycle deposition of HfO2. A cycle produced ~1 Å as determined by ellipsometry (EP3, Nanofilm Tech.). This method is used for stacking the three different kinds of period multi-layer resistive switching layer.
2.1.3 Top electrode
We use two kinds of top electrode, one is a 100nm-thick ITO conducting film deposit by DC sputtering and the other is the tungsten probe electrode to form the MIM sandwich structure. Sputtering deposition is a physical vapor deposition (PVD) method of thin film deposition, ejecting materials from the target onto the sample surface.
2.2 Material Analyses
2.2.1 X-ray Diffraction (XRD)
The crystal structure of the RS layer is investigated by the X-ray diffraction. The scanning step was 0.02°, and the scanning speed was 4°/min.
According to the theory of X-ray diffraction, the average grain size of each orientation can be estimated by using Scherrer’s equation.
2.2.2 Transmission Electron Microscopy (TEM)
Transmission electron microscopy is used for observing the thickness, interface and the specific local region of the resistive random access memory device. When electron beam is transmitted through an ultra thin specimen and interacting with it, an image can be generated by the transmission electrons. This image is focused and magnified by an objective lens and to be detected by an image sensor, then turns into a digital picture.
2.2.3 Atomic Force Microscopy (AFM)
Atomic force microscopy is used for detecting the surface roughness and the surface morphology of thin films.
2.3 Electrical Analyses
2.3.1 Current-Voltage Measurement
The current-voltage (I-V) characteristics of the resistive random access
memory devices are performed by Agilent 4156A. The resistive switching phenomenon is that the resistivity of the device can be altered by applying a specific voltage bias, which is reproducible. During the switching into the low resistive state (LRS), a large current pass through the device and a current compliance is imposed on the device to prevent the electrical damage.
2.3.2 Endurance Measurement
The endurance is the number that a device can be stably operated among various memory states by sweeping voltage bias, and the endurance cycle with excellent stability is expected to be as large as possible. The more endurance cycles the device can reach means the more stable the device is.
Endurance measurement by sweeping voltage bias is achieved by Agilent 4156A.
2.3.3 Data Retention Time Measurement
The data retention time is the time of the stored data which can be kept without any power supply. Two identical devices are switched into different resistance states. After a specific period of time, read voltage is applying to read the resistance of the device. The read voltage is the voltage used for reading the resistance in the endurance measurement, which cannot change the device into another resistance state. The data retention time measurement is measured by Agilent 4156A.
2.3.4 Nondestructive Readout Measurement
The nondestructive readout measurement is applying a DC voltage bias to read the current of various memory devices to estimate the maximum read time and the stability of the memory states. The nondestructive readout measurement is measured by Agilent 4156A.
Chapter 3
Result and Discussion
3.1 Physical Analysis of Multi-layer Resistive Switching Film
We show our physical analysis result in this section. The reasons why we use glass for substrate and ITO for electrode are making fully transparency device. It is named transparent resistive random access memory (TRRAM). In order to investigate how resistive switching works in amorphous oxide layer, we design our resistive switching layer into a series of multi-layer oxide insulator by Atomic layer deposition. A ratio 6:1 for HfO2 : Al2O3 has been chosen and make it to 38-cycle to reach about 25nm oxide thickness. Because this sample changes its material 76 times in about 25nm, it is not enough thickness for getting crystallized. Then we double the thickness of each cycle but deposited half cycles of the multi-layer insulator.
Then do it again. Here comes our three samples, Sample 1 (HfO2:Al2O3=6:1, 38-cycle, 260 Å), Sample 2 (HfO2:Al2O3=12:2, 19-cycle, 260 Å) and Sample 3 (HfO2:Al2O3=24:4, 9-cycle, 260 Å). In this thesis, we named these samples by its cycles, 9-cycle, 19-cycle and 38-cycle. After depositing the resistive switching layer, we use DC sputtering to deposit 100 nm ITO as the top electrode of resistive memory devices. Also we use the tungsten probe as top electrode of resistive memory devices. In this thesis, we discuss the tungsten probe top electrode memory device mostly.
The transmittances of the three samples are measured in the visible light region from 400 nm to 800 nm wavelength. Fig. 3.1.1. The transmittance including the substrate is approximately 81% averaged, maximum: 86%, minimum: 76%.
The cross-section HR-TEM images of the three samples with ITO top electrode are shown in Fig. 3.1.2, Fig. 3.1.3 and Fig. 3.1.4. Obviously, we can see the multi-layer configuration of 9-cycle and 19-cycle in Fig. 3.1.2 and Fig.
3.1.3. In addition, because of each Al2O3 layer has only one monolayer in 38-cycle, it has no interface configuration in oxide layer as we expected before and is shown in Fig. 3.1.4. Each sample demonstrates analogous amorphous phase type. Moreover, the bottom electrode ITO films showed nearly polycrystalline configuration. The oxide layer thickness of each sample is about 26nm.
The surface roughness is measured by AFM, as shown in Fig. 3.1.5, Fig.
3.1.6 and Fig. 3.1.7. The mean roughness of the samples is about 2~3 nm. As a result, 9-cycle has the smoothest surface. And the Fig. 3.1.8 shows the XRD patterns of these samples. The four peaks at 30.2°, 35.3°,50.6°, and 60.1° are caused by the bottom electrode ITO film. Therefore, according to these XRD patterns the multi-layer resistive switching layers are amorphous films, as we expected before.
Fig. 3.1.1 Optical transmittance spectrum of 9-, 19- and 38-cycle devices
400 500 600 700 800
0
ITO/HfO2+Al2O3...(19 cycle)/ITO/Glass
Transmittance(%)
Wavelength(nm) (b)
400 500 600 700 800
0
ITO/HfO2+Al2O3+...(9 cycles)/ITO/Glass
Transmittance(%)
Wavelength(nm) (a)
400 500 600 700 800
0
Fig. 3.1.2 The cross section HR-TEM images of ITO/9-cycle/ITO memory devices
ITO
ITO
9-cycle
Fig. 3.1.3 The cross section HR-TEM images of ITO/19-cycle/ITO memory devices
ITO
ITO
19-cycle
Fig. 3.1.4 The cross section HR-TEM images of ITO/38-cycle/ITO memory devices
ITO ITO
38-cycle
Fig. 3.1.5 The surface AFM images of 9-cycle
9-cycle
9-cycle
Fig. 3.1.6 The surface AFM images of 19-cycle
19-cycle
19-cycle
Fig. 3.1.7 The surface AFM images of 38-cycle
38-cycle
38-cycle
20 30 40 50 60 70 80
ITO (2 1 -5)
ITO (1 2 -4)
ITO (2 1 -2)
Intensity (a.u)
2 theta (θ)
ITO/Glass HfO2+Al2O3+...(38 cycles)/ITO/Glass HfO2+Al2O3+...(19 cycles)/ITO/Glass
HfO2+Al2O3+...(9 cycles)/ITO/Glass
ITO (0 0 3)
Fig. 3.1.8 The XRD patterns of 9-cycle/19-cycle/38-cycle
3.2 Electrical characteristics of resistive switching layer
In order to turning the insulator film into a resistive switching layer, we have to apply the forming process. In previous report [21]-[23], the forming process is defined as applying a high voltage bias to make a soft breakdown (SBD) happened to the insulator film, and this SBD switches it form original state to LRS. After forming process, multi-layer resistive switching memory device can be switched between LRS and HRS. Fig 3.2.1, Fig 3.2.2 and Fig 3.2.3 show the I-V curve of these devices. Obviously, the hysteresis can be observed for The-9-cycle devices /19-cycle/38-cycle.
Fig 3.2.1 Resistive switching behavior of 9-cycle
Fig 3.2.2 Resistive switching behavior of 19-cycle
Fig 3.2.3 Resistive switching behavior of 38-cycle
3.3 Resistive Switching Properties of Multi-layer Resistive Switching Film
In this section, we demonstrate the electrical properties of basic resistive switching characteristics, set/reset voltage distribution dispersion, retention time, endurance cycles and resistances of LRS and HRS
3.3.1 Electrical Property
At the first time we applying a negative voltage bias on the device, the forming process, filaments have been formed in the device, the device has been switched to LRS. Then a positive voltage bias is applied on the device, this reverse bias could switch the device back into the HRS, this is called the reset process. After the forming process and the first reset process, a negative voltage bias apply to the device again and this time it could make the device switch to LRS again, this is called the set process. Then we could keep doing set and reset process to make the device switch between LRS and HRS again and again.
When set process is happening the device switched to LRS. It needs a current compliance in order to protect the device from the permanent damage by sudden high current. This current compliance is also a very important
operation parameter of the device. Different compliance currents cause different LRSs. As shown in Fig. 3.3.1 , the larger compliance currents enhance hysteresis curve. This means the larger compliance current cause lower LRS, as shown in Fig. 3.3.2. The lower LRS also induce lager HRS/LRS ratio. This phenomenon might be attributed to that because lager compliance current forms stronger conducting filaments and cause the LRS becoming lower. In this reset process, the stronger conducting filaments need more energy power to rupture [24]. However, X. CaO et al. [25] believed that the switching current and voltage depend on the microstructures and stoichiometric of the materials. According to Kim et al [26], this can be related to the average power dissipated at SET and RESET processes.
The reason of filament rupture can be considered of the temperature of forming filaments, using the steady state temperature model, where the equation is given by Tm=(T04
+J2ργ/2Pw)1/4 [27]. Tm is the filaments temperature raised by Joule heating, T0 is the room temperature (=300K), J is the current density, ρ is the sample resistivity. γ is the filament radius, and PW is the radiative loss parameter of the filament. This result about the Joule heating effect is important factor for the RESET. However, there is another way to enlarge the HRS/LRS ratio. As shown in Fig. 3.3.3 and Fig. 3.3.4, the lager stop voltage can also enhance the hysteresis curve by making the HRS higher. These two phenomena help us to decide what compliance current and stop voltage we should chose for operating the device. And these two phenomena had been discovered by HY. Lee et al [11].
We chose 500 uA for compliance current and 5 V for stop voltage to
endurance experiment and read HRS/LRS resistances by 0.1 V. The results of these devices are shown in Fig. 3.3.5, Fig. 3.3.6 and Fig. 3.3.7. Obviously, these three kinds of devices have very different result. The-9-cycle devices has the best performance over 1250 cycle times. The 19-cycle could be operated to about 950 cycle times. And the 38-cycle has a result about 300 cycle times. Therefore, the set/reset voltage distributions are shown in Fig.
3.3.8, the average set voltage and the standard deviation are -1.258 V, 0.162 V (9-cycle), -1.927 V, 0.92 V (19-cycle) and -1.706 V, 0.932 V (38-cycle), the average reset voltage and the standard deviation are 1.275 V, 0.193V (9-cycle), 1.867 V, 0.375 V (19-cycle) and 1.412 V, 1.131 V (38-cycle).
Obviously 9-cycle has the tighter distribution of set/reset voltage and the operation voltage is also the smallest. According to the above result, 9-cycle must have some good property that can help the resistive switching become more stable. And the comparison of these devices is shown in Table. 3.3.1.
3.3.2 Resistive Switching Localization Test
We wonder what mechanism is of the resistive switching and what cause the difference among the three devices. So we start with the resistive switching localization test. Here we have to make a description of how we operate the device. Generally, the typical set/reset process is applying a voltage bias to the top electrode and the bottom electrode is grounding. In this test, another tungsten probe is used for second top electrode and is grounding as the bottom electrode used in typical set/reset process, as shown in Fig. 3.3.9. Unlike the typical operation, this test is just like applying a
apply the voltage bias on the twice thicker resistive switching layer with a conducting ITO layer in the middle and this middle conducting layer could split the resistive switching layer into two sides, the anode side and the cathode side. Where the anode side is defined by the voltage bias we applied for the forming process. Here we use negative bias for the forming process, so the side we applied bias is the cathode side and the other side, which is grounding, is the anode side. We can apply a small read voltage bias to get to know the resistance of both side and find out which side is the resistive switching happening.
This experiment had been done by KM. Kim et al [28]. The READ 1, READ 2 and READ 3 are shown in Fig. 3.3.10. READ 1 finds out the resistance of the cathode side and READ 2 is going to read the resistance of the anode side. READ 3 helps us to know if the device has been separated into anode side and cathode side by calculate the READ 1 resistance plus READ 2 resistance is equal to the READ 3 resistance. The results of this resistive switching localization test are shown in Fig. 3.3.11, Fig. 3.3.12 and Fig. 3.3.13. Obviously, all the READ 1 resistances are not switching, but the READ 2 resistances are switching its resistance after each set/reset process.
Even though the conducting filament is going through the entire resistive switching layer, the resistive switching could still be localized on the anode side.
3.3.3 Retention Time Property
As a nonvolatile memory, storing data without applying bias is a very important property. The retention time means how long does the data can be stored in the memory. The devices had been put in our retention time experiment and could stored data more than 104 seconds at room temperature, as shown in Fig. 3.3.14, Fig. 3.3.15 and Fig. 3.3.16, and are without apparently degradation. Therefore, these three devices could be developed as nonvolatile memories.
3.3.4 Nondestructive Readout Property
The previous section mentioned that we use 0.1V bias to read the resistance. Therefore, a no destructive read out experiment gives to the devices to find out does the small read voltage really not affect the resistance state. Each device is applying a voltage bias of 0.6V, which is much larger than the 0.1V read voltage, to read the current of various memory states. All the devices can survive more than 2000 seconds at RT, based on this result, as shown in Fig. 3.3.17, Fig. 3.3.18 and Fig. 3.3.19, the maximum read times and the stability of the memory states can be estimated.
-2 -1 0 1 2 3 ITO/HfO2+Al2O3+...(19cycles)/ITO/Glass
Current (A)
Voltage (V)
A
Fig. 3.3.1 (I-V) Different LRS due to different compliance current for 19-cycle
1 2 3 4 5
Fig. 3.3.2 (R-I) Different LRS due to different compliance current for 19-cycle
-2 -1 0 1 2 3 ITO/HfO2+Al2O3+...(19cycles)/ITO/Glass
Current (A)
Voltage (V)
Vstop
Fig. 3.3.3 (I-V) different stop voltage cause different HRS for 19-cycle
1.6 2.0 2.4 2.8 3.2 3.6 4.0
Fig. 3.3.4 (R-V) different stop voltage cause different HRS for 19-cycle
Fig. 3.3.5 Endurance experiment of 9-cycle
Fig. 3.3.6 Endurance experiment of 19-cycle
Fig. 3.3.7 Endurance experiment of 38-cycle
Fig. 3.3.8 Set/Reset voltage distribution of 9cycles/19-cycle/38-cycle
Fig. 3.3.9 The set/reset process of resistive switching localization test
Fig. 3.3.10 READ 1, READ 2 and READ 3 in resistive switching localization test
Fig. 3.3.11 READ 1/READ 2 resistances of 9-cycle by resistive switching localization test
Fig. 3.3.12 READ 1/READ 2 resistances of 19-cycle by resistive switching localization test
Fig. 3.3.13 READ 1/READ 2 resistances of 38-cycle by resistive switching localization test
Fig. 3.3.14 Retention time experiment of 9-cycle
Fig. 3.3.15 Retention time experiment of 19-cycle
Fig. 3.3.16 Retention time experiment of 38-cycle
Fig. 3.3.17 Nondestructive readout experiment of 9-cycle at 0.6V
Fig. 3.3.18 Nondestructive readout experiment of 19-cycle at 0.6V
Fig. 3.3.19 Nondestructive readout experiment of 38-cycle at 0.6V
Table. 3.3.1 Comparisons of 9-cycle, 19-cycle and 38-cycle device
3.4 Conduction Mechanism of Resistive Switching Layer
Fig. 3.4.1, Fig. 3.4.2 and Fig. 3.4.3 show the double-logarithmic plots of current-voltage curve for negative bias in set process for 9-cycle, 19-cycle and 38-cycle with the fitting results. Obviously they show I∝V at first in low voltage region and then show I∝V2 characteristics with the increase of voltage bias. This is the typical behavior of trap-controlled space-charge-limited current (SCLC) behavior. Because it happens before set process gets finished, this SCLC behavior stands for HRS carrier conduction mechanism[11][14].
And Fig. 3.4.4, Fig. 3.4.5, Fig. 3.4.6 show the double-logarithmic plots of current-voltage curve for positive bias in reset process for 9-cycle, 19-cycle and 38-cycle with the fitting results and I∝V relation can be observed. So the Ohmic conduction mechanism could stands for the carrier conduction mechanism of LRS in the resistive memory. Also the HRS fit well as SCLC here, this echo the statement in the above paragraph.