Chapter 2 An Interconnecting Technology for RF MEMS
2.5 Results and Discussions
2.5.1 Bumpless Interconnect Bonding
Figure 2.12 shows the micrographs of the CMOS chip before and after being diced and the as-fabricated silicon carrier, respectively. The dashed lines in Figure 2.12(a) indicate the dicing traces that are cut for bonding, as shown in Figure 2.12(b). The reference plane is defined at the edge of contact pads using thru-reflect-line (TRL) calibration [47] for RF characterization, as shown in Figure 2.12(c). The air bridge between two grounds is used to inhibit odd-mode excitation in the CPW. The CMOS chip and the Si carrier, which contain microstrip lines and CPWs, respectively, are bonded together under the conditions of 300°C at the carrier, 180°C at the chip, and 50 MPa applied pressure for 3min.
Figure 2.13 shows the SEM photographs of the chip-to-carrier assembly.
An enlarged view of the SEM picture on the bonding interface shows that there
is about 2 μm misalignment. The misalignment is caused by the malfunction of interlocking resulted by the overplating of Zn/Ni/Au layers on the Al pad.
Such a malfunction can be further resolved by a better process control. After forcefully pulling the bonded CMOS chip away from the Si carrier, it is found that a cross-alignment mark on the carrier is totally transferred and attached onto the CMOS chip [Figure 2.14(a)], or the Cu line deposited on the carrier can be lifted [Figure 2.14(b)]. The results indicate that the Au–Au thermocompressive bond is strong enough to break the interface between Ti and SiO2, which is about 100 MPa [48].
2.5.2 Electrical Characterizations of the DC Contact and the RF Transition Structure
The DC contact resistance is measured using DC probe station and Keithley 2000 multimeter. The contact resistance is calculated as aforementioned which is about 14±5 mΩ for each circular bonding pad of 0.4 μm Au/1 μm Ni with a radius of 20 μm. Since the contact resistance is about two orders smaller than equivalent series resistance of inductor, it doesn’t have to take into account of DC ohmic loss at interconnection joint in RF SOP integration design.
Two-port S-parameters of the transition structure are measured using Agilent E8364B PNA and Cascade Infinity GSG probe in the frequency range from 10 to 50 GHz, as shown in Figure 2.15. The measured S-parameters have excluded the parasitic effect from measurement pads and have a reference plane to the edge of the bonding pad via TRL calibration. The assembly technique provides about −1.7 dB insertion loss and −15 dB return loss at 40 GHz, including the transmission loss of the microstrip line. After detail
investigations, the discrepancy from the simulation results and the measurement results might be due to underestimate of substrate conductivity in the carrier.
From the measurement results of the CPW, the conductivity of the Si substrate is extracted as 75 S/m, much higher than the initial assumption of 10 S/m. This higher silicon conductivity will cause CPW become lower characteristic impedance and more dispersive, but Z0 of the microstrip line is still kept around 50Ω. High substrate conductivity also contribute more signal loss to flip-chip interconnect due to propagate of EM fields in the lossy substrate. The revised high-frequency structural simulation at 75 S/m silicon conductivity shows comparable S11 and S21 values as compared with the measurement result.
Nevertheless, the measurement result has revealed that the low loss and wide bandwidth characteristics of the bumpless interconnecting technology have the potential for RF chip integration.
2.5.3 UWB LNA with MEMS Inductors
Figure 2.16 shows the SEM picture of the as-fabricated LNA circuit using the proposed bumpless chip assembly technique. Figure 2.17 shows the comparison between simulated [Figure 2.17(a)] and measured [Figure 2.17(b)]
S11 and S21 with a different tuning voltage in the LNA circuit. There are discrepancies in S11 and gain degradation. The bandwidth of measured S11 is narrower than that of the simulation one and varied with the tuning voltage.
The discrepancy could be caused by EM field coupling within inductors, which would result in input mismatch. The proximity and interconnect trace of inductor can cause the coupling between coils. In terms of LNA circuit design, the four MEMS inductors on Si carrier are individually designed in HFSS at the
beginning, so the proximity effect is not considered in the initial design. After made effort to debug, the measurement result can be verified by full-layout simulation as shown in Figure 2.17(c). The effect, in fact, can be resolved by adding guard rings around the inductors for the enhancement of EM signal isolation and by removing more Si underneath the inductors for Q enhancement to realize higher gain performance.
2.5.4 Discussions
Although the function of self-interlocking was not fully demonstrated in this experiment due to the overplating of the Zn/Ni/Au layer on the CMOS chip, it can be resolved by process optimization. Nevertheless, it is noted that Ni, in the bonding scheme, not only plays a role as a seeding layer for following Au plating but also acts as a diffusion barrier to Au. In this work, the Au–Au thermocompressive bond is chosen to realize bumpless interconnecting unlike the under-bump metal (UBM) of the packaging, where the Au layer is only used as a wetting layer to the solder for FC bonding. Thus, to effectively prevent Au from diffusing into a CMOS chip, to have a strong Au–Au bond, and to maintain self-interlocking mechanism, further process characterizations, including the thickness control of the Ni/Au metallization and related bonding quality and reliability investigation, are required for having an optimal process condition for manufacture applications. In fact, in comparison with the other two kinds of Au–Au thermocompressive bonding techniques proposed for FC applications, i.e., the Au bump and the Au stud bump, as listed in Table 2.1 [49,50], the presented Ni/Au bumpless metallization for Au–Au thermocompressive bonding has shown a great potential in chip integration with the characteristics of high
throughput, flexible bump geometry and pitch size, low cost without a lithography process, and almost zero bump height for high-frequency signal transition. In addition, the previous study has shown that the electromigration of a typical Pb-free solder using Ni-P/Au UBM is mainly caused by the movements of Sn atoms against the electron flow [51]. Since there is no Sn solder required in the bonding scheme, a better electromigration characteristic can be expected.
The bumpless interconnecting technology can provide low parasitic capacitance and small contact resistance for chip assembly and make the electrical joint behave like a simple interconnect line, which can reduce IC design complexity, provide process flexibility, and make the whole system perform like the SOC. Thus, in addition to MEMS inductors, RF MEMS components, such as switches, tunable capacitors, inductors, antennas, and BAW resonators, can be easily implemented for RF microsystem fabrication based on the heterogeneous chip integration scheme with the bumpless interconnecting technology. Although this work only demonstrated an integration of a CMOS chip to a silicon carrier, the scheme can be utilized for a CMOS chip to a CMOS chip, a MEMS chip, or a III–V chip integration, and to provide an alternative technique for heterogeneous integration applications without modifying the existed chip design. Owing to the intrinsic characteristic of heterogeneous chip integration, the scheme can further ensure a cost-effective CMOS-MEMS fabrication process without sacrificing system performance as the scaling of CMOS technology is down to 90 nm or even further.