Thesis organization

The chip of our design is fabricated by the UMC 0.5um +/-20V2P2M high voltage process. It can works under 10V to 18V of supply voltage. With a supply voltage of 15V and an output resistor load of 8Ω, output power will be 2W with 0.062% THD. The quiescent current of this chip is 20mA typically. The chip dimension is 2210um x 3497um with an additional test key.

1.4 Thesis organization

This thesis aims to improve the design of linear audio amplifier output stage. In Chapter 2, we will further discuss in detail the structure of Class-AB output stage proposed by this thesis. Also, we will show how the functions of mute, standby, and volume control are realized in actual circuit design. Finally, in the last part of Chapter 2, we will provide the results of pre-simulation. In chapter 3, the complete layout and results of post-simulation will be shown. Chapter 4 mainly concludes the distinguishing features and contributions of this thesis, and it also provides possible work and improvements from a future perspective.

CHAPTER 2

Architecture and circuit design

2.1 Design specification and consideration

Class-AB single-ended audio amplifier with high supply voltage and high output power is not that popular a research target in the academic arena, so we turn to search for some product specifications of several well-established semiconductor corporations for reference.

These include companies such as STMicroelectronics, TEXAS INSTRUMENTS, National Semiconductor, and so on. They all have products with similar applications of single ended Class-AB audio amplifiers that work under a wide supply voltage range, 10V~18V. However, limited by our choices of process and packaging, we in the end choose ST-TDA7469L [11] to be the reference of our design spec., and lay down our design targets as in Table 2-1.

(Testing condition VS = 14V; RL = 8Ω, Temp=25℃)

Symbol Parameter Test condition Value Unit

Vs Supply voltage range 10~18 V

Iq Total quiescent

current <50 mA

PO Output power THD=1%, RL=8Ω >1.3 W

THD Total harmonic

distortion PO=1W, f=1kHz <0.4 %

BW Unit gain bandwidth >0.6 MHz

Ipeak Out peak current <1.1 A

PSRR Power supply

rejection ratio F=1kHz >50 dB

Table 2-1 Design Specifications of this work

2.2 Full circuit architecture

Fig.2.1 shows the block diagram of this chip [11]. The stereo audio channel consists of two buffered amplifiers, OP1A and OP1B, and two volume control amplifiers, VCA and VCB. Another open loop buffered amplifier, OP1C, is just for testing. The two unit gain buffers, OP2A and OP2B, are to be used as earphone output, and their structures are the same as OP1A

and OP1B, respectively, but differently sizing. Both of the two volume control amplifiers are controlled by a simple analog to digital converter, A_D. The mute control circuit is also contained in A_D. The function block, BIAS, including the standby control function, produces all needed current sources for each circuit.

We define the output reference voltage as

2

SS DD REF

V

V V −

= . The 8 Ohm load resistance will connect the output and V_REF through a capacitor outside the chip. V_REF is also taken as the common mode voltage in the close loop buffered amplifier. The unit gain amplifier, OPVREF, is used to drive the reference voltage, V_REF.

VC

^B

VC

A

OP

^1A

OP

1B

OP2B

OP2A

BIAS Vin_L

Vin_R

ER_Out_L

ER_Out_R

Out_L

Out_R Volume Vref

OP

^1C

VDD

VSS Vref

R1 R2

R2 R1

A_D

OP

^VREF

VMID

Figure 2.1 The block diagram of this chip

2.3 Buffered amplifier

Table 2-1 lists the required design targets. The design constraints include a highly supply voltage ranging from 10V to 18V, and an impedance load as low as 8 Ohm. Our design target is to achieve < 0.4% THD, and control the system’s quiescent current as low as 50mA. In section 1.1.1, we introduced a lot of architecture and circuits of Class-AB output buffers.

Some of them ([6] [8] [9]) may take up too much chip area to be used in high-power output applications, and some [7] may not be suitable for a high supply voltage range (10V~18V) to maintain stable linearity and acceptable quiescent current. Also, two other attractive structures can be referred to as in [12] [13]. However, to meet the high-power output requirement, these simple structures have big problems to compromise between current consumption, linearity and chip area.

Figure 2.2 The block diagram of buffered amplifier

2.3.1 Architecture of buffered amplifier

We as a result propose a new set of error amplifiers which form the common-source configuration output stage with the function of short circuit protection. Besides, we use a two-stage amplifier as the pre-amplifier to get a high gain in the gain stage. These two parts form a buffered amplifier as show in Fig.2.2.

2.3.2 Error amplifier for output buffer

Fig.2.3 shows a schematic of the error amplifier EP and M1 from Fig.2.2. A

complementary structure used to drive M2 is shown in Fig.2.4. For convenience, we take EP as the example for the following discussion. The error amplifier EP shown in Fig.2.3 can be recognized as an OTA by ignoring transistors MP10B, MP11B, MP13, and MP14. This OTA could provide a high output swing to drive the power transistor M1. The difference between Vin2 and VEP_OUT is sensed by the differential pair MP1 and MP2, which is biased by the tail current source IBP with a current mirror. The load of the differential pair consists of a chain of current mirror branches used to define the quiescent current. Applying similar ideas derived from the circuit shown in Fig.1.7, the source-follower transistors MP13 and MP14 will reduce the output impedance of the error amplifier EP to set its gain to a well-defined low value. The gates of source-follower transistors are biased by a negative feedback loop including MP11, MP11B, MP10B, and MP13. Here the constant current source ISS, as shown in Fig.1.7, is replaced by a variable current mirror source, MP10B, which will change its drain current as the input differential pair senses any difference.

Figure 2.3 Schematic of the error amplifier EP

MOS MBP MP0 MP1 MP2 MP3 MP4 MP5 MP6 W/L(μm) 10/4 10/4 45/5 45/5 10/4 10/4 10/4 10/4

M 1 40 20 20 4 4 4 4

MOS MP7 MP8 MP9 MP10 MP11 MP12 MP13 MP14 W/L(μm) 5/4 5/4 5/4 5/4 50/4 50/4 10/4 10/4

M 2 2 2 2 36 36 4 4

MOS M1 MP11B MP10B MC1 MC2 MC3 MC4 MC5 W/L(μm) 106/3 50/4 5/4 10/4 10/4 10/4 10/4 10/4

M 198 36 4 1 1 1 1 1

MOS MC6 MC7 MC8

W/L(μm) 5/4 5/4 10/4

M 1 1 1

IBP=10uA

Table 2-2 Transistors W/L ratio of Fig.2.3

Figure 2.4 Schematic of the error amplifier EN

MOS MBN MN0 MN1 MN2 MN3 MN4 MN5 MN6 W/L(μm) 25/4 25/4 50/5 50/5 10/4 10/4 10/4 10/4

M 1 20 24 24 4 4 4 4

MOS MN7 MN8 MN9 MN10 MN11 MN12 MP13 MP14

W/L(μm) 5/4 5/4 5/4 5/4 50/4 50/4 9/4 9/4

M 2 2 2 2 20 20 2 2

MOS M2 MN11B MN10B MC1 MC2 MC3 MC4 MC5 W/L(μm) 66/2.5 50/4 5/4 5/2.5 5/2.5 5/2.5 5/2.5 5/2.5

M 182 20 4 1 1 1 1 1

MOS MC6 MC7 MC8

W/L(μm) 5/3 5/3 5/3

M 1 1 1

IBN=10uA

Table 2-3 Transistors W/L ratio of Fig.2.4

To further analyze this newly proposed circuit, let us begin with the quiescent condition.

Therefore, the quiescent current of the output buffer is well-defined as

11 find the gain of the error amplifier in the quiescent condition, we assume that the input differential voltage is small enough so that MP10B can be regarded as a constant current source.

Considering the entire small signal current from the differential pair flows at the error-amplifier output, EP_OUT, the transconductance is

11

In the quiescent condition, g_mP1 = g_mP2, g_mP3 =g_mP4, g_mP5 = g_mP6, g_mP7 = g_mP8,

10

9 mP

mP g

g = , g_mP11= g_mP12, g_mP13 = g_mP14, and g_mP12 >>g_mP14 because I_P12 ≅2I_P14, and the W/L ratio of MP12 is usually much lager than MP14 so as to reduce the quiescent current.

Therefore, we can simplify (2.7) as

The output resistance of the error amplifier is dominated by the source-follower transistor MP13, and

The coefficient

13 ratio of transistors with appropriate bias. In practice, the drain current of MP10B will vary with the input differential voltage, Vd=(Vin1-Vin2). If Vd is negative, MP1 will conduct more tail current than MP2. As the difference increases, so does I_P9, too, but I_P11 decreases. When

11

9 P

P I

I = , MP13 will be cutoff, and the output impedance of the error amplifier is no longer dominated by the source-follower transistor, MP13. The output impedance of the error amplifier R_O ≈

(

r_{O P}9//r_{O P}11

)

, and voltage gain will highly increase to the order about an

O mr

g . This results in an additional benefit. The higher gain of the amplifiers enhances the linearity of output buffer under higher output power operation.

Consider the boundary condition of the above situation. This happens at I_P1 =2I_P2, and

BP

BP

From (2.12), and (2.13), the threshold input differential voltage, which cuts off the transistor MP13, is

However, in practice, there are always some mismatches of the error amplifiers caused by unexpected random effects. If the random offset voltage, VOS, is higher than Vd shown in (2.14), the gain of the error amplifier will increase considerably, and the quiescent current will be out of control. Therefore, Vd is chosen to be bigger than the expected random offset

voltage.

In section 1.1.1, (1.24) shows how to estimate the possible variation of the quiescent current at a given offset voltage. This equation, however, should be modified since the gain of the error amplifier shown in Fig.2.2 will be changed with VOS increasing. Now, define AOS as the changed gain of both two error amplifiers, EP and EN, when VOSP and VOSN exist as shown in Fig.1.5. The equation (1.24) becomes

⎟⎟

The A represents the gain of error amplifiers, EP and EN, affected by V_OS OSP. Review (2.10), the ratio,

Considering how VOSP affects the input differential pair;

2

AssumingV_OV,MP1 >>V_OSP 2,

Applying similar reasoning to (2.2), and (2.5),

7

Substituting (2.19) and (2.20) with (2.16) and rearranging properly,

( )

The above equation shows an important result. To minimize the variation of A affected by _OS VOS, the W/L ratio of

2.3.3 Short circuit protection

Consider the block diagram shown in Fig.2.2 without short circuit protection function. If we accidentally connect the output to VSS or VDD, or operate the chip improperly, M1 or M2 will be damaged or the whole system will be overheated because of the unexpectedly large output current caused by a short-circuited output.

Fig.2.5 shows the schematic of a short circuit protection function for the power transistor M1. A complementary structure used to protect M2 is shown in Fig.2.6. Consider the

transistors MEP1 ~ MEP5, which form an one-stage error amplifier, ESP, used to sense output current. By connecting ESP, MSP1, MSP5 and MSP2 as a feedback loop, the differential inputs of ESP, OUT and VSEN_P can be regarded as virtually short-circuited. Thus the drain current of M1 can be sensed accurately by MSP1 with a ratio of

current mirror so that IMSP5 will provide a nearly constant current to bias MSP2. Without IMSP5, (2.18)

(2.19) (2.20)

(2.21)

MSP2 may be in triode region when MSP1 senses a very small current. Under a condition like this, the feedback loop may be unstable. By adding a compensation capacitor CC1, and appropriately biasing MSP2, the problem of stability can be resolved.

MOS M1 MSP0 MSP1 MSP2 MSP3 MSP4 MSP5 MSP6 W/L(μm) 106/3 6/3 6.6/50 6/12 6/12 6/3 6/3 50/3

M 198 2 1 1 1 12 4 10

MOS MEP1 MEP2 MEP3 MEP4 MEP5 MC1 MC2 MC3 W/L(μm) 6/4 6/4 6/6 6/6 6/3 6/2.5 6/2.5 6/2.5

M 1 1 1 1 1 1 1 1

MOS MC4 MC5

W/L(μm) 6/3 6/3 IB=5uA

M 1 1 CC1=0.5P

Figure 2.5 Schematic of M1 short circuit protection

Table 2-4 Transistors W/L ratio of Fig.2.5

Figure 2.6 Schematic of M2 short circuit protection

MOS M2 MSN0 MSN1 MSN2 MSN3 MSN4 MSN5 MSN6 W/L(μm) 66/2.5 6/6 5/50 6/6 6/6 6/6 6/6 6/2.5

M 182 2 1 2 2 26 4 2

MOS MEN1 MEN2 MEN3 MEN4 MEN5 MC1 MC2 MC3 W/L(μm) 6/6 6/6 6/6 6/6 6/6 6/2.5 6/2.5 6/2.5

M 1 1 1 1 2 1 1 1

MOS MC4 MC5

W/L(μm) 6/3 6/3 IB=5uA

M 1 1 CC2=0.5P

Table 2-5 Transistors W/L ratio of Fig.2.6

MSP1, MSP2, MSP3, and MSP4 can be considered as a current comparator. The transistor MSP2 mirrors a constant current from MSP0, and MSP1 senses a current from M1. When ISP1 is bigger than the set current ISP4, MSP3 will be in triode region, and the voltage at node SW_P will be pulled down to turn on the transistor MSP6. As MSP6 is turned on, the source-gate voltage of M1 will be limited, which enables the function of short circuit protection.

When designing a circuit as shown in Fig.2.5, we will probably focus on the condition where Vout > Vref, under which M1 is turned on. Otherwise, when VOUT < VREF, the

Class-AB output stage will cutoff M1. However, we shall not neglect the effects of the circuit where VOUT < VREF. When VOUT is much lower than VREF, the drain-source voltage of MSP5

is much higher than its gate-source voltage. Considering channel length modulation, IMSP5

may become larger than IMSP4. When the system starts, the voltages at all nodes will be VSS in the beginning. After M1 charges node OUT for a short period of time, VOUT reaches VREF. If IMSP5 gets larger than IMSP4 due to channel length modulation, MSP6 will be turned on, which cuts off M1and consequently stops it from charging node OUT. All these reactions will result in a deadlock. Therefore, the criteria for enabling short circuit protection is

( sin ) 4 5

1Sen g MSP MSP

MSP I I

I > − . That is to say, IMSP4 and IMSP5 should not be set compatible in case of malfunction.

Figure 2.7 Schematic of pre-amplifier using in Fig.2.2

2.3.4 Frequency compensation

The circuit proposed in this thesis is applied to the audio band. Human ears respond to sound vibrations frequencies between 200Hz and 20KHZ. It is there anticipated that

bandwidth is probably not the main concern for an audio amplifier. Take the specifications in Table 1-1 for example, since the design target for Unit Gain Bandwidth is merely0.6MHz, a common two-stage amplifier as shown in Fig.2.7 as the pre-amplifier will do. This

pre-amplifier is designed with a high DC gain and a low bandwidth (0.8MHz). The buffered output stage as discussed in Sec. 2.3.2. is designed with a dominant pole 10 times larger than the unit gain frequency of the pre-amplifier, which saves the complex problem of frequency compensation.

To simplify the stability analysis of the buffered output stage, that pole RC

π 2

≈ 1 is

appropriated here. The circuit shown in Fig.2.3 contains several poles, including nodes, P1, P2, P3, P4, P5, EP_OUT, and OUT. Consider this transistor size listed in table 2-2. The power transistor M1 must be large enough to drive a desired output power, and transistors MP11, MP11B, MP12 can’t be too small to define the quiescent current. Therefore, the parasitical capacitance at node EP_OUT will be the maximum. To obtain a higher gain in the differential

MOS M0 M1 M2 M3 M4 M5 M6 M7

W/L(μm) 6/6 6/20 6/20 6/6 6/6 6/6 6/6 6/6

M 2 10 10 2 2 4 30 30

MOS MC1 MC2 MC3 MC4 IB=1uA W/L(μm) 6/2.5 6/2.5 6/2.5 6/3 R1=40K

M 1 1 1 1 C1=1.5P

Table 2-6 Transistors W/L ratio of Fig.2.7

pair, MP1 and MP2 are usually chosen of a larger size. We can therefore derive the comparisons of parasitical capacitance at these nodes from the size of each transistor as

4 3 5 2 1

_OUT P P P P P

EP

OUT > > > > > > .

Although node OUT carries the biggest parasitical capacitance, it is connected to a resistors as small as 8 Ohm that helps push its pole to the high frequency domain. As a result, the order of poles at all node in the frequency domain will be

OUT P

P P P P OUT

EP_ < 1≈ 2< 5< 3≈ 4< .

As mentioned earlier that MSP13 will be cutoff as the voltage VOUT increases, it will change the equivalent resistance at EP_OUT from

13

1

gmP to (r_O,P9 //r_O,P11), and the pole of EP_OUT will thus move to the lower frequency domain. Therefore, it should be carefully considered whether the moved dominate pole would affect the stability of the pre-amplifier.

(2.22)

(2.23)

Figure 2.8 Schematic of Volume control circuit

R1=480K R2=90K R3=120K R4=90K R5=70K R6=50K R7=40K R8=30K R9=20K R10=20K R11=30K

2.4 Volume control circuit

Fig.2.8 shows the block diagram of the Volume control circuit which is made up of an inverting feedback OPAMP and 9 transmission gates. The schematic of the OPAMP is the same as Fig.2.7, but the dimensions of transistors are different (See Table 2-7). When the switch of a transmission gate is active, the corresponding parallel resistor will become short circuited. When all the transmission gates are switched open, the inverting close loop gain of OPAMP reaches the maximum. As TG1 is active, its close loop gain decreases. When these transmission gates are inactivated in order, a 10 level volume control is therefore made possible.

Since human hearing is measured by the log scale, resistors in this design should be specially chosen so that the 10 level close loop gain is linear in log scale.

That is

Therefore, the fixed difference of each volume level is 20logα .

MOS M0 M1 M2 M3 M4 M5 M6 M7

Table 2-7 An alternative list of W/L ratio of transistors in Fig.2.7.

2.5 DC control 10 level volume

Fig.2.9 shows a simple analog to digital converter. Transistors, MS1~MS9, are mirrored current sources, which are connected to the corresponding NMOS, MV1~MV9, below, to form 9 inverters. By setting that the closer the NMOS is to the right in Fig2.10, the smaller W/L ratio it has, the respective switching voltage of the 9 inverters will be in order as a rising sequence. As VCON increases gradually, these 9 inverters will be switched on one by one.

That is to say, one single DC Voltage VCON is enough to generate a set of 9 control signals, VC[1:9] and VCB[1:9], which is used to control the 9 transmission gates in Fig.2.8. On the other hand, inverters MS10 and MV10 are used as a control signal generator for the MUTE function. When VMUTE gets larger than 2.5V, BUF_EN exports signal 0, and BUF_ENB, 1.

This will turn off power transistors M1 and M2 in Fig.2.2.

INV_C, as shown in Fig.2.9, is a inverter chain. It is illustrated in detail in Fig2.10. The INV_C as an inverter chain is used to make the switch signal transient very fast.

Figure 2.9 A simple Analog to Digital converter

Figure 2.10 Schematic of symbol INV_C shown in Fig.2.9

MOS MB1 MB2 MS1 MS2 MS3 MS4 MS5 MS6

W/L(μm) 4/5 4/5 4/5 4/5 4/5 4/5 4/5 4/5

M 5 1 1 1 1 1 1 2

MOS MS7 MS8 MS9 MS10 MV1 MV2 MV3 MV4 W/L(μm) 4/5 4/5 4/5 4/5 4/2.5 4/3 4/4 4/6.5

M 2 3 3 1 20 2 2 1

MOS MV5 MV6 MV7 MV8 MV9 MV10 M1 M2 W/L(μm) 4/14 4/12.5 4/19 4/18 4/24 4/15 5/4 5/4.7

M 1 1 1 1 1 1 2 1

MOS M3 M4 M5 M6

W/L(μm) 5/5 5/5 5/5 5/5 IB1=2uA

M 1 1 1 1 IB2=2uA

Table 2-8 Transistors W/L ratio of Fig.2.9 and Fig.2.10

Figure 2.11 Schematic of OPAMP used as a buffer for driving Vref

MOS M0 M1 M2 M3 M4 M5 M6 M7

W/L(μm) 5/12 5/9 5/9 5/9 5/9 5/12 5/9 5/12

M 2 4 4 2 2 2 4 2

MOS M8 M9 M10 M11 MST1 MST2 MST3 MST4 W/L(μm) 20/4 20/4 20/4 20/4 5./3 5/25 32/5 5/2.5

M 2 8 2 8 1 1 18 1

MOS MC1 MC2 MC3 MC4 MC5 MC6

W/L(μm) 5/25 5/25 5/25 5/25 5/25 5./3 IB=5uA

M 1 1 1 1 1 1

Table 2-9 Transistors W/L ratio of Fig.2.11.

2.6 Reference voltage generator

In Fig.2.1, we use two diode connecting PMOS to generate the reference voltage,

2

SS DD MID

V

V V −

= . Any current flowing out or into VMID will change its voltage. This is why we need the unit gain buffer, OPVREF. Usually, a very large capacitor is used to connect VREF and VSS to avoid unexpected interference from the power supply. According to the

application notes of TDA7496L, a 470uF capacitor is advised. Fig.2.11 shows the amplifier, OPVREF, with a common-drain output stage. With an output capacitor load so big as 470uF, the output node of the amplifier will be the dominate pole in frequency domain. Consider the transient at the start. It may take a very long time to charge the 470uF capacitor load to the required voltage,

2

SS DD V V −

. Transistors MST1~MST4 are therefore used to shorten the charging time. When the system is shut down, the control signals will be EN=Low,

ENB=High. All of the voltage at node N1, N2, N3, N4, MID, OUT will be Low, too. However, when the system starts, the control signal is reversed, and the VMID will be high enough to trigger the inverter, MST1 and MST2, to turn on transistor MST3. Before the voltage VOUT is charged to

2

SS DD V V −

, VSW will be reversed again, and turn off MST3.

CHAPTER 3

Simulation result and discussion

3.1 Chip layout

The chip of our design is fabricated by the UMC 0.5um +/-20V2P2M high voltage process. To be economical, we only use two layers of metal. The chip dimension is 2210um x 3497um as shown in Fig.3.1, and Fig.3.2 shows its function blocks accordingly.

Figure 3.1 Chip layout view

Figure 3.2 Chip layout view and its according function blocks

OP

^1A

OP

^1B

OP

^1C

BIAS

A_D

OP

^2A

OP

^2B

VC

^A

VC

^B

OP

^VREF

3.2 Pre-Simulation result and Monte Carlo analysis

(1) Buffered amplifier VSS

Original function pin of TDA7496L

VSS VSS IN L ER L VOL ER R NC IN R VREF VDD OUT VSS NC

VSS VSS VSS OUT L VDD VDD OUT R VSS MUTE STBY BIAS VIN1 VIN2 NC

PIN1

PIN14 PIN15 PIN28

Added test pin

Frequency Response of buffered amplifier

VDD=10V VDD=18V Gain 108 dB 113dB

PM 96° 99°

FF

0℃ GB 0.63 MHz 0.99MHz

Gain 103dB 109dB

PM 87° 91°

TT

30℃ GB 0.63MHz 0.74MHz

Gain 101dB 108dB

PM 84° 77°

SS

70℃ GB 0.45 MHz 0.54MHz

With RL=8Ω, CL=30pF Table 3-1. The frequency response pre-simulation result of buffered amplifier

Figure 3.3 Pin Connection after packaging

<Monte Carlo Analysis>

<Monte Carlo Analysis>

在文檔中 有效控制靜態耗電流之高功率高線性度AB類音頻放大器 (頁 32-0)