Chapter 3 Fabrication and Measurement Instruments
3.2 Semiconductor Fabrication Process
3.1 Introduction
The interdigitated electrode micro-plasma device will be demonstrated in this chapter. The embodiment including the fabrication processes, technologies and instruments which are available to develop the structure of interdigitated electrode micro-plasma device will be described in the following sections. First, the semiconductor process including wet bench, furnace, spin coating, exposure, develop, sputter, lift-off and evaporate will be used. Besides, the features of the fabricated device were measured by typical semiconductor measurement systems, such as optical microscope, atomic force microscope (AFM), scanning electron microscope (SEM). In addition, the performance, such as ignition voltage, voltage margin and glow images were characterized in a specific vacuum system including charge-couple device (CCD) camera and pulse DC controller. The mentioned instruments mentioned above will be illustrated in this chapter.
3.2 Semiconductor Fabrication Process
The detail fabrication processes are listed below and the flow chart is shown in Fig. 3.1.
Metal Deposition
Barrier Rib Formation Substrate Cleaning
Silicon Oxide Growth
UV Exposure
Lift-Off
Dielectric Layer Deposition
Fabricated Device
Fig. 3.1. The flow chart of fabrication process for micro-plasma device (a) substrate cleaning (b) silicon oxide growth (c) metal deposition (d) dielectric layer deposition (e) barrier rib formation.
a. Substrate Cleaning:
First of all, silicon wafers were cleaned by RCA clean in wet bench, shown in Fig. 3.2. The RCA clean is the industry standard for removing contaminants from silicon wafer. Werner Kern developed the basic procedure at RCA (Radio Corporation of America) laboratories in 1960’s. As shown in Table 3.1, the main purpose for this procedure is removing organic residue and films from silicon wafers. The decontamination works based on sequential oxidative desorption and complexing with H2O-NH4OH-H2O2 (called “standard clean-1”, SC-1) at 75~85 °C. A second standard clean (SC-2) is often used H2O-HCl-H2O2 at 75~85 °Cto further clean the surface.
SC-1 is used to remove the organic residues from silicon wafer. In the process, it oxidizes the silicon and has a thin oxide on the surface of the wafer which should be removed is a pure silicon surface is desired.
Fig. 3.2. The photograph of Wet Bench for silicon cleaning.
Table 3.1 The RCA clean procedure.
RCA Clean Steps
1. DI water rinse, 5 min
2. H2SO4 : H2O2 = 3:1 Organic Clean
3. DI water rinse, 5 min
4. HF : H2O = 1:100 Chemical oxide Strip
5. DI water rinse, 5 min
6. NH4OH : H2O2 : H2O = 1:4:20 (SC-1), 10 min (75~85 °C) Particle Clean 7. DI water rinse, 5 min
8. HCl : H2O2 : H2O = 1:1:6 (SC-2), 10 min (75~85 °C) Ionic Clean 9. DI water rinse, 5 min
10. HF : H2O = 1:100 Chemical oxide Strip
11. DI water rinse, 5 min
12. Spinner Dry wafers
b. Silicon Oxide Growth:
Because silicon wafer is a semiconductor, the electrode formed on the surface will influence the discharge properties without a buffer layer. In order to avoid discharge between electrode and silicon wafer, a quite thick silicon oxide (about 1 µm) was grown on the surface as a buffer layer. The buffer layer was grown at 1100 °C using both thermal wet and dry oxide by Furnace, shown in Fig. 3.3.
Fig. 3.3. The photograph of Furnace for thermal oxide.
Table 3.2 The growth of 1 µm silicon oxide for Si (100).
Thermal Oxide Growth (1100 °C)
Wet oxide 135 minutes
Dry oxide 20 minutes
c. Metal Deposition:
After growing a buffer oxide on the silicon wafer, the electrode was fabricated on the buffer oxide. Firstly, the HMDS is sprayed to increase the adhesion between substrate and photoresist. In the procedure, the positive photoresist (FH-6400) was spin coated on the surface of substrate and then was exposed UV light by Mask Aligner (MJB-3, Karl-Suss), shown in Fig. 3.4. Consequently, the pattern on the mask
was transformed to positive photoreisit after developing. The pattern was used to define the geometric feature of electrode layer. The width of the gap between each electrode and electrode are 20 µm and 15 µm, respectively. The metal electrode, chromium (Cr), was evaporated on the substrate with patterned photoresist by E-Gun Evaporation System and then the electrode layer was formed by lift-off technology.
Fig. 3.4. The photograph of Mask Aligner for photolithography.
Table 3.3 The lithography procedure for patterning the electrode.
Lithography Steps
1. Spray HMDS In a vacuum oven (150 °C)
2. Spin Coating Photoresit (FH-6400) 1st Spin Speed: 1000 rmp, 10 sec.
2nd Spin Speed: 3500 rmp, 40 sec.
3. Soft Bake 90 sec. at 90 °C
4. Exposure 40 sec.
5. Development 20~30 sec.
6. After Develop inspection (ADI)
7. Hard Bake 150 sec. at 120 °C
d. Dielectric Layer Deposition:
In order to make plasma by bipolar voltage waveform, the dielectric layer should be deposited on the electrode. The HfO2 pellet which is the source material of dielectric layer was evaporated by E-Gun Evaporation System, shown in Fig. 3.5.
Before evaporating dielectric layer, the electrode pad was shadowed by the vacuum type.
Fig. 3.5. The photograph of E-Gun Evaporator System.
e. Barrier Rib Formation:
After depositing the dielectric layer (HfO2), the thick photoresist (XP SU-8 3050) was spin coated on the dielectric layer. Finally, the geometric pattern was realized by the lithographic techniques. The detail parameters are shown in Table 3.1. In the procedure, the thick photoresist (XP SU-8 3050) was spin coated on the dielectric layer. The first spin speed was 750 rmp for 25 seconds until the thick photoresist (XP SU-8 3050) reaches the edge of the substrate. The second spin speed was 3000 rmp for 40 seconds to obtain the desired thickness, referring to the attached spin speed curve in Fig. 3.6. Soft bake the coated substrate in two steps. Firstly increase the temperature from room temperature up to 65°C. Let the substrates at 65 °C for 1 min and then increase up to 90 °C for 15 min. After cooling gradually to the room temperature, the substrate was exposed by UV light for 25 seconds. Consequently, the
pattern on the mask was transformed to the thick photoresit (XP SU-8 3050) after post exposure bake (PEB). The time of post exposure bake (PEB) is 1.5 minutes at 65 °C and then 90 °C for 6 minutes. Developing 8 minutes in SU-8 Developer and rinse with Isopropanol (IPA). Once there is not any white traces the development is then finished. With temperature of 175 °C for 15 minutes, the hard bake was implemented before drying the wafer at the ambient air on a wet bench.
0
Fig. 3.6. XP SU8-3050 spin speed curve.
Table 3.4 The parameters of XP SU-8 3050 photoresist.
Product Spin Speed (rpm) Soft Bake Time Exposure Time