• 沒有找到結果。

Design of PEG-Based Structured LDPC Codes

4.4 Simulation Results and Comparison

In this section, we study the performance of codes constructed by the proposed algo-rithm and give some comparisons. Randomly generated data with binary phase-shift key-ing (BPSK) mappkey-ing are simulated through a zero-mean additive white Gaussian noise (AWGN) channel. First, we construct codes by the proposed algorithm, with parameters specified in Table 3.1, and compare the code performance with those constructed by pre-viously mentioned PEG-QC algorithm. Except for the (3,27)-regular LDPC code, all the other codes constructed by the proposed algorithm are in approximate lower triangular form. Moreover, we choose the codes with girth 6 for simulation except for the (3,27)-regular LDPC code based on PEG-QC algorithm. This is because that it doesn’t report codes with girth larger than 4 even then it has constructed more than 10000 codes.

The performance comparison of (4608, 4096) and (2560, 2240) LDPC codes are given in Fig. 4.5 and Fig. 4.6, respectively, with maximum 80 iterations. As these two figures show, our codes have performance not worse than that of the codes constructed by PEG-QC algorithm. In Fig. 4.7, the 2560-bit rate 1/2 code constructed by the proposed ALT-CP-PEG algorithm shows much better performance. Lower bit error rate (BER) and packet error rate (PER) are perceived as compared to PEG-QC LDPC codes. Fig.

4.8 consists of three codes, all of them are of length 2560 and rate 3/4. As the figure shows, our codes outperform PEG-QC LDPC codes, especially a PER improvement of

one order in magnitude in high-SNR region. Moreover, we compare the ALT-CP-PEG LDPC code with EMD criterion to that without EMD criterion. The former has lower error floor, which is lower than BER of 10−7, and it shows better performance than the latter in high-SNR region. This confirms that the EMD criterion is also suitable for our algorithms.

To further compare the performance of above-mentioned ALT-CP-PEG LDPC codes, the following figures are presented. Fig. 4.9 ∼ 4.11 focus on the convergence rate of iterative decoding, and codes with various maximum numbers of iteration are simulated.

Comparing performance under 80 iterations to those under 10 iterations, we can see that the high-code-rate code (rate = 7/8) converges faster than the code with lower code-rate (rate = 1/2). Moreover, because our codes contain at most one 1 in each column of submatrix Hi,j, we can use layered decoding algorithm referred in Section 2.3.4 to speed up the convergence rate. Fig. 4.12 and Fig. 4.13 show that they can achieve performance similar to a traditional log-BP decoder, but only half of the iterations are required.

To trade off the complexity with error-correcting performance, we can use the min-sum algorithm introduced in Section 2.3.3 instead of log-BP to decode LDPC codes. Fig.

4.14 shows that min-sum algorithm introduces about 0.7 dB SNR loss at BER = 10−5 when both decoders perform 15 decoding iterations. However, we can compensate the loss by modified min-sum algorithm. The result is also shown in Fig. 4.14, where β is the normalization factor as referred in equation (2.57). Fig. 4.15 shows the same trend but less performance loss compared to Fig. 4.14. In Fig. 4.16, we can see that the performance by using modified min-sum algorithm outperforms that by using log-BP under BER = 10−6. This may result from cycles in the corresponding Tanner graph of this LDPC code. Log-BP algorithm is not an optimum solution for an cyclic graph, so the modified min-sum algorithm may perform better.

At the end of this section, we compare performance of codes constructed based on the proposed method to that of the irregular LDPC code adopted in IEEE 802.16e. Here, these two codes have the same degree distribution pair and the same submatrices size.

Both codes have length as 2304 and rate as 1/2, and their parity check matrices are both in ALT form. Girth of the code constructed by our algorithm is 8, however, that of the code in IEEE 802.16e is 6. As shown in Fig. 4.17, we can see that our code slightly

outperforms the IEEE 802.16e LDPC code. Moreover, because of the ALT form, our code remains encoding complexity similar to that of IEEE 802.16e.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

10-6 10-5 10-4 10-3 10-2 10-1 100

Eb/N 0 (dB)

Error rate

80 iterations

BER(4608,4096) PEG-QC, girth = 4 BER(4608,4096) CP-PEG, girth = 6 PER(4608,4096) PEG-QC, girth = 4 PER(4608,4096) CP-PEG, girth = 6

Figure 4.5: Performance comparison of the regular codes with rate 8/9 constructed by the proposed and PEG-QC algorithms

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

Figure 4.6: Performance comparison of the irregular codes with rate 7/8 constructed by the proposed and PEG-QC algorithms

0 0.5 1 1.5 2 2.5

Figure 4.7: Performance comparison of the irregular codes with rate 1/2 constructed by the proposed and PEG-QC algorithms

0 0.5 1 1.5 2 2.5 3 3.5

Figure 4.8: Performance comparison of the irregular codes with rate 3/4 constructed by the proposed and PEG-QC algorithms

0 0.5 1 1.5 2 2.5

Figure 4.9: Iterative decoding with various maximum number of iteration for (2560, 1280) ALT-CP-PEG LDPC code with rate 1/2

0 0.5 1 1.5 2 2.5 3 3.5

Figure 4.10: Iterative decoding with various maximum number of iteration for (2560, 1920) ALT-CP-PEG LDPC code with rate 3/4

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

Figure 4.11: Iterative decoding with various maximum number of iteration for (2560, 2240) ALT-CP-PEG LDPC code with rate 7/8

0 0.5 1 1.5 2 2.5

Figure 4.12: Performance of (2560, 1280) ALT-CP-PEG LDPC code with rate 1/2 by using layered decoding algorithm

Figure 4.13: Performance of (2560, 1920) ALT-CP-PEG LDPC code with rate 3/4 by using layered decoding algorithm

0 0.5 1 1.5 2 2.5

Modified minsum, Beta=0.75, 15 iterations Minsum, 15 iterations

Figure 4.14: Performance of (2560, 1280) ALT-CP-PEG LDPC code with rate 1/2 by using min-sum and modified min-sum algorithms

0 0.5 1 1.5 2 2.5 3 3.5

Modified minsum, Beta=0.75, 10 iterations MinSum, 10 iterations

Figure 4.15: Performance of (2560, 1920) ALT-CP-PEG LDPC code with rate 3/4 by using min-sum and modified min-sum algorithms

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

Modified minsum, Beta=0.75, 10 iterations MinSum, 10 iterations

Figure 4.16: Performance of (2560, 2240) ALT-CP-PEG LDPC code with rate 7/8 by using min-sum and modified min-sum algorithms

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

BER of proposed (2304,1152), girth = 8 BER of IEEE 802.16e (2304,1152), girth = 6 PER of proposed (2304,1152), girth = 8 PER of IEEE 802.16e (2304,1152), girth = 6

Figure 4.17: Performance comparison of the irregular codes with rate 1/2 constructed by the proposed algorithm and of IEEE 802.16e

Chapter 5 Conclusion

In this thesis, we propose a general method, called CP-PEG algorithm, to construct hardware-oriented LDPC codes for reducing VLSI design complexity. As compared to other algebraic methods, our algorithm is practical due to code parameters such as rate, block length, and degree distribution more flexible. In order to reduce encoding com-plexity, the parity check matrices in ALT form are also presented. Moreover, we can combine EMD criterion into CP-PEG or ALT-CP-PEG algorithm to enhance the error floor performance. With our approach, the resulting LDPC codes don’t suffer error floor even though at BER = 10−7.

Simulation results confirm that proposed algorithms are much better than traditional PEG-QC algorithm in terms of BER or PER. Comparing with the LDPC code adopted in IEEE 802.16e standard, our code performance outperforms that of IEEE 802.16e LDPC codes. Finally, for the convergence rate consideration, our structured codes are much suitable for layered decoding algorithm which can provide around two times faster de-coding convergence. Because of the abovementioned advantages, the proposed CP-PEG algorithm can be a good candidate for designing practical LDPC codes.

Bibliography

[1] R. G. Gallager, Low-Density Parity-Check Codes. Cambridge, MA: MIT Press, 1963.

[2] V. Zyablov and M. Pinsker, “Estimation of the error-correction complexity of Gal-lager low-density codes,” Probl. Pered. Inform., vol. 11, pp. 23–26, Jan. 1975.

[3] G. A. Margulis, “Explicit construction of graphs without short cycles and low density codes,” Combinatorica, vol. 2, no. 1, pp. 71–78, 1982.

[4] R. M. Tanner, “A recursive approach to low complexity codes,” IEEE Trans. Inf.

Theory, vol. IT-27, no. 5, pp. 533–547, Sep. 1981.

[5] M. Sipser and D. A. Spielman, “Expander codes,” IEEE Trans. Inform. Theory, vol. 42, pp. 1710–1722, Nov. 1996.

[6] D. J. C. MacKay and R. M. Neal, “Near Shannon limit performance of low density parity check codes,” Electron. Lett., vol. 32, pp. 1645–1646, Aug. 1996.

[7] D. J. C. MacKay, “Good error correcting codes based on very sparse matrices,” IEEE Trans. Inf. Theory, vol. 45, no. 2, pp. 399–431, Mar. 1999.

[8] S.-Y. Chung, J. G. D. Forney, T. Richardson, and R. Urbanke, “On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit,” IEEE Commun.

Lett., vol. 5, no. 2, pp. 58–60, Feb. 2001.

[9] X.-Y. Hu, E. Eleftheriou, and D.-M. Arnold, “Progressive edge-growth Tanner graphs,” in Proc. IEEE Global Telecommunications Conf. (GLOBECOM), San An-tonio, TX, Nov. 2001, pp. 995–1001.

[10] ——, “Regular and irregular progressive edge-growth Tanner graphs,” IEEE Trans.

Inf. Theory, vol. 51, no. 1, pp. 386–398, Jan. 2005.

[11] Air interface for fixed and mobile broadband wireless access systems, IEEE Std.

P802.16e/D12 Draft, Oct. 2005.

[12] IEEE 802.11n Wireless LANsWWiSE Proposal: High Throughput extension to the 802.11 Standard, IEEE Std. 11-04-0886-00-000n.

[13] Z. Li and B. V. K. V. Kumar, “A class of good quasi-cyclic low-density parity check codes based on progressive edge growth graph,” in Proc. 38th Asilomar Conf. Signals, Syst. Comput., 2004, pp. 1990–1994.

[14] M. C. Davey and D. J. C. MacKay, “Low density parity check codes over GF (q),”

IEEE Commun. Lett., vol. 2, pp. 165–167, June 1998.

[15] L. Ping, W. K. Leung, and N. Phamdo, “Low density parity check codes with semi-random parity check matrix,” Electron. Lett., vol. 35, no. 1, pp. 38–39, Jan. 1999.

[16] T. Richardson and R. Urbanke, “Efficient encoding of low-density parity-check codes,” IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 638–656, Feb. 2001.

[17] F. R. Kschischang, B. J. Frey, and H.-A. Loeliger, “Factor graphs and the sum-product algorithm,” IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 498–519, Feb. 2001.

[18] J. F. Fan, Constrained Coding and Soft Iterative Decoding. Kluwer Academic Pub-lishers, 2001.

[19] Y. C. Liao, C. C. Lin, C. W. Liu, and H. C. Chang, “A dynamic normalization technique for decoding LDPC codes,” in IEEE Workshop Signal Processing Syst., Nov. 2005, pp. 768–772.

[20] A. J. Blanksby and C. J. Howland, “A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder,” IEEE Journal of Solid-State Circuits, vol. 37, no. 3, pp.

404–412, Mar. 2002.

[21] E. Yeo, P. Pakzad, B. Nikolic, and V. Anantharam, “VLSI architectures for iterative decoders in magnetic recording channels,” IEEE Trans. on Magnetics, vol. 37, no. 2, pp. 748–755, Mar. 2001.

[22] M. M. Mansour and N. R. Shanbhag, “High-throughput LDPC decoders,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 6, pp. 976–996, Dec. 2003.

[23] D. E. Hocevar, “A reduced complexity decoder architecture via layered decoding of LDPC codes,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS’04), Oct. 2004, pp. 107–112.

[24] T. Richardson, A. Shokrollahi, and R. Urbanke, “Design of capacity-approaching irregular low-density parity-check codes,” IEEE Trans. Inf. Theory, vol. 47, pp. 619–

637, Feb. 2001.

[25] J. Xu, L. Chen, I. Djurdjevic, S. Lin, and K. Abdel-Ghaffar, “Construction of regular and irregular LDPC codes: Geometry decomposition and masking,” IEEE Trans. Inf.

Theory, vol. 53, no. 1, pp. 121–134, Jan. 2007.

[26] S.-Y. Chung, T. J. Richardson, and R. Urbanke, “Analysis of sum-product decoding of low-density parity-check codes using a Gaussian approximation,” IEEE Trans. Inf.

Theory, vol. 47, no. 2, pp. 657–670, Feb. 2001.

[27] Y. Mao and A. H. Banihashemi, “A heuristic search for good low-density parity-check codes at short block lengths,” in Proc. IEEE Int. Conf. Commun., Helsinki, Finland, June 2001.

[28] T. Tian, C. Jones, J. D. Villasenor, and R. D. Wesel, “Construction of irregular LDPC codes with low error floors,” in Proc. IEEE Int. Conf. Communications, May 2003, pp. 3125–3129.

[29] C. Di, D. Proietti, E. Telatar, T. J. Richardson, and R. Urbanke, “Finite-length analysis of low-density parity-check codes on the binary erasure channel,” IEEE Trans. Inf. Theory, vol. 48, no. 6, pp. 1570–1579, June 2002.

[30] H. Zhong and T. Zhang, “Block-LDPC: A practical LDPC coding system design approach,” IEEE Trans. Circuits Syst. I, vol. 52, no. 4, pp. 766–775, Apr. 2005.

[31] H. Xiao and A. H. Banihashemi, “Improved progressive-edge-growth (PEG) construc-tion of irregular LDPC codes,” IEEE Commun. Lett., vol. 8, no. 12, pp. 715–717, Dec. 2004.

[32] S. H. Kim, J. S. Kim, D. S. Kim, and H. Y. Song, “LDPC code construction with low error floor based on the IPEG algorithm,” IEEE Commun. Lett., vol. 11, no. 7, pp. 607–609, July 2007.

作者簡歷

姓名:林義凱

出生地:台灣省高雄市

出生日期:1983 年 10 月 5 日

學歷: 1989.9 ~ 1995.6 高雄縣立林園國民小學 1995.9 ~ 1998.6 高雄縣立林園國民中學 1998.9 ~ 2001.6 高雄市立小港高級中學

2001.9 ~ 2005.6 國立中央大學 電機工程學系 學士

2005.9 ~ 2007.11 國立交通大學 電子研究所 系統組 碩士

相關文件