CHAPTER 3 OUTPUT BUFFERS FOR DATA
3.6 Simulation Results
3.6.2 Simulation Results of Low-Offset-Voltage
The circuit schematic of low-offset-voltage class-B buffer with chopper techniques is as shown in Fig.3.10. The input offset voltage 2.7mV is externally added, and the period of the two clocks, ph1 and ph2, are set equally twice the input signal. Since in time domain, the output voltage is input voltage plus offset voltage in first period, and input voltage minus offset voltage in second period, and so on as shown in Fig.3.23 and Fig.3.24, Fig.3.25 and Fig.3.26. This is an ac signal in frequency domain, which can be filtered out by the inherent low-pass filter characteristic of liquid crystals. When input signal equals 4.2V, the first output voltage is equal to 4.1957V and the second output voltage is equal to 4.2011V; the average voltage is equal to 4.1984V which is within ± mV output voltage deviation. 2 When input signal equals 0.2V, the result is similar, and the average voltage is equal to 200.975mV.
Fig.3.23 Transient response of first 4.2V, Vout = 4.1957V.
Fig.3.24 Transient response of second 4.2V, Vout = 4.2011V.
Fig.3.25 Transient response of first 0.2V, Vout = 197.9 mV.
Fig.3.26 Transient response of second 0.2V, Vout = 204.05 mV.
CHAPTER 4
DIGITAL TO ANALOG CONVERTER AND CHARGE RECYCLING FOR
DATA DRIVER
4.1 Gamma Correction
The Gamma Correction is needed because of the color sensitivity of human eye is not linear. If we apply a linear voltage to control the gray levels of a LCD panel, the human eye would consider it non-linear. Thus, the digital to analog converter (DAC) used in TFT-LCD data driver is necessary to be implemented with a modified T-V curve (Transparency-to-Voltage curve), which is so called “Gamma Correction”.
Fig.4.1 shows an example of T-V curve and we can find the T-V curve is symmetrical to transparency axis [6]. The reason is the same as inversion driving method that is discussed in section 2.2.1, where a LCD panel should be driven by AC signals.
4.2 Digital to Analog Converter
There are several general types of digital to analog converter (DAC), which are voltage scaling DAC, charge scaling DAC, timing scaling DAC, and current scaling DAC. For TFT-LCD data driver, current scaling architecture wastes too much power and will not be discussed here. In this chapter, the three other types of DAC architecture will be discussed.
Fig.4.1 Transparency-to-voltage curve withγ -correction [6].
4.2.1 Voltage Scaling DAC
The theory of voltage scaling DAC is by using a resistor ladder, a given reference voltage (Vref) can be divided into N segments. Fig.4.2 and Fig.4.3 illustrate two fundamental voltage scaling DAC architectures. The properties of the two architectures are compared below.
Common properties:
Simple and monotonic Large chip size at higher bits.
Good DNL and poor INL.
Lower noise.
Optimized Gamma Correction.
Vref+
Fig.4.3 Voltage scaling DAC (2).
Different properties:
Architecture in Fig.4.2 uses an n-to-2n decoder, where architecture in Fig.4.3 uses binary code.
Delay time of architecture in Fig.4.2 is 2n ×C×Ron, where in Fig.4.3 is
×2
×
×R C
N on .
In TFT-LCD driver circuit design, there are hundreds of output voltage buffers in a single chip. If we want to display the same display data in all outputs, their voltage reference must be the same or there will be gray level differences. Also, for gamma correction, voltage scaling DAC is the easiest way to implement different segments.
For higher bits applications, decoders in Fig.4.2 would be too huge to implement for TFT-LCD layout. For TFT-LCD applications, its layout width must be within 60µm.
Chip area and operational speed of architecture in Fig.4.3 is similar to Fig.4.2, but its width can be implemented in 60µm. Thus, in this thesis, voltage scaling DAC in Fig.4.3 is decided.
4.2.2 Charge Scaling DAC
As voltage scaling DAC, a reference charge can be divided into N equal packets by using N identical capacitors. A conventional charge scaling DAC is illustrated in Fig.4.4. In this circuit, it has two steps. The capacitors storage the reference voltage first, and then transfer the charge to output capacitor. By this operation, the output voltage can be determined by the following equation:
−
Vref
Fig.4.4 Charge-Redistribution DAC.
VM
Fig.4.5 Two-step charge scaling DAC.
As we can see from Fig.4.4, this circuit has a big disadvantage, large size at higher bits. Therefore, an alternative architecture called two-step charge scaling DAC which can solve this problem is illustrated in Fig.4.5. The operation method of this circuit is similar as conventional DAC. Take 8-bit DAC as an example, the output voltage of this circuit can be also determined by (4-2):
)
DAC out
Fig.4.6 C-2C charge scaling DAC.
Besides these two circuits, there is another type of architecture that can reduce more chip size, called C-2C DAC which is shown in Fig.4.6. In summary, all of them have some advantages better than voltage scaling DAC. First, the matching for capacitor is better than resistor ladder. Second, the charge scaling can save more power. But they have several problems in TFT-LCD applications. First, the reference voltage of all output voltage buffers cannot be implemented identically by using charge scaling DACs. Second, all of them are very difficult to achieve gamma correction. From the above discussions, charge scaling DACs are not applied in this thesis.
4.2.3 Time Scaling DAC
In Fig.4.7, a diagram about the concept of time scaling DAC is illustrated. In this architecture, a ramp source that can be distributed to many parallel DAC, and this ramp source drives several DAC simultaneously. As the ramp increases, the data line is slowly charged by the ramp. When the voltage of the data line reach the desired voltage, the data line is disconnected from the ramp source by the DAC, and the data
line holds the proper voltage. At the beginning of the next conversion, the ramp source is reset and repeats the same process. The DAC is just like a switch that controls the time of connection between ramp source and data line. Therefore, the different voltage can be controlled by the different connection time.
As discussed above, the major advantage of this architecture is consistency across all parallel data line, but it also has a major disadvantage, speed. First, the loading of ramp source is very large. Second, if the pixel resolution is too high, the slope of the ramp would be much sharper. Therefore, this architecture isn’t suitable for high resolution and large size TFT-LCD applications.
DAC DAC DAC
t1 t2 t3
t2 t1 t3
V2 V3
V2
V1
V3
Fig.4.7 The concept of time scaling DAC.
4.3 Low Power Design Consideration
The power dissipation for an electronic system has four sources:
Dynamic power is the result of charging capacitances in the circuit such as wires and transistor gates. It is governed by the following equation[16]:
2 1
0
fCV
P
dyn= α
→(4-3)
where α0→1 is the fraction of clock periods in which component switches from a logical zero to one.
Short circuit power is the result of resistive paths from power to ground while circuits are transitioning.
Static power is the result of resistive paths from power to ground when circuits are not transitioning.
Leakage power is the result of reverse bias between diffusion regions and substrate.
In this thesis, dynamic power is focused. To reduce dynamic power, charge recycling method is applied.
4.3.1 Half Charge Recycling
Fig.5.1 and Fig.5.2 illustrate a circuit and simulation waveform of the half charge recycling. In dot or column inversion, the voltages of the neighboring data lines are alternated every row line time to inverse polarity. Therefore, the adjacent data lines are shorted together before the gray scales decision. Adjacent data lines share their charges and their voltage would become the average voltage of all data lines. Thus, the voltage swing is reduced to the half of that of the conventional data driver, and driver circuits could save about 1/2 power consumption.
CR
Conventional Data Driver
Panel Fig.4.8 The circuit diagram of the half charge recycling.
Fig.4.9 Waveform of the half charge recycling and its current consumption.
4.3.2 Triple Charge Recycling
Fig.5.3 shows a circuit of the triple charge sharing. In this circuit, and external large capacitor is needed, CEXT >> N×CL, where N is the number of the data lines.
The input signal is shown in Fig.5.4, and its operation of the triple charge sharing is shown in Fig.5.5. First, the external capacitor is supposed to have been charged to VL+(1/3)VSWING. During the first charge sharing, SEL1 is high, the even-numbered are shorted to CEXT and charged to VL+(1/3)VSWING. And then all the output data lines would share the charge and change the voltage to VL+(2/3)VSWING. Finally, the odd-number data lines are shorted to external capacitor and the voltage of data line would discharge to VL+(1/3)VSWING. Meanwhile, the odd-numbered data lines would recover the charge of external capacitor. After charge sharing, the data driver drives the data line. Then the voltage swing is reduced to the third of that of the conventional data driver, thus driver circuits can save 2/3 power consumption.
SEL1 SEL2 SEL3 AMP
C
EXTConventional Data Driver
Panel
Fig.4.10 The circuit diagram of the triple charge recycling.
Fig.4.11 Waveform of the triple charge recycling and its current consumption.
Fig.4.12 Input waveform of the triple charge recycling.
CHAPTER 5
CIRCUIT LAYOUT AND MEASUREMENT RESULTS
5.1 Layout Considerations
The circuits for data driver that was discussed in previous sections, the output buffer, the output buffer with chopper cancellation, voltage scaling DAC, charge recycling are designed and layout. All of these circuits have been designed as testkey.
The purpose of designing testkey is to measure the separate performance and see whether it works. By modifying and refine these circuits, whole data driver can be composed. All circuits are fabricated in a TSMC 0.35µm CMOS technology.
Fig.6.1 shows the layout of input differential amplifier. Here we use dummy, guard ring, and layout symmetrically to reduce input offset voltage. Fig.6.2 shows the layout of feedback capacitor, which is symmetric with dummy. Fig.6.3 shows the whole voltage buffer, where its width must be within 60µm since we have 384 output pins on a single driver IC. Fig.6.4 shows the layout of 10-bit DAC, where its width is also less than 60µm although its height is quite long. The layout of whole chip is shown in Fig.6.5. Since all the circuits are implemented on a single chip, power supply pads and ground pads of all circuits are separated to avoid crosstalk. Fig.6.6 illustrates the layout floorplain.
Fig.5.1 Layout of input differential amplifier.
Fig.5.2 Layout of feedback capacitor.
Fig.5.3 (Left figure) Layout of whole voltage buffer.
Fig.5.4 (Right figure) Layout of 10-bit voltage scaling DAC.
Fig.5.5 Layout of whole chip and pad names.
Buffer
Buffer with
chopper No charge recycling
DACwith buffer recyclingHalf
Triple recycling
Decoupling capacitors
Fig.5.6 Layout floorplain.
5.2 Measurement Results
Fig.5.7 Chip die photo.
Fig.5.7 shows the die photo of this implemented IC. There are six major parts of this chip, which are Class-B buffer, Class-B buffer with chopper techniques, Two buffers without charge recycling, 10-bit digital to analog converter, Half charge recycling and Triple charge recycling. All above circuits are measured on different PCBs, and measurement environments are carefully set up. Fig.5.8 shows several measurement PCB boards.
Two Buffers without Recycling (Front) 10-bit DAC (Front)
Two Buffers without Recycling (Back) 10-bit DAC (Back)
Triple Charge Recycling (Front) Triple Charge Recycling (Back)
Fig.5.8 Several measurement PCB boards.
5.2.1 Class-B Buffer
Some DC values of measured class-B buffer are listed in Table. III. Since the input range of the class-B buffer is from 0.2V to 4.2V, some values of the unity-gain buffer is measured. As we can see, the voltage differences between input and output are about 3mV to 5mV.
Vin (V) Vout (V) Vin-Vout Vin (V) Vout (V) Vin-Vout
4.2006 4.1952 5.4mV 2.0873 2.0774 3.9mV
4.0227 4.0177 5.0mV 1.8854 1.8820 3.4mV
3.8567 3.8516 5.1mV 1.7121 1.7086 3.5mV
3.5448 3.5398 5.0mV 1.5383 1.5353 3.0mV
3.1227 3.1180 4.7mV 1.3693 1.3660 3.3mV
3.0605 3.0560 4.5mV 0.9950 0.9910 4.0mV
2.5791 2.5749 4.2mV 0.4684 0.4646 3.8mV
2.2760 2.2712 4.8mV 0.2001 0.1959 4.2mV
Table. III. DC voltage values of measured class-B buffer.
Vcc Current Vcc Current
6.0V 35.5µA 4.6V 9.3µA
5.6V 23.3µA 4.35V 7.0µA
5.3V 17.5µA 4.0V 3.4µA
5.0V 13.4µA 3.5V 2.0µA
Table. IV. Current consumption of measured class-B buffer.
The static current consumption of this buffer is about 35µA, which is way too high comparing to simulation results. Also, the current consumption drops too quickly as the Vcc drops. To explain this, let us see the corner simulation results of this proposed buffer plus the measurement result graph, as shown in Fig.5.9.
Fig.5.9 Simulation results of current consumptions of SS, TT, FF corners and measured current.
By checking the simulation DC data, when the process corner goes to fast-fast, the class-B buffer becomes class-A buffer, which means the output stage MOS transistors do not turn off and consume huge current about 74µA . The plotted measured current shows that this chip process drops between typical-typical and fast-fast.
The condition of testing transient response of this buffer is shown in Fig.5.10, and the measurement results are shown in Fig.5.11. As we can see, the transient response of this buffer is quick enough to charge the loading.
Fig.5.10 Measurement condition of measuring transient response.
Fig.5.11 Measurement results of transient response.
5.2.2 Class-B Buffer with Chopper Techniques
The test condition of measuring class-B with chopper is similar as class-B buffer, but adding chopping signals. The measurement results are shown in Fig.5.12, Fig.5.13 and Fig.5.14. By adjusting the oscilloscope scale to very small, we can see that the Vos is added one time and subtracted next time. By this chopping operation, the liquid crystal sees the average voltage of two input voltage values and the Vos could be cancelled. Notice that the chopping clock is disturbed as the Vout changes since it is created from Vout by D-type flip flops.
Fig.5.12 Transient response: chopping clock and Vout of class-B buffer with chopper.
Fig.5.13 Three adjacent Vout waveforms.
Fig.5.14 Another three adjacent Vout waveforms.
5.2.3 Two buffers without charge recycling
This circuit is only measured in order to compare with the other charge recycling circuits. The output waveform of this circuit is shown in Fig.5.15.
Fig.5.15 Two buffers without charge recycling.
While trying to measure its current consumption, an interesting data that listed in Table. V is observed. As we can see, if input frequency equals 33kHz and input swing equals 4V, the current consumption is strangely inverse proportional to Vdd:
Vdd=4.7V I=472µA Vdd=5.3V I=117µA
Vdd=4.9V I=509µA Vdd=5.6V I=113µA
Vdd=5.0V I=237µA Vdd=6.0V I=130µA
Table. V. Current consumption of two buffers while |Vin|=4V.
In order to find out why this happens, several measurements are made and results are shown in Table. VI and Table. VII:
|Vin|=0.05V I=23.0µA |Vin|=0.05V I=47.9µA
(Vin swings between 0.2V and 4.2V)
Table VI. Current consumption of two buffers as input swing varies at different supply voltages.
Vdd=5.0V Vin1=0.2V, Vin2=4.2V I=14.3 µA Vdd=6.0V Vin1=0.2V, Vin2=4.2V I=60.1 µA
Table VII. Current consumption of two buffers as input frequency equals zero.
From the above data, we can tell that the current consumption bursts out when supply voltage goes low (less than 5.5V) and input swing goes high (4V), which means the measured current does not follow the current consumption equation,
sCV I
I I
Itotal = static + dynamic = static + (this will be further calculated in 5.2.5). Also,
if input frequency equals zero, this phenomenon would not occur.
In order to find out the explanation, going back to check HSPICE simulation is necessary. As illustrated in Fig.5.16 and Fig.5.17, if Vdd equals 5.0V, the current consumption goes terribly large when input swing goes to 4.0V, while the current consumptions are all normal if Vdd equals 6.0V.
Fig.5.16 Current consumptions of different input swings at Vdd=5.0V.
Fig.5.17 Current consumptions of different input swings at Vdd=6.0V.
Analyzing the input common mode voltage would tell the answer to current consumption, as shown in Fig.5.18. As we can see, the input common mode voltage is limited at Vdd=5.0, i.e., when the input voltage is greater than 3.75V, the Ibias of input stage (Fig.3.6) would decline, eventually cutoff. During transient response, the high input voltage would cause Ibias of input stage to be cutoff. Once it is cutoff, all the rest MOS transistors will be cutoff except output stage MOS transistors. Under this condition, the results are illustrated in Fig.5.19 and Fig.5.20.
At first, the Vout are 0.2V and Vin are 4.2V. The common mode voltage is 2.2V and the circuit is still under normal operation, thus the inverter stage would make output stage MOS transistors on and chase the input voltage level. After a while, as Vout approaches Vin and the input common mode voltage goes greater than 3.75V, all transistors turn off suddenly as the Ibias turns off. Thus, the gate voltages of output stage transistors remain the same, resulting great current consumption during transient response. If Vdd equals 6.0V, input voltage of 4.2V is still in input common mode range, all transistors are under normal operation.
Notice that there is still a small current while Vin equals 4.2V at Vdd=5.0V. This explains why DC values are correct.
Fig.5.18 Current of input stage mirrored current source at Vdd=5.0V and Vdd=6.0V.
Fig.5.19 Current of different stage transistors at Vdd=5.0V.
Fig.5.20 Gate voltages of two output stage MOS transistors.
5.2.4 Half charge recycling
The input signals of half charge recycling are already described earlier in 4.3.1.
The measurement results of half charge recycling are shown in Fig.5.21, and its current consumption is listed in Table. VIII.
Fig.5.21 Waveform of half charge recycling.
Vdd=6.0V I=80µA
Table. VIII Current consumption of half charge recycling at Fvin=33kHz.
5.2.5 Triple charge recycling
Similarly, the input signals of triple charge recycling are discussed in 4.3.2. The output waveform of triple charge recycling is shown in Fig.5.22, and its current consumption is listed in Table. IX.
Fig.5.22 Waveform of triple charge recycling.
Vdd=6.0V I=75.6µA
Table. IX Current consumption of triple charge recycling at Fvin=33kHz.
In order to calculate how much dynamic power that charge recycling saves, we must go back to the data of 5.2.3 and calculate the static power and dynamic power. It follows the equation, Itotal = Istatic + Idynamic = Istatic +sCV :
Two Buffers Without Charge Recycling Vdd=6.0V
Table. X Calculation of dynamic current consumption.
From the above calculation, the dynamic power that half charge recycling saves is about
5.2.6 10-bit Digital to Analog Converter
The measurement results of this digital to analog converter are quite bad. The desired output voltage range is from 0.2V (input code 00000000000) to 4.2V (input code 1111111111), but the measured voltages are from about 0.12605V (input code 0000000000) to about 2.7723V (input code 1111111111). This is caused by improper layout method. As illustrated in Fig.5.23, since the supply voltage is 6V and 0.2V to 4.2V is required, two kinds of resistance materials, N-well and Poly have been used as resister string. This is because the square resistance value of N-well is much larger than that of Poly. But as shown in Fig.5.24, N-well resistance grows larger as the voltage drop across itself becomes larger due to the growth of depletion region. Thus the voltage division is a disaster.
The measurement results of different input code are listed in Table. XI. Although the result is still linearity, due to its wrong output voltage range, calculating DNL, INL is meaningless. Fig.5.25 shows its operating frequency when the input code changes from 0000000000 to 1111111111.
VDD
0.2V 4.2V
2 N-well Resistors
1024 Poly Resistors
Fig.5.23 DAC resistor string.
N+ N+ N+ N+
5V 4.2V 0.2V
P-sub N-Well
N-Well
Depletion Region
Fig.5.24 Resistance of N-well grows larger as the voltage drop across itself becomes larger.
Fig.5.25 Output waveform of DAC when input code changes from 0000000000 to 1111111111.
Input code Vout ∆ V Input Vout ∆ V 0000000000 0.1260V -- 0000010010 0.1719V 2.4mV 0000000001 0.1283V 2.3mV 0000010011 0.1745V 2.6mV 0000000010 0.1310V 2.7mV 0000010100 0.1773V 2.8mV 0000000011 0.1333V 2.3mV 0000010101 0.1798V 2.5mV 0000000100 0.1362V 2.9mV 0000010110 0.1825V 2.7mV 0000000101 0.1388V 2.6mV 0000010111 0.1846V 2.1mV 0000000110 0.1412V 2.4mV 0000011000 0.1874V 2.8mV 0000000111 0.1439V 2.7mV 0000011001 0.1899V 2.5mV 0000001000 0.1466V 2.7mV 0000011010 0.1926V 2.7mV 0000001001 0.1489V 2.3mV 0000011011 0.1953V 2.7mV 0000001010 0.1516V 2.7mV 0000011100 0.1979V 2.6mV 0000001011 0.1540V 2.4mV 0000011101 0.2003V 2.4mV 0000001100 0.1567V 2.7mV 0000011110 0.2030V 2.7mV
0000001101 0.1591V 2.4mV : :
0000001110 0.1617V 2.6mV 0111111111 1.4437V --
0000001111 0.1642V 2.5mV : :
0000010000 0.1668V 2.6mV 1111111110 2.7703V -- 0000010001 0.1695V 2.7mV 1111111111 2.7723V 2.0mV
Table. XI Measured DAC output values at Vdd=6V.
CHAPTER 6
CONCLUSIONS AND FUTURE WORKS
6.1 Conclusions
Scan driver and data driver is necessary in TFT-LCD panel. They are used to process the signals from graphic cards and transfer the signals properly to LCD panel.
Scan driver and data driver is necessary in TFT-LCD panel. They are used to process the signals from graphic cards and transfer the signals properly to LCD panel.