Single-Sampled Gain-Compensated Integrator

F2

V in

V out

F2 F1

F2

F2 Cs

C¢s F1

Cf

F1

F2

V

-C¢f

Figure 3.8: Gain-compensated SC integrator with limit in input [12]

A topology of SC integrator with gain compensation shows in Fig. 3.8 is proposed [12].

The output is valid during phase2, and produce an output during phase1 equal to the output dur-ing phase2. By maintaindur-ing an approximately constant output voltage from phase1 to phase2, V⁻ = −Vout/A remains nearly constant during phase1 and phase2 as desired. The circuit works well under the assumption thatVinis approximately constant. First, we analysis how the circuit work, and discuss the limitation ofVin. Then another topology that used to improve this topol-ogy will be introduced. Finally, make a comparison between of them. The topoltopol-ogy that have effective high gain can be described as follow.

The circuit can be analyzed with three half consecutive phase, form (n-3/2) to (n-1/2).

First, we assume the circuit start atφ2(n-3/2) shown in Fig. 3.9(a). During this phase, the circuit not only integrated the input voltage but also mix the error voltage that due to op-amp finite gain. The charge storage in the capacitorsCs Cf andC_f^′, include the mixed error charge. The mixed error charge that due to the op-amp finite gain is Vout(n − 3/2)/A. Next, the circuit

C¢

Figure 3.9: The SC integrator during (a) phase2 and (b) phase1

switch to φ1(n-1) shown in Fig. 3.9(b). The capacitor C_s^′ = 2Cs are used to cancel the input voltage that dump byC_s at previous phase, also integrated the input voltage to output. There will be a problem here for input voltage limitation, and it will be discussed next. During this phase, the voltage V_in(n − 1) and V_out(n − 3/2)/A was integrated to the capacitor C_f^′, where the second term Vout(n − 3/2)/A was dumped by the capacitor Cs. The capacitor C_f^′ now storage the previous and this moment input voltage and previous gain error. Then the capacitor Cs will storage the voltage Vout(n − 3/2)/A² and Vout(n − 1)/A on it. At third phase, the circuit switch to φ2(n − 1/2), the voltage storage on Cs withVout(n − 1)/A will be canceled byVout(n − 1/2)/A, and only the term of Vout(n − 3/2)/A²preserve. The circuit works like to predict the error voltage and cancel it at next phase. This is how it have effective squared gain.

Here shows the charge conservation at op-amp inverted input.

First, whenφ1 high, and φ2 low, the charge conservation at node V⁻can be described as

− Cs[1 Second, whenφ2 high, and φ1 low, the charge conservation at node V⁻can be described as

− Cs[1

Combining Eq.(3.10) and Eq.(3.11) assuming that 2Cs = C_s^′, and taking the z-transform, the overall transfer function can be expressed

H(z) = Vout(z)

Vin(z) = (1 + _A⁴)z⁻¹² + _A¹z⁻¹

[(1 + _A⁴)(1 + _A¹) + _A¹(1 + _A¹)]z⁻³² − [(1 + _A⁴)(1 + _A²)]z⁻¹² (3.12)

The DC magnitude at z=1 can be expressed

|H(z)|_z=1= 5A + A²

3 (3.13)

To show the disadvantage of ”slow moving” of input show in Fig. 3.8, we first assume ideal switch and ideal op-amp here. The circuit can be analyzed over three consecutive half clock cycles shown in Fig. 3.9. On the last half cycle, phase2,Vinis integrated ontoCf through Csto produceVout(n), and can be expressed as the input must be slow moving, it means that input must be approximately constant.

To solve this disadvantage, another topology have been proposed [13] shown in Fig. 3.10.

Fig.3.11 shows the circuit during φ₁ and φ₂. It is assumed that the discrete time duringφ₁ is (n-1/2) and that duringφ₂it is n. Thus, the discrete times associate with the previousφ₁ andφ₂ are (n-3/2) and (n-1), respectively. The charge conversion equation at nodeV⁻can be described in three half cycle.

Figure 3.10: Gain-compensated SC integrator with no limitation for input signal [13]

Cs

Figure 3.11: The SC integrator during phase (a)φ1and (b)φ2

First, whenφ2, high, and φ1, low, the conversion at node V⁻can be described as

− C_s[V_in(n − 3

Second, whenφ1, high, and φ2, low, the conversion at node V⁻can be described as

− C_f[Vout(n − ³₂)

Combining Eq.(3.16) and Eq.(3.17), and assuming the op-amp DC gain≫ 1 [15], the charge conservation equation of theV⁻becomes

Vout(n − 1

Taking the z-transform of Eq.(3.18), and assumingC_s^′ = C_s, the approximated overall transfer function can be obtained as

H(z) = − 1 − (_A¹ +_AC^Cs

Where the gain error is 2/A and the pole error is2/A², the gain is enhanced significantly when compare to the DC gain of A for simple integrator as shown in Fig. 2.7. From analysis the

difference of them, we can find out the key point to design a SC integrator that insensitive to the finite gain of op-amp is the Cs. When Cs always connect at the inverted input of op-amp, the voltage of −Vout/A will be sampled at the Cs during both phase. Then the term of Vout(n − 1/2)(Cs/A) and Vout(n − 3/2)(Cs/A) will be canceled as shown in Eq.(3.18). It is the reason why have effective finite gain, because only the term 1/A² will keep. The offset of the op-amp can also canceled byCs. The another advantage of Fig. 3.10 is the use of capacitor C_s^′. The circuit useC_s^′ to sample the input first, and then compensate the voltage that dumped byC_sat previous phase. It makes the disadvantage of ”slow moving” will not happen.

Here we use an ideal op-amp to construct the single-sampled integrator shown in Fig. 3.10.

In order to test the function of the topology, a 10kHz sinusoidal signal with amplitude of 1mv is applied to the topology. The sampling frequency is 10MHz, and the gain of the amplifier is 40dB. Then the output magnitude and phase of an ideal inverting integrator is given by

|H(z)|ideal = | −1

The output magnitude and phase of the integrator with no compensation shown in Fig. 3.1(b) is given by

|H(z)|no compensation = | −A

(2 + A) − (1 + A)z⁻¹| ≈ 84.3

6 H(z)|no compensation ≈ 147.65^◦

(3.22)

Where A is the op-amp finite gain. The output magnitude and the phase of the integrator with gain compensation that paper proposed shown in Fig. 3.10 is given by

|H(z)|paper = | − 1 − _A²

1 − (1 − _A²2)z⁻¹| ≈ 155.9

6 H(z)|paper ≈ 92^◦

(3.23)

From Eq.(3.21) and Eq.(3.23), can find the SC integrator with gain compensation is very close to ideal ones. The DC magnitude is effectively toA²/2, and makes the op-amp more easier to design without high op-amp gain. The finite gain of op-amp not only reduce the magnitude of output signal but also cause a phase error. The simulation results shown in Fig. 3.13 and Fig. 3.14 are the output signal of the SC integrators for conventional ones with no compensation and paper proposed. The simulation results shown in Fig. 3.15 is an SC integrator with no compensation but constructed of a 80dB op-amp. The output voltage for a high gain op-amp will be more approximately to an ideal SC integrator. The frequency response of the op-amp with finite gain 40dB was shown in Fig. 3.12.

Figure 3.12: The frequency response of the macro model op-amp with 40dB magnitude

Figure 3.13: The output voltage of the SC integrator with no gain compensation,fin = 10kHz with amplitude 1mv,fs = 10MHz, and A=40dB

Figure 3.14: The output voltage of the SC integrator with gain compensation, fin = 10kHz with amplitude 1mv,fs = 10MHz, and A=40dB

Figure 3.15: The output voltage of the SC integrator with no gain compensation,fin = 10kHz with amplitude 1mv,fs = 10MHz, and A=80dB

The gain-compensated technology that we discussed above are single-sampled topology.

It sampled the gain error during one half phase, then compensated it during next half phase.

The another one was constructed with a double-sampled technology, which integrated the input voltage during both two half phase, but only one half phase has the gain compensation. Next, we will show a double-sampled gain-compensated SC integrator and find the trade off between both of them. Finally, we design a circuit which is the modification of the paper proposed, and make a comparison of them.