Sub-retinal prosthesis

As long ago as 1956, Tassiker in Australia described in a patent a retinal prosthesis that consisted of a light-sensitive selenium cell placed behind the retina of a blind patient [41]; this transiently restored the patient’s ability to perceive light. In the ensuing period, however, greater successes were reported with cortical implants [42], although spatial resolution and the fading of excitation were still unresolved problems. These techniques have subsequently been taken to their most sophisticated form by Normann who has developed an intracortical array comprising 100 individual“needle＂electrodes [43].

By the early 1990s the efforts of many research teams finally came to concentrate on the retina. In particular, more sophisticated developments in the field of microelectronics and the successful use of the cochlear implant to replace lost auditory function suggested that the possible development of a functional retinal implant was within reach. After these early prototypes had been developed and implanted, experimental animal work was performed to define the electrical stimulation parameters for the retina. In this context the capacity of the human eye to adapt to large brightness and contrast variances plays a decisive role.

Before thoughts could turn to a corresponding series of experiments in humans, the appropriate surgical techniques for the reliable insertion and attachment of these implants first had to be developed. As a rule this work was performed in animal models because these are apparently suitable for answering the specific questions raised in this context. In addition, it was of crucial importance first to establish which patients appeared best suited to receive prosthesis of this type.

Currently, the research conducted by teams in Germany, the USA and Japan into epi-retinal and sub-retinal implants has reached the stage where clinical trials can now be

performed with the devices that have been developed.

The fundamental concept of the Sub-retinal approach is that electrical charge generated by the micro-photodiode array (MPA) in response to a light stimulus may be used to artificially alter the membrane potential of neurons in the remaining retinal layers in a manner to produce formed images [44]. The MPA functions in solar cell mode, that is, it operates without power supply. Fig. 1.4 shows the sub-retinal implant [45]. This approach would theoretically allow the remaining intact retinal circuits of the inner retina to process this signal in a near-normal fashion and transmit this signal to the brain. In addition, the sampling density of a sub-retinal device could be designed to match that of the remaining photoreceptor or bipolar cell matrix, thereby providing a potentially high-resolution input to the retina.

Although the current sub-retinal implants have less circuit complexity, they suffer from the problem that the pn junction diode in solar cell mode cannot provide enough photovoltaic power supply to the retinal chip. Therefore, it is important to improve the efficiency of the pn junction diode in solar cell mode in sub-retinal implants.

1.3 REVIEW ON POWER SUPPLY ISSUE IN ARTIFICIAL RETINA PROSTHESES It is medically infeasible to have permanent wired connections pass through the eyeball wall because the wire would do quick damage to the eyes. Laying the wires and connecting the nodes entails extensive incisions, a potentially hazardous surgery. Therefore, the power issue is a great challenge for implanted retinal circuit.

Owing to lower stimulus level, sub-retinal chip usually consists of photodiode and electrode array which provides stimulus of low energy [46]. Thus sub-retinal chip requires no power supply. However, this kind of artificial retinal prosthesis can only replace the photoreceptor, a cell converting light into electrical signal. If more than the damage of photoreceptor causes blindness, the typical sub-retinal chip cannot restore the vision.

A common way to provide the implanted retinal circuit power is utilization of RF telemetry [2], [40]. This kind of implanted device consists of an extraocular and intraocular unit. The implantable component receiver power and a data signal via a telemetric inductive link between the two units. The extraocular unit includes a video camera and video processing board, a telemetry protocol encoder chip, and an RF amplifier and primary coil. The intraocular unit consists of a secondary coil, a rectifier and regulator, a retinal chip with a telemetry protocol decoder, a stimulus signal generator, and an electrode array. The major difficulty for this telemetry technique is tissue heating associated with electromagnetic power deposition in the tissues and power dissipation in the microchip collectively.

The proposed method to supply power to implanted retinal chip is using solar cells.

When the circuit is designed as low-power circuit, solar cells can provides enough energy to the implanted circuit. Two advantages of solar cell are described below. Firstly, when there is no light and therefore human cannot see and the solar cells supply no power to the implanted

circuit. It clearly reduces some power dissipation and tissue heating. Secondly, solar cell is compatible with intraocular unit. Therefore, there is no equipments need to carry with the blind.

Figure. 1.1 The Human Eye. Reprinted from “Foundations of Physiological Psychology,” by Neil R. Carlson, 1988, p.134.

Figure. 1.2 A Conceptual Epi-Retinal Prosthetic System. Reprinted form “A Neuro-Stimulus Chip with Telemetry Unit for Retinal Prosthetic Device,” by Wentai Liu, and etc, 2000.

Figure. 1.3. The Typically Functional Implantable Epi-Retinal Microsystem. Reptinted from

“A Neuro-Stimulus Chip with Telemetry Unit for Retinal Prosthesis Device” by Wentai Liu, and etc., 2000.

Figure. 1.4. The Sub-Retinal Implant. Reprinted from the internet:

“http://www.optobionics.com/theeye.htm” by Mike Zang.

1.4 MOTIVATIONS

1.4.1 Solar cell structure.

In modern CMOS imager design, the silicon-based phototransduction has been studied in several different aspects. We will show the relation between layout structure and phototransduction efficiency in this section. One of the important sensors for digital imaging is PN junction photodiode because it is easy to fabricate in CMOS technology, which is inexpensive and widely available. When the light irradiates a diode’s junction, electron-hole pairs are generated due to the light illumination. Inside the depletion region, Electrons and holes generated will be swept into the adjacent N and P regions, respectively, due to the electric field across the junction. In addition, electrons and holes generated in the adjacent P and N regions may diffuse into the depletion region and be swept into the other side.

Photogenerated carriers swept into the across junction layer may be detected either as photocurrent or as photovoltage. The photodiode can be operated in two basic modes:

photoconductive mode and photovoltaic mode. The equivalent circuit for both modes of operation is shown in Fig. N, where Iph represents photocurrent, D0 is a diode, Rs is the series resistance, Rj is the load resistance, and V is the reverse bias voltage. If the incident light power is Pph, the photocurrent Iph corresponding to the current source in Fig. 1.5 is

ph ph

I q Pη

= ω

where η is the quantum efficiency if the photodiode and ω is the angular frequency of the incident light. In short-circuit photoconductive mode, the voltage across the photodiode is zero and the external current is Iph. The photoconductive mode is also known as photo-sensing mode which is widely applied in CMOS imager design. In photovoltaic mode, the carriers swept through the depletion layer build up a potential across the PN junction. The photovoltaic mode is also known as solar cell power supply mode which is widely used in on-chip solar power supply system. In this work, we will use these two different modes to build up a CMOS imager and retina stimulator with on-chip solar power supply system. [48]

There are several different layout methodologies of the CMOS photodiode. The N+/P-substrate photodiode, which is shown in Fig .1.6, is the most popular layout structure in APS (active pixel sensor) imager design. But the photodiode structure above can’t be applied in solar cell power supply system because the p-substrate in CMOS circuit must be connected to ground. Thus the N+/P-substrate structure can only provide negative voltage level and the p-substrate can’t be connected as the VDD of the CMOS circuit because the NMOS in the circuit will operate under high body voltage condition that the Vt (threshold voltage) will increase. In order to provide a positive voltage level to the circuit, the P+/N-well photodiode structure is proposed as shown in Fig. 1.7. The solar cell with this structure can provide the positive voltage level as an on-chip power supply.

There are two solar cells connected in series to provide the voltage power supply in the

beginning of the solar cell power supply design. The retinal chip is powered by on-chip solar cell which can be measured individually. The measurement environment is shown in Fig. 1.8.

The measurement result is shown in Fig. 1.9. The characteristic I-V curve of the solar cells, which are connected in series, has a strange curve within 0V to 1V voltage-sweep range. In compassion with ideal curve, the measured curve seems to be a compound of ideal solar cell I-V curve and ideal solar BJT I-V curve. The top view and cross-section view of the solar cell supply system is shown in Fig. 1.10. We suppose there is a parasitic BJT in the solar cell power supply system as shown in Fig. 1.11. Due to the p-substrate is connected to ground; the junction between n-well and p-substrate is under reverse bias and the junction between p+ and n-well is foreword bias. Therefore the parasitic BJT is turn on and the I-V curve of the solar cell supply system is change to the I-V curve of the photo-BJT (parasitic BJT). With this parasitic structure, we create a new simulation model of the solar cell supply system as shown in Fig. 1.12. This model is based on experimental results of the solar cell supply system. The simulation result of the new solar cell supply system is shown in upper box of the Fig. 1.14.

The comparison between the simulation result and the measurement result can verify the cause of the strange I-V curve of the solar cell supply system.

In addition, if there is only one solar cell to provide the on-chip power supply, the problem we face above still has in the parasitic effect. On the measuring of another testkey with same p+/n-well diode structure, the connection condition of p-substrate has tremendous influence on the efficiency of the solar cell. The testkey with same p+/n-well diode structure is surrounded by the n-well guard-ring and p-substrate guard-ring. The top view layout of this testkey is shown in Fig. 1.14. The measurement results of the single solar cell testkey above are shown in Fig. 1.15. Four different lines represent the different connection of the n-well and p-substrate individually. NW:O: the n-well is connected to VDD; NW:X: the n-well is floating. Psub:O: the p-substrate is connected to ground; Psub:X: the p-substrate is floating.

As we can see in this figure, the connection of the n-well has strongly effect on the efficiency of the solar cell, but has no influence on the Voc of the solar cell, which is very important for a power supply. In another hand, the connection of the p-substrate has a great influence on both efficiency and Voc of the solar cell. First, the red dashed line and black solid line have shown the same characteristic which measured in above solar cell supply system. Therefore the problem of the p-substrate connection, which happened in solar cells connected in series, still can be found in this single solar cell testkey. The connection effect of the n-well is not usually seen but the p-substrate connection problem will happen in any NMOS in normal CMOS design. As a result, we propose several layout methodologies in next Chapter to prevent the problem of parasitic BJT.

Iph D0 Rj

Rs

Cj Rl

Rl

V

Photovoltaic mode

Photoconductive mode

Figure 1.5. Equivalent circuit for a photodiode. Iph represents photocurrent, D0 is a diode, Rs is the series resistance, Rj is the load resistance, and V is the reverse bias voltage.

Figure 1.6 .the cross-section view of the n-well/p-substrate photodiode which is widely used in CMOS imager design.

Figure 1.7. the solar cell power supply system with two solar cells in series which can provide sufficient positive voltage supply.

Figure 1.8. the measurement environment of the solar cell testkey and solar cell powr supply system. The right box is the probe station with four recording channel.

Figure 1.9. the measurement results of the solar cell power supply which has two solar cells connected in series. The curve light2 is under 400lux illumination, curve light3 is under 1000lux illumination, and light4 is under 1500lux illumination.

HP 4145B / HP 4156B

Tektronic TDS 3054

Figure 1.10. the top view and cross-section view of the solar cell power supply system. .

Figure 1.11. the parasitic BJT of the solar cell supply system. The leakage current through the BTJ result in the strange I-V curve we measured.

Figure 1.12. new simulation model of the solar cell supply system with parasitic BJT. both parasitic BJT and solar cell have phototransduction current. This model is based on experimental resluts of the solar cell supply system.

Figure 1.13. the comparsion between the simulation results and experimental results. Upper box: the simulation result of the new solar cell supply system. Lower box: the experimental results of the solar cell supply system.

from photodiode from photoBJT

P+ guardring (connected to p-substrate) N-well guardring

Solar cell

Figure 1.14. the top view of the layout of the single solar cell test key.

Figure 1.15. the measurement results of the single solar cell test key. Four different lines represent the different connection of the n-well and p-substrate individually. NW:O: the n-well is connected to VDD; NW:X: the n-well is floating. Psub:O: the p-substrate is connected to ground; Psub:X: the p-substrate is floating. As we can see in this figure, the connection of the n-well has strongly effect on the efficiency of the solar cell, but has no influence on the Voc of the solar cell, which is very important for a power supply. in another hand, the connection of the p-substrate has a great influence on both efficiency and Voc of the solar cell. Therefore the problem of the p-substrate connection, which happened in solar cells connected in series, still can be found in this single solar cell testkey^.

1.4.2 Power issue

In CMOS solar cell power supply design, the photovoltaic efficiency is limited to the chip fabrication foundry and the total supplied power is in proportional to the layout area of the solar cells. Therefore the power supply design of the retinal chip is mainly focus on the power saving policy.

Persistence of vision is the phenomenon of the eye by which even nanoseconds of exposure to an image result in milliseconds of reaction (sight) from the retina to the opitic nerves. This is because persistence of vision depends on chemical transmission of nerve responses, and this biochemical hysteresis is much slower than the light transmission. A typical explanation of persistence of vision went something like this: when the human eye is presented with a rapid succession of slightly different images, there is a brief period during which each image, after its disappearance, persists upon the retina, allowing that image to blend smoothly with the next image. [47] Therefore the retinal chip needs not to stimulate the retinal cell continuously but stimulate the retinal cell with a more discrete method. As we know that the maximum frame rate which can be distinguished by human is about 60Hz, namely, we can stimulate the retinal cell every 16ms or less and the retina still consider the discrete stiulus as a continuous stimulus.

By applying the technique of divisional power supply architecture to exploit the characteristic mentioned above, an three times output current could be achieved. The details are in the followings. We divide the pixel array into four blocks whole outputs are controlled by four control signals generated by power control unit. The blocks will be activated in turn to send out their stimulating signals. The time interval between neighboring activation of the same block must be much smaller than biochemical hysteresis of the cell. Only one of the blocks is activated at the same time and the power from whole chip, which is supplied by solar cells, is provide to that block to increase the output stimulating current. In contrast to the conventional MPA design, the output power is much greater and the discrete stimulus won’t cause any misinterpret in the retina but still provide continuous signals to the brain.

1.5 MAIN RESULTS

In this thesis, a retinal chip has been designed, analyzed, and fabricated to improve the power efficiency of the sub-retinal prostheses. The feasibility of on-chip solar cell supply system which integrated with circuit system in CMOS technology has been verified in the work. According to the experiment data, the preliminary in vitro experiment of the silicon retina chip which composed of micro photodiode array has been designed and verified.

According to the experiment data, the silicon retina with MPA can successfully trigger the retina cell and the electrical-response is similar to the light-response in retina cell. A three times output stimulating current is achieved by taking advantage of the bio-inspired divisional power supply architecture. The stimulating output current is approximately 844nA under the illumination of 3.6mW/cm² light intensity and 1.72μA under the illumination of 5.06mW/cm² light intensity. The retinal chip fabricated with a standard 0.18μm tsmc CMOS process demonstrate good mimic of electrical behavior of human retina with low-power consumption.

CHAPTER 2 Solar Cell Design in CMOS Technology

2.1 THE NOVEL STRUCTURE OF SOLAR CELL

The new layout methodologies for the solar cell supply system are proposed in this section to solve the problem we faced in above section. We propose three different layout methodologies for the new solar cell supply system. First, we found that some of the solar cells in previous testkey can still have proper characteristic as a power supply. In comparison with other solar cells and other on-chip solar cell power supply system, the distance between p-substrate pick-up and solar cell seems to be a key factor to this problem. The p+/n-well solar cell can maintain the same characteristic while the distance between p-substrate pick-up and solar cell is greater than 50μm. Therefore, we can use same p+/n-well diode structure to build up an on-chip solar cell supply system. But in order to maintain the characteristic of the solar cells, the required layout area is increasing dramatically due to the distance between p-substrate pick-up and solar cells. We propose other solar cell structures to provide the solar cell power supply. In order to keep the p-substrate floating to prevent the leakage problem in p+/n-well solar cell, we use deep-n-well to isolate the solar cells or NMOS in the circuit as shown in Fig. 2.1. One of the layout structures is shown in top block of Fig. 2.1: the NMOS is

The new layout methodologies for the solar cell supply system are proposed in this section to solve the problem we faced in above section. We propose three different layout methodologies for the new solar cell supply system. First, we found that some of the solar cells in previous testkey can still have proper characteristic as a power supply. In comparison with other solar cells and other on-chip solar cell power supply system, the distance between p-substrate pick-up and solar cell seems to be a key factor to this problem. The p+/n-well solar cell can maintain the same characteristic while the distance between p-substrate pick-up and solar cell is greater than 50μm. Therefore, we can use same p+/n-well diode structure to build up an on-chip solar cell supply system. But in order to maintain the characteristic of the solar cells, the required layout area is increasing dramatically due to the distance between p-substrate pick-up and solar cells. We propose other solar cell structures to provide the solar cell power supply. In order to keep the p-substrate floating to prevent the leakage problem in p+/n-well solar cell, we use deep-n-well to isolate the solar cells or NMOS in the circuit as shown in Fig. 2.1. One of the layout structures is shown in top block of Fig. 2.1: the NMOS is