Summary

2.4 Summary

The channel current density of AlGaN/GaN HEMTs can be modulated by applying uniaxial tensile strain and it depends on the gate orientation. Additionally, tensile strain severely degrades current recovery. This could be attributed to the additional donor-like surface states induced by the additional piezoelectric polarization that the tensile strain produces.

Figure 2-1(a). Top view of the test die and gate orientations under uniaxial stress along [11-20] and [10-10], and (b) schematic configurations of the three-point bending test fixture for the tensile stress.

Figure 2-2. ID-VD curves of the device without the uniaxial tensile strain.

J₀

Figure 2-3. Transconductance characteristic of the device without the uniaxial tensile strain.

Figure 2-4. Three-terminal breakdown performance of the device without the uniaxial tensile strain. The breakdown down voltage is defined by drain leakage current up to 1mA/mm.

Figure 2-5. Normalized IDSS of the devices with gates oriented [10-10] and [11-20]

directions, and theoretical charge density shift as a function of mechanical uniaxial strain.

Figure 2-6. Normalized transconductance shift of the devices with gates oriented [10-10] and [11-20] directions as a function of mechanical uniaxial strain.

0.0 1.0x10^-4 2.0x10^-4 3.0x10^-4 4.0x10^-4

Normalized Idss and theoretical charge density shift (%)

[10-10]

Figure 2-7. Transient characteristics (VGS = Vpinch-off to 0V, 1V/step) of unpassivated AlGaN/GaN HEMTs under the strain of zero and 1.47



10^-4 in comparison with the DC characteristics.

Figure 2-8. Current recovery of the unpassivated AlGaN/GaN HEMTs as a function of mechanical uniaxial strain, measured at the bias point of VGS = Vpinch-off and VDS = 0 V.

0 2 4 6 8 10

0 200 400 600

800 DC without stress Pulsed IV without stress Pulsed IV with stress

I

DS

( m A /m m )

V

DS

(V)

DC with Stress

0.0 1.0x10^-4 2.0x10^-4 3.0x10^-4 4.0x10^-4 60

70 80 90 100

[10-10]

[11-20]

C u rr e n t re c o v e ry ( % )

Mechanical uniaxial strain

Bias Point : (Vds, Vgs) = ( 0V, -6V )

0.0 1.0x10^-4 2.0x10^-4 3.0x10^-4 4.0x10^-4 10

20 30 40 50

Mechanical uniaxial strain

Bias Point : (Vds, Vgs) = ( 20V, -6V )

Current recovery (%)

[11-20]

[10-10]

Figure 2-9. Current recovery of the unpassivated AlGaN/GaN HEMTs as a function of mechanical uniaxial strain, measured at the bias point of VGS = Vpinch-off and VDS = 20 V.

Figure 2-10. Cross-section of the HEMT device with a sequence of SiNx passivation, including the first 100nm-thick SiNx layer and the second 550nm-thick SiNx layer.

Figure 2-11. Omega-2Theta scan by high-resolution x-ray diffraction with an accuracy of ±7 arcsec.

Figure 2-12. Transient characteristics(V_GS = V_pinch-off to 0V, 1V/step) of the device before and after second layer passivation, , measured at the bias point of VGS = V pinch-off and V_DS = 0 V.

34.1 34.2 34.3 34.4 34.5 34.6 34.7 34.8 Before passivation

After 2 layers passivation

Intensity

2Theta ( degree )

34.5

15 arcsec

Figure 2-13. Transient characteristics (VGS = Vpinch-off to 0V, 1V/step) of the device before and after second layer passivation, , measured at the bias point of VGS = V pinch-off and VDS = 20 V.

Figure 2-14. Transient current as a function of transient time measured from the bias point of VGS = Vpinch-off and VDS = 0 V to the bias point of VGS = 0V and VDS = 8 V. After second SiNx passivation

Transient Current ( mA/mm )

Time (-sec )

Bias piont: (Vd, Vg) = ( 0V, -5V) ( 0V, 8V)

Figure 2-15. Transient current as a function of transient time measured from the bias point of VGS = Vpinch-off and VDS = 20 V to the bias point of VGS = 0V and VDS = 8 V.

1 10 100 1000

540 560 580 600 620 640 660 680

Bias piont: (Vd, Vg) = ( 20V, -5V) ( 0V, 8V)

Before second SiNx passivation After second SiNx passivation

Transient Current ( mA/mm )

Time

(

-sec

)

Chapter 3

30 GHz Low Noise Performance of 100nm-Gate-Recessed n-GaN/AlGaN/GaN HEMTs

3.1 Introduction

The power performance of gate-recessed AlGaN/GaN HEMTs at 30 GHz has been reported and the results demonstrate that they are suitable for high-frequency and high-power applications [3-1]. For low noise performance, GaN-based HEMTs can achieve a minimum noise figure (NF_min) of less than 2 dB over the frequency of 10–20 GHz [3-2, 3-3, 3-4, 3-5]. These results were achieved without a recessed gate and short channel effects were observed when the gate length was scaled down to the deep-submicrometer range. In this chapter, a heavily Si-doped GaN cap layer and a recessed gate were proposed to demonstrate the potential of GaN-based HEMTs for low noise applications up to 30 GHz.

3.2 Device Fabrication

The AlGaN/GaN heterostructure was grown on a 3-inch (0001) sapphire substrate using metal-organic chemical vapor deposition (MOCVD). The epitaxial structure consisted of a nucleation layer, a 2-μm-thick GaN buffer layer, a 25-nm-thick Al0.25GaN0.75N barrier layer, and a 5-nm-thick Si-doped (3 × 10¹⁸ cm⁻³ ) GaN cap layer, as illustrated in Figure 3-1. The heavily Si-doped cap layer was proposed to reduce contact resistance [3-6]. Figure 3-2 shows the band diagram of the proposed structure, where Ec level is still higher than femi level as a Schottky gate contacting with n-GaN layer. Schottky barrier height here is assumed to be 1.1eV [3-7]. It suggests that the heavily Si-doped cap layer would not result in a leaky gate to degrade the device low noise performance.

The HEMT device fabrication started with ohmic-contact formation.

Ti/Al/Ni/Au metal stacks (20/120/25/100 nm) were evaporated as ohmic metals and subsequently annealed at 800C for 60 s in ambient N2. An ohmic-contact resistance of 0.28 ·mm was obtained using the TLM method. Mesa isolation was formed

utilizing inductively coupled plasma etcher with Cl2-based gas. For the T-shaped gate process, it was defined in the center of the 7 μm drain-source spacing by a 50 kV JEOL electron beam lithography system (JBX 6000 FS) with trilayer e-beam resist.

The e-beam resist was also used as a mask for recess etching afterward. Before Ni/Au (20 nm/300 nm) gate metal deposition, gate recess was performed using inductively coupled plasma etcher with BCl₃ gas. The recess etching rate was controlled at 0.05nm per second. In this work, approximately 12 nm recess depth was etched to enhance the aspect ratio to around 5.5. Finally, gate metal was lifted off by acetone and dimethylacetamide (ZDMAC) to form a 100-nm T-shaped recessed gate. The gate width of the device in this work was 2 × 50 μm.

3.3 Device Characterization

The DC performance of the device was measured by Agilent E52702B. As shown in Figure 3-3, the drain current characteristics of the device with a 100 nm recessed gate exhibit a good pinch-off behavior, which is due to the enhanced aspect ratio by the gate recess technique. The off-state breakdown voltage is 90 V, as defined by the drain leakage current up to 1 mA/mm. Figure 3-4 shows the gate leakage current (I_G) during the device operation. It can be seen that the gate leakage current is lower than 2μA/mm at each bias point. Such a low leakage current might be attributed to the extremely low recess etching rate which helps reduce the damage caused during the dry etching process. After recessing, more than one order reduction in the reverse leakage current was observed using a Schottky diode, as shown in Figure 3-5. This finding was in agreement with that of Okamoto et al. [3-8]. They suggested that the reduction of leakage current after recessing is due to the suppression of the tunnelling component of the gate leakage current by slight removal of the surface n-type AlGaN.

However, the mechanism is not understood clearly and needs further study. The pulsed ID-VD is shown in Figure 3-6, where the bias point is (VDS, VGS) = (0V, Vpinchoff). Comparing with DC ID-VD curve, it indicates that not much damage was induced due to the recess dry etching.

The S parameters of the fabricated device were measured using an on-wafer probing system with an Agilent E8361A network analyzer. The standard LRRM calibration method was adopted to calibrate the measurement system with reference planes set at the tips of the probes. Figure 3-7 shows the frequency dependence of the

current gain H21 and Mason‟s unilateral gain U of the device measured at VDS = 10 V and VGS = −3 V. The parasitic effects (mainly capacitive) due to the probing pads have been carefully removed from the measured S parameters using the same method as in [3-9] and the equivalent circuit model in [3-10]. The unity current gain cutoff frequency (F_T) and the maximum frequency of oscillation (F_MAX) were extrapolated as 48 GHz and 75 GHz respectively using −20dB/decade regression.

High-frequency noise properties at room temperature were measured over the frequency range of 18–40 GHz using an Auriga noise measurement system with a Agilent 8975A noise figure analyzer. Figure 3-8 plots the 30GHz minimum noise figure (NFmin) as a function of gate bias at VDS = 10V. The lowest noise figure of around 1.5dB can be obtained at gate bias of –3V. Figure 3-9 plots the minimum noise figure and the associated gain (Gass) as a function of frequency at the bias point of VGS = −3V and VDS = 10V, where the lowest noise figure was achieved. A NFmin

value of 1.2 dB (1.6 dB) with Gass = 6.5dB (5dB) at 20 GHz (30 GHz) was observed.

Such a low noise performance could be attributed to the low contact resistance of 0.28

·mm, source resistance of 2.5 extracted from S parameters, and also the low gate leakage current of 0.9 µA/mm during the device operation. To the best of our knowledge, this 30 GHz noise performance is the best reported so far for GaN-based HEMTs with a recessed gate. Another important figure of merit used to characterize the performance of a broadband low-noise amplifier is the equivalent noise resistance Rn normalized to the optimal noise matching impedance |Z_opt| (|R_n/Z_opt|)[3-11]. The fabricated device exhibited 0.47 (0.57) of |R_n/Z_opt| at 20Ghz (40GHz) and an average value of 0.53 from 20 GHz to 40 GHz, indicating an excellent potential for broadband low-noise amplifier applications.

3.4 Summary

A minimum noise figure of 1.6 dB was obtained at 30 GHz, which could be attributed to the low gate leakage current as well as the low contact resistance due to the use of a heavily Si-doped GaN cap layer. Furthermore, an average value of 0.53 for |Rn/Zopt| from 20 GHz to 40 GHz was obtained.

Figure 3-1. Cross section of 100nm-gate-recessed n-GaN/AlGaN/GaN HEMT.

Figure 3-2. Band diagram for n-GaN/AlGaN/GaN with a Schottky contact.

0 200 400 600 800

-3,5 -3,0 -2,5 -2,0 -1,5 -1,0 -0,5 0,0 0,5 1,0 1,5 2,0 2,5 3,0 3,5

E_V EF

AlGaN

Relatively Energy (eV)

Thickness from surface

n-GaN GaN

EC

Figure 3-3. DC forward characteristics of 100nm-gate-recessed n-GaN/AlGaN/GaN HEMT.

Figure 3-4. Gate leakage current density during the device operation.

0 2 4 6 8 10

Figure 3-5. Reverse I-V characteristics of non-recessed and recessed Schottky diode.

Figure 3-6. Pulsed ID-VD compared with DC forward ID-VD of the proposed device, which was measured at the bias point of (V_DS, V_GS) = (0V, Vpinchoff).

0 5 10 15 20 25 30

5x10^-8 5x10^-7 5x10^-6 5x10^-5

Recess

Normalized Current

(

A/cm2

)

Bias (V)

Non-recess

0 2 4 6 8 10

0 50 100 150 200 250 300 350 400 450 500

550 Pulsed I-V

I DS (mA/mm)

VDS (V) Vg = 0 ~ 4V, -1V/step

DC

Figure 3-7. Intrinsic S-parameter performance of the device at bias point of VGS = -3V, VDS = 10V.

Figure 3-8. NFmin against gate bias at VDS = 10V, and 30GHz.

-4 -3 -2 -1 0

1.0 1.5 2.0 2.5 3.0 3.5 4.0

NF m in ( d B )

Gate Bias (V)

Frequency = 30GHz

1 10 100

0 5 10 15 20 25 30 35

|H₂₁|² U

Gain (dB)

Frequency (GHz)

( Bias Point: V_GS = -3V, V_DS = 10V )

F_T = 48GHz F_MAX = 75 GHz

Figure 3-9. Frequency dependence minimum low noise figure (NFmin) and associated gain of the device at bias point VGS = -3V, VDS = 10V.

15 20 25 30 35 40 1.0

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0

NF_min NF (dB)min

Frequency (GHz)

Associated Gain

Associated Gain (dB)

Chapter 4

Normally-off Operation AlGaN/GaN MOS-HEMT with High Threshold Voltage

4.1 Introduction

In this Chapter, Fluorine-based treatment technique was used in combination with an Al2O3 film as gate oxide layer to demonstrate normally-off operation AlGaN/GaN MOS-HEMTs with high threshold voltage, of which the current density was comparable with conventional normally-on HEMTs.

4.2 Device Fabrication

An AlGaN/GaN heterojunction was grown on a 2-inch c-plane sapphire substrate using metal-organic chemical vapor deposition (MOCVD). The epitaxial structure consisted of a nucleation layer, a 2-μm-thick GaN buffer layer, a 1-nm-thick AlN interlayer, and a 13-nm-thick Al0.25Ga0.75N barrier layer. The room-temperature Hall mobility and sheet electron concentration of the sample were 1900 cm²/Vs and 8.8



10¹² cm^-2, respectively.

Fabrication of the MOS-HEMTs started with ohmic-contact formation with 7 μm drain-source spacing. Ti/Al/Ni/Au metal stacks (20/120/25/100 nm) were evaporated as ohmic metals and subsequently annealed in N₂ ambient at 800C for 1 min. Mesa isolation was formed utilizing inductively coupled plasma (ICP) etcher with Cl2-based gas. A 100-nm-thick SiNx layer was deposited using plasma-enhanced chemical vapor deposition (PECVD) and then was patterned by lithography with 1-μm-width etching window in the center of the 7 μm drain-source gap. Before removal of the photo-resist, the SiNx was etched by reactive-ion etcher (RIE) with CF₄/O₂ gas mixture, and then the device was treated with CF₄ plasma, of which the condition was similar with that reported in [4-1]. Afterward, a 16-nm-thick Al₂O₃ oxide layer was deposited using atomic-layer deposition (ALD) and the devices were subsequently annealed at 400 C for 10 min in N2 ambient. The thermal annealing was not only for damage recovery [4-2] but also for post oxide-deposition annealing. Before gate

metallization, electrode pads were patterned by lithography and the oxide layer was removed by wet etching with HF solution. Finally, a 3-μm-length gate was evaporated with Ni/Au (20/300 nm) to cover the F ion treatment region, as illustrated in Figure 1.

The gate width of the devices in this work was 2 × 50 μm.

4.2 Device Characterization

DC performances of the devices were measured by Agilent E5270B. Figure 2 compares IG-VGS characteristics of normally-off operation HEMTs using F-based treatment technique with and without Al2O3 layer. In reverse and forward performances, the MOS-HEMT appeared lower gate leakage current than that of HEMT without oxide layer. The gate of the conventional device started to turn on at VGS = 2 V, as defined by 1 mA/mm leakage current; however, the 16-nm-thick Al2O3

layer prevented the other device from not only Schottky gate leakage but also tunnelling leakage current up to VGS = 12.7 V. Figure 3 compares IDS-VGS

characteristics of the devices with and without oxide layer. Although the conventional device performed higher drain current and higher peak transconductance at VGS = 5 V and 2.5 V, respectively, such performances suffered from huge gate forward leakage current which can be seen in Figure 2. On the contrary, the MOS device showed a peak transconductance of 100 mS/mm, and a drain current of approximately 500 mA/mm while the gate still maintained off at 11 V. This was higher than the drain current of 250 mA/mm obtained at V_GS turn-on voltage (V_on=2 V) from the device without oxide layer. Additionally, the threshold voltage was increased from 0.7 V to 5.1 V due to the insertion of Al₂O₃ gate oxide layer. Fig. 4-4 shows the benchmark of maximum drain-source saturation current (I_DSS) and V_th for the reported E-mode GaN-based HFETs. A high Vth of 5.1 V with high current density of 500 mA/mm were demonstrated in this work.

Pulsed IDS-VDS measurements were performed at bias points of VDS=10V and VGS=0V, as shown in Fig. 4-5. In order to reveal dispersion effects of the surface trap, we plotted DC ID-VD curve in the same figure as a reference. When gate was biased at 5 V with grounded drain voltage, pulsed IDS-VDS exhibited higher current density than DC one. About 50% increment of current density than that of DC measurement at VGS= 10 V, which implied some charging effects would happen during DC measurement. At bias point VGS= 0 V and VDS= 10 V, the current density was even

higher, with a drain current density of 750 mA/mm. Both pulsed IDS-VDS curves showed no dispersion effect due to surface traps, no current degradation, which could be attributed to SiNx passivation and Al₂O₃ gate insulator.

Fig. 4-6 shows the frequency response of F-based MOS-HEMT. The F_T and the F_MAX were 4.74 GHz and 12.24 GHz, respectively, when the device was biased at V_GS = 7 V and V_DS = 10 V. Compared with the device without gate insulator as shown in Fig. 4-7, the F_T of MIS-HEMT was almost the same, while the F_MAX of the MOS device exhibited better small-signal response. Better frequency response could be due to lower gate leakage current under bias point, which could be found in Fig. 4-2.

According to above results, Al2O3/AlGaN/GaN MOS-HEMTs demonstrated the potential of RF electronics, and the RF response could be improved by scaling down gate length along with smaller source-drain spacing.

4.3 Summary

Lower gate leakage current and higher gate turn-on voltage, as compared with the conventional CF4-treated normally-off device, was achieved by using the Al2O3

gate oxide layer. As a result, a high drain current density of 500 mA/mm was obtained at a gate voltage of 11V without the large gate leakage current, and the threshold voltage as high as 5.1 V was achieved.

Figure 4-1. Schematic cross-section of the fabricated normally-off MOS-HEMT.

Figure 4-2. IG-VGS characteristics of the normally-off HEMT with and without gate oxide layer.

-2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12

Figure 4-3. IDS-VGS characteristics of the normally-off HEMT with and without oxide layer.

Figure 4-4. Benchmark of IDSS and Vth for normally-off GaN-based HEMTs.

0 2 4 6 8 10

Figure 4-5. Pulsed IDS-VDS measurements of F-based normally-off Al2O3/AlGaN/GaN MOS-HEMT

Figure 4-6. S-parameter performance of F-based normally-off MOS-HEMT at bias point of VGS = 7 V and VDS = 10 V.

0.1 1 10 100 0

5 10 15 20 25 30

f_max = 9.5 GHz |H₂₁|²

MAG/MSG

Gain (dB)

Frequency (GHz) f_t = 4.8 GHz

( Bias Point : V

G = 3 V, V

D = 4 V )

Figure 4-7. S-parameter performance of F-based normally-off HEMT at bias point of VGS = 3V and VDS = 4V

Chapter 5

Conclusion

For the strain experiments of the AlGaN/GaN HEMTs, the channel current density of devices can be modulated by applying uniaxial tensile strain. The magnitude of the change in current density depends on the gate orientation. Although this strain can enhance DC characteristics, it also severely degrades current recovery.

Similar results from a SiNx passivation test suggest that tensile strain degrades the device transient performance. This could be attributed to the additional donor-like surface states induced by the additional piezoelectric polarization that the tensile strain produces. These findings could be useful for the optimization of SiNx passivation on AlGaN/GaN HEMTs and it also suggests that any tensile train which might occur during the device processing should be taken into consideration carefully.

For practical applications, the 100-nm gate-recessed AlGaN/GaN HEMT device was presented for 30 GHz low noise application. The minimum noise figure of 1.6 dB was obtained at 30 GHz, which could be attributed to the low gate leakage current as well as the low contact resistance due to the use of a heavily Si-doped GaN cap layer. Furthermore, an average value of 0.53 for |Rn/Zopt| from 20 GHz to 40 GHz was obtained, suggesting that such a device is a promising candidate for broadband low-noise amplifier applications in modern communication networks. Additionally, the normally-off operation AlGaN/GaN MOS-HEMT with high threshold voltage was demonstrated successfully. Lower gate leakage current and higher gate turn-on voltage, as compared with the conventional CF₄-treated normally-off device, was achieved by using the Al₂O₃ gate oxide layer. As a result, the high drain current density of 500 mA/mm was obtained at gate voltage of 11V without the huge gate leakage current, and the threshold voltage as high as 5.1 V was achieved. Such the device should be used for power electronic applications.

Appendix A

Benchmark of AlGaN/GaN HEMTs (CSDLab)

A.1 RF Power Application

The epi-structure of n-GaN 5nm / i-AlGaN 30nm / i-GaN 2μm was grown on a 3-inch semi-insulating SiC substrate using metal-organic chemical vapor deposition (MOCVD). The room temperature Hall mobility and sheet electron concentration of the wafer were 1800 cm²/Vs and 1



10¹³ cm^-2, respectively.

The HEMT device fabrication started with ohmic-contact formation.

Ti/Al/Ni/Au metal stacks (20/120/25/100 nm) were evaporated as ohmic metals and subsequently annealed at 800C for 60 s in ambient N₂. Mesa isolation was formed utilizing inductively coupled plasma etcher with BCl3/Cl2 gases. An ohmic-contact resistance of 0.28 ·mm was obtained using the TLM method. For the gate metallization, it was defined in the center of the 7 μm drain-source spacing by a optical lithography system with double-layer resist stack (PMMA/Co-polymer), followed by the metal stack of Ni/Au (20 nm/300 nm) gate deposition by e-beam evaporator. After the lift-off process, a 50



2



0.7 μm gate was formed. Afterward, a 100-nm-thick SiNx layer was deposited using plasma-enhanced chemical vapor deposition (PECVD). Finally, an air-bridge structure was electro-plated with 5 μm-thick gold. Figure A-1 illustrates the fabricated device cross-section with related geometry dimension.

Figure A-2~A-8 present DC and RF characteristics of the fabricated device.

For the DC performance, the device demonstrated 800mA/mm, 275mS/mm, and higher than 100V of saturation current density, transconductance, and three-terminal breakdown voltage, respectively. For the small signal performance, the device demonstrated 18GHz and 50GHz of FT and FMAX, respectively. For the large signal performance, the device demonstrated 7W/mm, 5.5W/mm, and 5W/mm output power density at 2GHz, 3.5GHz, and 8GHz with 61.7%, 35.28%, and 26.23%

For the DC performance, the device demonstrated 800mA/mm, 275mS/mm, and higher than 100V of saturation current density, transconductance, and three-terminal breakdown voltage, respectively. For the small signal performance, the device demonstrated 18GHz and 50GHz of FT and FMAX, respectively. For the large signal performance, the device demonstrated 7W/mm, 5.5W/mm, and 5W/mm output power density at 2GHz, 3.5GHz, and 8GHz with 61.7%, 35.28%, and 26.23%

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