1.2 MEMS Fabrication
1.2.1 Surface Micromachining Process
Different to bulk micromachining, surface micromachining does not remove material from the bulk silicon substrate, instead surface micromachining constructs structures on the surface of the silicon substrate by adding thin/thick films. Scientists at Westinghouse Electric Corp., and IBM Corp. had been demonstrated the potential of fabricating MEMS devices using surface micromachining in the 1960s and 1970s [8,9]. In surface micromachining, material is added on the substrate in the form of layers of thin films. These thin films can be characterized as structural layers or sacrificial layers. A structural layer is a material out of which the free-standing structure is made (generally polysilicon, silicon nitride and aluminium) and a sacrificial material, deposited wherever either an open area or a free-standing mechanical structure is required (usually an oxide). These layers are deposited and subsequently etched in sequence, with the sacrificial material being finally wet etched away to release the final structure. Each additional layer is accompanied by an increasing level of complexity and a resulting difficulty in fabrication [7]. Fig. 1.4 shows a basic process steps in surface micromachining [10].
Fig. 1.4 The basic process flow of surface micromachining
A well known surface micromachining process is the Cronos/MEMSCAP PolyMUMPs process. The Multi-User MEMS Process (MUMPs) was developed at Berkeley Sensors and Actuators Center (BSAC) of University of California in the late 80’s and early90’s. In the past few days, MEMSCAP offers three standard processes as part of the MUMPs® program: PolyMUMPs, a three-layer polysilicon surface micromachining process: MetalMUMPS, an electroplated nickel process; and SOIMUMPs, a silicon-on-insulator micromachining process.
They are commercial program that provides cost-effective, proof-of-concept MEMS fabrication to industry, universities, and government worldwide. As a result, the MEMS engineers/researchers can share their design space for cost-efficient research and development as well as accelerate the schedule of mass production.
The PolyMUMPs process itself consists of a non-patternable nitride isolation layer, three polysilicon layers (one polysilicon ground layer (plane layer) and two structural polysilicon layers), two oxide release layers, and one metal layer for electrical connection and reflectivity enhancement. Polysilicon is used as the structural material, deposited oxide (PSG) as the sacrificial material, and silicon nitride for electrical isolation from the substrate. Figure 1.5 shows the cross-sectional view of the PolyMUMPs process. The thickness of each layer is listed in the table 1.1. Figure 1.6 shows scanning electron microscope (SEM)
images of the micromirror fabricated through PolyMUMPs process. This micromirror is actuated by two pre-stress comb-drive actuators (PCA); hence, the micromirror can achieve rotation and vertical motion.
Fig. 1.5 Cross sectional view showing all 7 layers of the PolyMUMPs process (not to scale).
TABLE 1.1:THICKNESS OF EACH LAYER IN POLYMUMPS PROCESS.
Layer Thickness (μm)
Metal (Au) 0.5
Poly2 1.5
2nd Oxide 0.75
Poly1 2.0
1st Oxide 2.0
Poly0 0.5 Nitride 0.6
In addition, dissolving the sacrificial layer to free the structural elements, known as release process, plays a key step in the surface micromachining. Stiction, adhesion of suspended structures and the other surfaces, is the main post process setback existed in the surface micromachining. It has been widely reported to be
responsible for greatly curtailing the yield and reliability of the fabricated MEMS devices due to the phenomenon of stiction. There are several terms to evolved stiction problem such as adhesion due to Van Der Waals force, electrostatic force, capillary force and contamination [11]. A commercialized CO2 super critical drying machine will be used to improve the stiction problem in surface micromachining.
Fig. 1.6 SEM images of a micromirror fabricated through PolyMUMPs with (a) micromirror device (b) mirror and springs (c) pre-stress comb actuator.
1.2.2 BUCK MICROMACHINING PROCESS
The bulk micromachining technique is one of the most popular micromachining techniques. In bulk micromachining, the 3D mechanical structures such as cantilever beam, bridge, membrane, cavity, nozzle and trench
are formed by selectively removing (‘etching’) wafer material, as illustrated in Fig.
1.7 [12].
Fig. 1.7 Schematic view of various structures manufacturing by bulk micromachining [12].
In general, the process of bulk micromachining can be classified into isotropic and anisotropic etching. In isotropic etching, the etching rate is symmetrical in each crystalline orientation of silicon. Nevertheless, in anisotropic etching, the silicon substrate is etched with different rates along the different crystal plane, as shown in Fig. 1.8 Anisotropic etching techniques provide a high-resolution etching and tight dimensional control due to their high selectivity to different silicon crystallographic orientation [13,14].
Fig. 1.8 Difference between (a) anisotropic and (b) isotropic wet etching
1.2.3 HIGH ASPECT RATIO PROCESS
The main high-aspect-ratio process in MEMS technologies including deep reactive ion etching (RIE) [15,16], LIGA [17,18], and electroplating [19,20]
processes. Deep RIE is used to etch deep cavities in substrates with relatively high aspect ratio. Most systems utilize the so-called "Bosch process", in which a fluor polymer is used to passivate the etching of the sidewalls. Typical aspect ratios of 10 to 20 can be achieved. LIGA is an important tooling and replication method for high-aspect-ratio microstructures. The technique employs X-ray synchrotron radiation to expose thick acrylic resist of PMMA under a lithographic mask. The exposed areas are chemically dissolved and, in areas where the material is removed, metal is electroformed, thereby defining the tool insert for the succeeding moulding step. LIGA is capable of creating very finely defined microstructures up to 1000 µm high. Nevertheless, it is limited by the need to have access to an X-ray synchrotron facility. Fig. 1.9 shows the process flow of LIGA [21].
Fig. 1.9 Schematic process flow of LIGA [21]
1.3REVIEW OF MICRO-ACTUATOR IN MEMS
Various actuation mechanisms, such as thermal/bimetallic bimorph [1,22,23], electromagnetic [24,25], piezoelectric [26,27] and electrostatic actuation [28,29], have been established and applied fundamentally in MEMS-based devices where mechanical actuation is required. In MEMS research, the most widely used micro-actuator is the electrostatic actuator [30]. The main benefit of the electrostatic actuator is its characteristic in small power consumption and fast response. The simplest electrostatic actuator is a parallel-plate electrostatic actuator. Such actuators have been utilized in many applications such as accelerometers [8,9,14], deformable optics [9], and relays [11]. However, parallel-plate electrostatic actuators suffer from pull-in phenomenon, which greatly constrains the stable traveling range of actuators (usually one-third of initial gap) [31]. To avoid the pull-in phenomenon, electrostatic comb-drive
actuators have been developed [32]. This actuator consists of two interdigitated finger structures with one fixed and the other connected to suspended springs, as shown in figure 1 (a). By applying a driving voltage between the movable comb fingers and fixed comb fingers, a displacement of movable comb fingers toward fixed comb fingers generates by the attractive electrostatic force. An electrostatic comb-drive actuator offers a near constant force over a large range of displacements. This actuator becomes a preferred design for implementing of electrostatic actuator. Applications of electrostatic comb-drive actuators include resonators [33,34], microgrippers [35], x-y microstages [36] and electromechanical filters [37].
Although electrostatic comb-drive actuators have these advantageous characteristics, the stable traveling range of the comb-drive actuator is limited by the electromechanical side instability (side pull-in). Side instability means that the situations in which the movable comb fingers move perpendicular to the stroke direction and then make contact with the fixed comb fingers. As the overlapping comb fingers area increasing with the forward displacement of the actuator, the cross-axis force become larger and larger that causes the fingers suddenly snapping over sideway. The side instability and stable traveling range of electrostatic comb-drive actuators depend on finger gap spacing, initial finger overlapping, and spring stiffness of suspended springs. Increasing finger gap spacing of an electrostatic comb-drive actuator is the simplest method for increasing the stable traveling range; nevertheless, this method results in a high driving voltage which is undesirable in numerous applications. To extend the stable traveling range of electrostatic comb-drive actuators, several approaches have been developed [38-41]. Among these methodologies, the most widely used method is to design different types of suspended springs to enhance the cross-axis
stiffness which need extra driving voltage to extend the traveling range.
1.4DISSERTATION WORK
In this dissertation, we focus our research to develop cascade electrostatic comb-drive actuators. With the novel cascade multi-stage configuration, the traveling range can be extended without extra driving voltage..
The dissertation is organized as follows. Chapter 2 illustrates the fabrication processes including CMOS fabrication processes and post-CMOS micromachining steps. In chapter 3, a lateral cascade electrostatic comb-drive actuator is presented. The FEM simulation and experimental results are also given to demonstrate our design concept. Chapter 4 proposed a vertical type of the cascade electrostatic comb-drive different from the chapter 2, and the design concept, simulation, and experimental results are also given. Chapter 5 summarizes the accomplishments of the dissertation and provides suggestions for further research.
CHAPTER II
CMOS-MEMS FABRICATION PROCESS
2.1INTRODUCTION
In this dissertation, the cascade micro-actuators were initially fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 μm two polysilicon and four metal layers (2p4m) complementary metal-oxide-semiconductor (CMOS) fabrication processes. After CMOS process, post-CMOS micromachining steps are employed to define MEMS structures and release suspended structures. Section 2.2 gives an overview of the CMOS MEMS processes. CMOS processes and Post-CMOS micromachining steps are described in the section 2.3.
2.2CMOSMEMS
While MEMS technology has made a substantial impact over the past decade at the device or component level, it has yet to realize the “S” in its acronym, as complex microsystems consisting of sensors and actuators integrated with sense, control, and signal-processing electronics are still beyond the current state of the art [42-46]. There are several incentives to co-fabricate MEMS devices and electronics on a single silicon chip, which apply to applications such as inertial sensors. The parasitic resistance and capacitance associated with the interconnection between the MEMS devices and electronics degrade electrical signal quality and hence degrade system performance. This problem is critical for
thin-film, surface micromachined devices in which changes in position are sensed as a small, capacitively induced current. If the MEMS devices can be co-fabricated with electronics on a single chip, the parasitic resistance and capacitance of these components can be greatly reduced. The elimination of chip-to-chip interconnections can also lead to more reliable packages. This is especially important for large arrays of MEMS devices that require independent addressing of each element, such as the micromirrors in an optical cross-connect switch, for which the monolithic integration of switching electronics can reduce the number of off-chip connections by orders of magnitude. Depending on the integration strategy that is adopted, the co-fabrication of microstructures and electronics on the same substrate may provide significant overall cost savings.
The integration of micromachining steps with CMOS process can be accomplished in different ways. The additional steps (or process modules) can either precede the CMOS process (pre-CMOS) or be preformed in between the CMOS process (intra-CMOS) or after the completion of the CMOS process (post-CMOS).
2.2.1 PRE-CMOS
In the pre-CMOS approach, the MEMS structures or part of them are formed before the regular CMOS process sequence. Pre-CMOS micromachining or
‘MEMS-first’ fabrication approaches avoid thermal budget constraints during the MEMS fabrication. In this way, e.g. thick polysilicon microstructures requiring stress relief anneals at temperatures up to 1100 ºC can be co-integrated with CMOS circuitry. Typically, the MEMS structures are buried and sealed during the initial process module. After the wafer surface is planarized, the preprocessed
wafers with embedded MEMS structures are used as starting material for the subsequent CMOS process. Challenges include the surface planarization required for the subsequent CMOS process and the interconnections between MEMS and circuitry areas. A number of pre-CMOS technologies have been developed [47-54]. Fig. 2.1 shows two schematic cross-sectional views of pre-CMOS MEMS processes.
Fig. 2.1 Schematic cross-sectional views of two pre-CMOS MEMS processes: (a) M3EMS technology developed by Sandia National Laboratories [47]. (b) SOI MEMS with 10 μm device layer for fabrication of single-crystalline silicon inertial sensors [52].
2.2.1 INTRA-CMOS
In the intra-CMOS approach, the CMOS process sequence is interrupted for additional thin film deposition or micromachining steps. This approach is
commonly exploited to implement surface micromachined polysilicon structures in CMOS technology. Either the standard gate polysilicon or an additional low-stress polysilicon layer is used as structural material. Intermediate micromachining is most commonly used to integrate polysilicon microstructures in CMOS/BiCMOS process technologies. Inserting the micromachining process steps before the back-end interconnect metallization ensures process compatibility with the polysilicon deposition and anneal. The polysilicon annealing temperature is typically limited to about 900 ºC in order not to affect the doping profiles of the CMOS process. Commercially available examples of polysilicon microstructures, fabricated with CMOS/BiCMOS processes with intermediate micromachining, include Analog Devices ADXL series accelerometers and ADXRS series gyroscopes [55], Infineon Technologies’ KP100 series pressure sensors [56] and Freescale’s (Motorola) MPXY8000 series pressure sensors [57]. Fig. 2.2 shows two cross-section of intra-CMOS processes
Fig. 2.2 Schmatic cross-sectional view of two intra-CMOS processes: (a) Analog Devices’ integrated MEMS technology with an n+-diffusion interconnect structure between polysilicon microstructure and on-chip electronics [58].(b) Srface micromachined pressure sensor element developed at Toyota Central R&D Laboratories [59].
2.2.1 POST-CMOS
In the post-CMOS approach, two general fabrication strategies can be distinguished. In the first strategy, the MEMS structures are completely built on top of a finished CMOS substrate, leaving the CMOS layers untouched. Examples for this approach are Texas Instruments' Digital Micromirror Device (DMD) [60,61], the electroplated ring gyroscope developed by Delphi Automotive
Systems [62-64], the electroplated acceleration switch developed by Infineon [65,66], and Honeywell's thermal imagers [67]. In all four cases, the microstructures are released using sacrificial layer etching. Alternatively, the MEMS can be obtained by machining the CMOS layers after the completion of the regular CMOS process sequence. Using a variety of CMOS compatible bulk and surface-micromachining techniques, e.g., pressure [68-70], inertial [71], flow [72], chemical [73], and infrared radiation [74] sensors have been produced this way. Both post-CMOS approaches are attractive, because the CMOS wafers can be processed at any CMOS (or BiCMOS) foundry. This way, even very advanced CMOS technologies with multiple (copper) metallizations can be exploited for MEMS. The main limitation of the post-CMOS technologies is the stringent thermal budget for the add-on fabrication steps, limiting process temperatures to about 400 "C. Fig. 2.3 illustrates the cross-sectional views of two different post-CMOS processes.
Fig. 2.3 Schematic cross-sections of (a) polysilicon and (b) polycrystalline silicon germanium (poly-SiGe) microstructures fabricated by post-CMOS surface micromachining techniques on top of a completed CMOS substrate wafer [75,76].
2.3FABRICATION PROCESSES
The CMOS processes and post-CMOS micromachining steps utilized to fabricate the proposed devices are described in the following two sections.
2.3.1 CMOSFABRICATION PROCESS
The beginning of the CMOS processes is a lightly p-doped (110) wafer with a typical doping concentration of NA~1015. The first step is the definition of the active areas by local oxidation of silicon (LOCOS), thus growing a thick (~0.4 µm) field oxide in the areas between the individual transistors. Next, the p-wells for the n-channel MOSFETs and the n-wells for the p-channel MOSFETs are
impla1nted. A joint drive-in for both wells establishes the desired junction depth of 2–3 µm. Typically, drive-in times are 4–6 h at 1000-1100 ℃. The n-well diffused in the p-substrate can be used to define accurately the thickness of a silicon membrane. Such membranes are commonly released by anisotropic wet etching from the back of the wafer using an electrochemical etch-stop technique at the p-n junction between n-well and p-substrate.
After n- and p-well formation, the MOSFET gate and channel regions are engineered. First, Channel implants for the n- and the p-channel transistors are implanted to adjust their threshold voltage to the desired values. After removing the implantation oxide in the active area, the fate oxide with a thickness ≦ 10 nm in modern CMOS process is thermally grown in the active areas. Next, a 0.3–0.5 µm thick polysilicon layer for the gate electrodes is deposited across the wafer in an LPCVD furnace operating at about 600 ℃ and doped by ion implantation.
Finally the polysilicon layer is patterned to define the actual gate regions. In MEMS, the gate polysilicon can also be used for resistors, pizoresistors, thermopiles, electrodes, and as structural materials. The last application often requires a high-temperature anneal of the polysilicon to reduce its residual stress to values acceptable for the microstructures. Such a high temperature step can be critical at this stage in the CMOS process, as it might effect previous doping distributions and, hence, the CMOS device characteristics.
After gate formation, the source/drain regions are implanted. In typical sub-micro CMOS technologies, this is done using a LDD (light doped drain) process. It provides a gradient in the doping of the source/drain regions towards the channel region, reducing the peak value of the electric field close to a channel and, hence, increasing device reliability. First phosphorus (or arsenic as alternative
* Appendix A: CMOS Process Flow
n-type dopant) is implanted in the source/drain of the NMOS transistors to form n¯ regions, followed by a boron implantation of the source/drain of the PMOS transistors to form p¯ regions. Next, a conformal spacer dielectric layer is deposited on the wafer and anisotropically etched back, leaving sidewall spacers along the edges of the polysilicon gate. After growing a thin screen oxide for the following implantation, the wall spacer of the source/drain region of the NMOS and PMOS transistors not protected by the sidewall spacer are successively implanted to form n+ and p+ regions, respectively. The final step of the source/drain engineering is a furnace anneal, typically at ~ 900 ℃ for 30 min, to activate the implants, anneal implant damage, and drive the junctions to their final depth. Alternatively to the furnace anneal a much shorter rapid thermal anneal at higher temperatures can be performed (e.g. 1 min at 1000–1050 ℃). The fabrication of the active devices is now completed. Any subsequent high-temperature step (above 700–800 ℃) necessary for the MEMS fabrication must be carefully qualified, as it night affect the doping distributions in the active devices, thus potentially changing the device characteristics.
In the back end of the process, the individual active devices are interconnected on the wafer to form circuits and pads for input/output connections off the chip are created. Although a large number of back-end metallization process flows with up to eight metallization levels exist, the CMOS processes described in this dissertation use four metallization levels. The contacts to the source/drain regions and to the gate polysilicon are based on tungsten (W) with a TiN (titanium nitride) adhesion/barrier layer. To planarize the surface of each layer, modern CMOS processes often use chemical mechanical polishing (CMP) for interconnect and interconnect dielectric planarization. Each of the following wiring levels uses CVD tungsten vias with a TiN adhesion/barrier layer and an
aluminum (with a small percentage of Si and Cu) interconnect layer. Finally, the passivation layer is deposited (typically by PECVD) and patterned to form the pad openings necessary to contact the device from the outside. The composition of the passivation layers are SiO2 and Si3N4. After passivation, the wafers are annealed at low temperatures (400–500 ℃) for about 30 min in forming gas (10% H2 in N2) to alloy the metal contacts. The thickness of each layer is shown in fig. 2.4.
Fig. 2.4 Thickness of each layer for the TSMC CMOS process.
2.3.2POST-CMOSMICROMACHINING STEP OF CIC
The CMOS processes make use of two polysilicon layers, four metal layers, three via layers, and several dielectric layers/sacrificial layers. The four metal layers are made of aluminum. The contact and via holes are filled with tungsten
The CMOS processes make use of two polysilicon layers, four metal layers, three via layers, and several dielectric layers/sacrificial layers. The four metal layers are made of aluminum. The contact and via holes are filled with tungsten