A closed-loop diagram of the boost converter with the HCC technique is shown in Fig. 5.
The loop gain is T(s) as shown in (19). H(s) is the sensor gain, which is equal to R2/(R1+R2).
Gc(s) is the compensation transfer function. Generally, Gc(s) is composed of an error amplifier and a PI compensator. The PI compensator contributes one low-frequency pole-zero pair, (ωpc1, ωzc1), and one high-frequency pole, ωpc2.
( ) vc( ) ( ) c( )
T s =G s H s G s⋅ ⋅ (19)
H(s)
Fig. 5. The simplified feedback system of the HCC regulator.
Therefore, T(s) can be illustrated in Fig. 6 at light and heavy loads. Owing to the decrease of the RHP zero ωz(RHP) at heavy loads, the compensation zero, fzc1, in the PI compensator is designed to cancel the effect of the system output pole, ωp1, in order to extend the system bandwidth. However, at heavy loads, the crossover frequency is limited by ωz(RHP), which is represented by a solid dash line in Fig. 6(a). Thus, it is hard to have a good cancellation of the system output pole. According to Fig. 4(b), the ratio of ωc and ωz(RHP) has an optimum value when the dip output voltage is the major concern. That is the compensation zero is decided at heavy loads.
On the other hand, the bandwidth becomes worse due to the decrease of ωp1 at light loads.
As depicted in Fig. 6(b), the compensation zero can be adaptively adjusted within a stable region. The maximum value of ωzc1 is determined by the phase margin since there are two poles at low frequencies when the compensation zero is moved toward high frequencies. On the other hand, the minimum value of ωzc1 is determined by the minimum value among ωz(RHP)
and ωpc2 since the decrease of ωzc1 also causes the decrease of ωpc2. As a result, the minimum is no longer decided by ωz(RHP) since ωpc2 is smaller than ωz(RHP) at light loads. In order to get a better phase margin at light loads, ωzc1 needs to be adaptively moved toward the origin at light loads. Consequently, an adaptive compensation zero locates high frequencies and low
frequencies at heavy loads and light loads, respectively. However, an adaptive compensation zero can ensure a good phase margin but the transient response is still not improved due to the limitation of low-frequency RHP zero. Thus, the MHCC technique includes an ACC technique to get fast transient response and good phase margin in steady state.
1
fzc fpc2
1
fpc
1
fp
1
fzc fpc2
1
fpc
1
fp
(a)
1
fp 1
fpc
1
fzc fpc2
1
fp 1
fpc
1
fzc fpc2
(b)
Fig. 6. The compensated loop gain T(s) (a) at light loads and (b) at heavy loads.
Chapter 3
The Proposed MHCC Technique for Fast Transient Response
The proposed MHCC architecture is shown in Fig. 7. It can ensure a limited output ripple and adjust the trailing and leading edges for fast transient response. Besides, the ACC technique can rapidly regulate the output of the error amplifier to speed up the transient response and guarantee a good phase margin in the steady state. The difference voltage between the upper band VIH and the lower band VIL forms the hysteresis current window, which is product of Ihys and Rhys. VIL is equal to the output voltage Veao of the error amplifier for improving the accuracy of load regulation. The adaptive compensation control technique is composed of the adaptive resistance and capacitance, which are controlled the ACC controller. As a result, the compensation poles and zeros can be adaptively adjusted during load transient and steady state.
Fig. 7. The system architecture of the proposed boost converter with the proposed MHCC technique.
3.1 The ACC Technique
As depicted in Fig. 8(a), the PI compensator is connected at the output Veao of error amplifier. Since only small on-chip capacitor is allowed in IC fabrication, the small feedback voltage VFB may cause a large voltage variation at Veao since high-frequency compensation zero contributes insufficient phase margin. Therefore, a pseudo large capacitance can be generated through a mirrored ac current, K*ic, connecting to ground as illustrated in Fig. 8(b) [11] [12]. As a result, Veao can have a stable settling behavior since a large transient current can be re-directed to ground. Similar to the off-chip compensation zero, a pseudo low-frequency compensation zero is used to cancel the effect of the output system pole. As mentioned above, the bandwidth is small due to the RHP zero.
In Fig. 8(c), the ACC technique modifies the pseudo compensation poles and zeros to get a small dip output voltage and fast transient response time. According to Fig. 4(b), the ratio of ωc to ωz(RHP) can be increased for a short period to get a higher bandwidth and the dip output voltage will not be increased too much when the operation point from B toward higher ratio of ωc to ωz(RHP). That is the fast transient period will push the operation point from point B to C, and to D. After the fast transient period, it is pushed back to point B, again, to ensure better PM value. The fast transient period only occupies one fraction of the transient period. The dip output voltage can be smaller than that without the ACC technique. Therefore, the value of Veao can be rapidly settled to its stable level and thus the MHCC technique can achieve a fast transient response and small dip output voltage without being limited by the RHP zero.
(a)
VFB
Error Amplifier
Veao
Vref
RO
R1
R2
RZ1
Vo
gm
iC
K*iC On-chip
small CZ1
W/o ACC
PI compensator
(b)
VFB
Fig. 8. The PI compensator (a) with a small on-chip capacitor, (b) with the pseudo capacitance, and (c) with the ACC technique.
The operation of the ACC technique needs to carefully control compensation poles and zeros during the fast transient period. Basically, the fast transient period contains two stages, which are the transient 1 and the transient 2 stages. At the transient 1 stage, the mirrored ac current is fully re-directed to the small on-chip capacitor to rapidly recovery the voltage level of Veao. After the transient 1 stage, the transient 2 stage needs to detect the valley point of the dip output voltage in order to pull back the compensation poles and zeros to the position that ensures the system has a better PM value. The compensation poles and zeros controlled by the ACC technique are shown in Fig. 9 (a) and (b) when load current changes from light to heavy and vice versa.
(a)
0dB
time
Fig. 9. (a) The compensation poles and zeros controlled by the ACC technique when load current changes from light to heavy. (b) The compensation poles and zeros controlled by the ACC technique when load current changes from heavy to light. (c) The load transient waveforms controlled by the MHCC technique.
3.2 The Compensation of the Modulation Techniques
The switching frequency of PWM mode is fixed and the switch has to turn on and off every switching cycle. The recovery time takes a longer time as shown in Fig. 10(a) when the output current changes from light to heavy. On the other hand, the inductor current in the HCC technique is controlled within two boundaries ic, which is determined by the error amplifier, and ic +∆I as depicted in Fig. 10(b). ∆I is the current hysteresis window. The recovery time can be shortened since the on-time value will not be limited by the maximum on-time value in the PWM control technique. The switching period can be extended and thus the inductor current can be rapidly increased to the regulated level. The current of il_sub1 gets more time to reach the boundary ic +∆I. The system frequency of the boost converter
recovery time of the HCC technique is faster than that of the current-mode PWM technique.
The fast recovery of ic can speed up the transient response time. Therefore, the proposed MHCC technique rapidly regulates the output of the error amplifier in order to shorten the transient response time. However, the system bandwidth is limited by the RHP zero in the boost converter. The MHCC technique utilizes the characteristics of the RHP zero to cause a large control signal due to worse phase margin to rapidly recover the voltage level at the output of error amplifier. However, the worse phase margin can’t ensure the stable operation in the steady state. The MHCC technique can adaptively adjust the compensation poles and zeros to low frequencies to guarantee the system stability. During the transient response, if ic
can rise and fall as soon as possible, the recovery time will be shortened as shown in Fig.
10(c).
'
I N O U T
V V
= D
(a)
Heavy Load
∆I
Light Load
Smaller Recovery time
iL-sub1 iL-sub2
ic
ic+ ∆I
Inductor Current Load Current
(b)
(c)
Fig. 10. Recovery time during light load to heavy load: (a) The waveforms controlled by the PWM technique. (b) The waveforms controlled only by the new HCC technique. (c) The waveforms controlled by the proposed MHCC technique.
Chapter 4
The Circuit Implementation
The proposed MHCC technique contains two main blocks. One is the HCC circuit and the other one is ACC circuit. The current sensor and the fixed hysteretic current window circuit constitute the HCC circuit. The adaptive compensation resistance and capacitance circuits and the ACC controller constitute the ACC circuit.
4.1 Current Sensor
The HCC technique needs to sense the full-range inductor current. Thus, an accurate current sensor is required. As depicted in Fig. 11, a small value of sensing resistor RS is connected in series with the inductor to sense the full-range inductor current. It may cause a little reduction in the power conversion efficiency but it is a simple implementation. The transistors M1 and M2 are biased by the same current I1. Thus, VSG1=VSG2. According to the current values labeled in the figure, (20) can be derived and simplified as (21) if R1=R2 under a good layout matching result.
1 ( 1) 1 2 ( 1) 1 2
As a result, the sensing signal VSENSE can be expressed in (22) and used to represent the full-range inductor current. Easily, the value of VSENSE can be scaled by the ratio of (RS*RV) to R1. According to the operation of the HCC technique, the value of VSENSE is limited within the hysteresis window, which is controlled by the fixed hysteretic window circuit.
1 S V
SENSE o V L L
V I R I R R I
= = R ∝ (22)
Fig. 11. The schematic of current sensor.
4.2 Fixed Hysteretic Current Window Circuit
In Fig. 12, the fixed hysteretic current window circuit is designed to accurately control the output ripple for ensuring the regulation performance. The low band of the fixed hysteretic current window is controlled by the output of the error amplifier, which is Veao. Thus, a unity-gain buffer used to filter out the switching noise can generate the low band VIL. The hysteretic window is easily generated by adding an IR-drop to the low band VIL. The value of IR-drop is derived by a constant current flowing through a hysteresis resistor Rhys. As a result, the upper band VIH can be expressed by (23). The cascaded current mirror M6 and M7 can suppress the channel length modulation effect to get a higher accuracy.
1
IH IL N hys
V =V +I ×R (23)
Veao Fig. 12. The fixed hysteretic current window circuit.
4.3 The Adaptive Capacitance and Resistance Circuits and the ACC Controller
The fast transient mechanism is triggered by the threshold detector in Fig. 13(a). Once the feedback voltage VFB is higher or lower than VH or VL, respectively, the ACC controller starts to control the fast transient procedure. The ACC technique can speed up the transient response by two transient procedures. One is transient 1 stage and the other is transient 2 stage.
The transient 1 stage is simply decided by a one-shot circuit to rapidly increase the voltage of Veao. As depicted in Fig. 13(a), the one-shot period can be determined by (24).
The one-shot period is inversely proportional to the input voltage since the one-shot
value should be shortened under a large input voltage. Besides, a bigger overshoot output voltage and undershoot output voltage need a longer one-shot value. The time constant RSCS
can be adjusted by the trimming process to ensure the system stability at any loads.
The adaptive resistance is shown in Fig. 13(b) and equal to the value of two resistances in parallel. That is, RZ1= RLIGHT||RMN_HEAVY. The maximum equivalent value of RZ1 is designed to RLIGHT at light loads since the transistor MN_HEAVY operating in cut-off region causes RMN_HEAVY large to be ignored. The adaptive capacitance in Fig. 13(b) contains the voltage follower designed by the low-voltage operational amplifier to ensure the accurate current mirror constituted by the transistors M1~M4. The input common mode range can be set from 0.4V to 1.9V. The current mirror array can determine the value of the pseudo capacitance Cpseudo. The ratio of the current mirror array is 1:M:N:(100-M-N). In this paper, M=65 and N=30. During the transient 1 stage, the switches in Fig. 13(b) are set by the table in Fig. 13(c).
Thus, Cpseudo changes from (1+K)CZ1 to the value as shown in (25).
That is, 95% of the mirrored current is directed to the small capacitor CZ1 to rapidly increase the voltage level of Veao. As a result, the system bandwidth can be extended and the drop voltage can be reduced. However, the phase margin is not enough to ensure a stable operation. Thus, the one-shot timing control in (24) depends on Vin and Vo to avoid oscillating.
After the transient 1 stage, the transient 2 stage is determined by the valley of the output voltage. Thus, a peak detector in Fig. 13(a) is required to decide the period of the transient 2 stage. As illustrated in Fig. 13(d), the feedback signal VFB can be filtered by two low-pass filters, which are (RLP1, CLP1) and (RLP2, CLP2), to generate two output signals VLP1 and VLP2. In the transient 2 stage, the switches in Fig. 13(b) are conservatively set to increase Cpseudo to the
1
During the transient 2 stage, the compensation poles and zeros are pulled toward the origin to get a higher PM value. Once VLP1 is higher than VLP2, the transient 2 stage is ended.
After the detection of the peak value, the compensation poles and zeros are set to the positions that can guarantee an adequate PM value. Cpseudo is equal to (1+K)CZ1, again.
SB1
VDD VC2
RMN_HEAVY Adaptive resistance (RZ1)
(b)
(c)
(d)
Fig. 13. (a) The schematic of the ACC controller. (b) The adaptive capacitance circuit. (c) The controlling table of the switches. (d) The waveforms of the peak detector.
In Fig. 14(a), the Bode plot is shown when load current changes from light to heavy.
Besides, the position of all poles and zeros is listed in Fig. 14(b). The value of fc is set to about 30% of the value of fz(RHP) at heavy loads. It has been mentioned in Fig. 4(b). Similarly, the Bode plot is shown in Fig. 15(a) when load current changes from heavy to light. Fig. 15(b) lists the relationship of the poles and zeros. At light loads, the value of fc is set to about 30%
of the value of fpc2. The adaptive resistance moves both fzc1 and fpc2 toward the origin. Thus, fpc2 is smaller than fz(RHP) at light loads. In other words, fpc2 determines the position of fc.
1 10 100 1 103 1 104 1 105 1 106
70mA to 270mA Bode Plot
Frequency
Output load current changes from light (70mA) to heavy load (270mA).
①
Fig. 14. (a) The Bode plot when load current changes from light to heavy. (b) The position of all poles and zeros.
(a)
Output load current changes from heavy (270mA) to light (70mA) load.
①
Fig. 15. (a) The Bode plot when load current changes from heavy to light. (b) The position of all poles and zeros.
4.4 The Start-up Circuit and the Protection Circuits
The flow chart as depicted in Fig. 16(a) includes the start-up operation, the protection functions, and the MHCC operation. When the power is turned on, the chip begins the start-up procedure. As a result, it is necessary to have the under-voltage lockout (UVLO) circuit as shown in Fig. 16(b) to determine whether the power supply is greater than 2.5V or not. If the supplying voltage is not high enough, the closed-loop is not adequate to be established in order to avoid oscillating. Before the supplying voltage approaches the pre-defined voltage level, the value of UVLO is high and can be expressed as (27).
In this paper, the supplying voltage should be larger than 2.5V to guarantee a stable closed-loop operation. Before the closed-loop operation, the output is connected to the input supplying voltage through the inductor. Once the power supply is greater than 2.5V, the start-up circuit takes over the operation. That is the switching converter will begin to boost the output to a higher output voltage level. During this start-up procedure, the maximum inductor current IL_max_startup is limited below 1.13A.
In the implementation of the start-up circuit, it is easy to divide the resistor RV in Fig. 11 into three small resistors, RV1~RV3 in Fig. 16(b). Good layout matching can guarantee the accuracy the current sensing and the protection function. According to (21), the divided voltage VST at node X can be used to limit the inductor current during the start-up period. Thus, the value of IL_max_startup can be expressed as (28).
(
1)
When the output voltage Vo approaches to 12V, the feedback voltage VFB will be greater
MHCC operation. The maximum inductor current will be raised to a higher level to avoid the overloading condition during the MHCC operation. The voltage VOCP at node Y is used to compare with Vref to detect the over current protection (OCP) condition and thus the protection current of the OCP protection is higher than that of the start-up period. The expression of OCP is shown in (29). When the OCP condition occurs, the ST_OK will be set to 0 and the high voltage (HV) N-MOSFET, HN24G5, will be turned off to let the system return to the start-up operation.
1 when o V2 ref
OCP = I ×R >V (29)
(a)
IO
Fig. 16. (a) The flow chart includes the start-up operation, the protection functions, and the MHCC operation. (b) The start-up and protection circuits.
Chapter 5
Experimental Results
The proposed boost convert with the MHCC technique was fabricated by TSMC 0.25 µm CMOS process. The threshold voltages of nMOSFET and pMOSFET are 0.477 V and -0.596 V, respectively. The off-chip inductor and output capacitor are 6.8 µH and 10 µF, respectively. The output voltage Vo is 12V to drive 3 white LEDs in series. The specification is listed in Table I. The chip micrograph is shown in Fig. 17 and the chip area is about 1480 µm × 2780 µm including the test pads.
C_Multiplier Peak Detect Error Amp.
BIAS
Fig. 17. Chip micrograph.
TABLE I THE DESIGN SPECIFICATION
Characteristics Typ. Unit
Supply Voltage (Vin) 3.5~4.5 V
Output Voltage (Vo) 12 V
Output Current (Iload) 70~270 mA
Input Inductor (L) 6.8 µH Equilibrium series Resistance of
the inductor (DCR) 45 mΩ
Output capacitor (CO) 10 µF
Equilibrium series resistance of
the output capacitor (RESR) 50 mΩ
Operation temperature 0~100 ℃
Experimental results of conventional boost converter are shown in Fig. 18. The input voltage is 4V. The load currentchanges from 70mA to 270mA. The slew rate of load current is 200mA/us. The undershoot voltage and overshoot voltage are 338mV and 308mV, respectively. The recovery time is 141µs when load current changes from light to heavy load or heavy to light. And the load regulation is 0.16mV/mA. It is obvious to see that the bandwidth is limited by the existence of the RHP zero. Under the low-bandwidth design, the transient response can’t be speeded up. Thus, the slow-response output voltage may cause the LEDs in series have a little of luminance variation when the dimming control is applied on the LED brightness control.
(a)
(b)
11.845V 11.877V
VOUT
IL
Recovery time = 141µs
Iload=270mA 70mA within 2µs
Iload
32mV Load regulation =0.16mV/mA Overshoot voltage
=308mV
(c)
Fig. 18. Waveforms in conventional boost converter with hysteresis control when load current changes from 70mA to 270mA within 2µs.
Compared to the slow-response of the conventional design, the experimental results of the proposed boost converter are shown in Fig. 19. The test setting is the same as the conventional design. The undershoot voltage and overshoot voltage are 300mV and 234mV, respectively. The recovery time of light load to heavy load is 19.5µs and the recovery time of
heavy load to light load is 18.8µs. Experimental results show the improvement in transient response is higher than 7.2 times when load current changes from light to heavy or vice versa compared to the conventional boost converter design. The improvement comes from the new HCC and the ACC techniques. The output of the error amplifier can be settled rapidly by the ACC technique to define the low band of the hysteresis window. Besides, the new HCC
heavy load to light load is 18.8µs. Experimental results show the improvement in transient response is higher than 7.2 times when load current changes from light to heavy or vice versa compared to the conventional boost converter design. The improvement comes from the new HCC and the ACC techniques. The output of the error amplifier can be settled rapidly by the ACC technique to define the low band of the hysteresis window. Besides, the new HCC