Chapter 5 Test Setup and Experimental Results
5.3 The Die Photomicrograph, Testing Board, and Pin Configuration
Figure 5.8 shows the die photomicrograph of the experimental SDM and Figure 5.9 shows the photograph of the testing DUT board. Figure 5.10 presents the pin configuration and lists the pin assignments of the experimental SDM.
Figure 5.8 Die photomicrograph of the proposed SDM
Figure 5.9 Photograph of the SDM DUT board
Figure 5.10 (a) Pin configuration diagram and (b) Pin assignment
Pin Name I/O Describe
1 NC - No connection
2 GND - DUT Ground
3 NC - No connection
4 INN In Input Signal (0°) 5 INP In Input Signal (180°) 6 B3 In Bias Voltage 7 OUTN Out Output Signal (0°) 8 REN In DAC Feedback Voltage 9 CLK In System clock input 10 NC - No connection 11 REP In DAC Feedback Voltage 12 OUTN Out Output Signal (180°) 13 B5 In Bias Voltage 14 B2 In Bias Voltage 15 B1 In Bias Voltage 16 NC - No connection 17 VDD - DUT Supply Voltage 18 NC - No connection
5.4 Performance Evaluations of SDM
This proposed SDM chip has fabricated by TSMC 0.18 μm technology. It was powered by 1.8 V supply. A 4 kHz sine wave is applied and the clock rate is 2.5MHz while the corresponding bandwidth is 20 kHz. The time-domain analysis is measured by an oscilloscope (Figure 5.11).
Figure 5.11 Measurement result of output waveform
Figure 5.12 shows the measured spectrum. The input signal frequency is 4kHz and the signal bandwidth is 20kHz. The output bit streams can be recorded with a logic analyzer, so that the data can be processed with MATLAB. The fast Fourier transformation with 8192 points was used and the Blackman window was applied [30].
Figure 5.13 shows the SNDR versus normalized input signal. The peak SNDR and DR are 43.2dB and 47dB of -9dB input, respectively. This corresponds to a resolution of 7 bits. The power consumption is only 0.198mW. The complete measured performance summary of the third-order SDM is given in Table 5.1.
Figure 5.12 Measured output spectrum
Figure 5.13 Plot of SNDR versus normalized input signal
Table 5.1 Summary of measured results of the SDM
5.5 Summary
The design of third-order continuous-time SDM was completed. It took the design considerations described in Chapter 3 and Chapter 4 into account. The original resolution was predicted to achieve 10bits. The measured result shows that the actual performance is 7bits. The possible reasons of performance decay are that the resistances variation, thermal noise, operation amplifier performance decay, and the noise of external circuits on the testing printed circuit board. The noise floor of the input signal is a little large due to the external circuits which are single-to-differential transformer circuit and AC couple circuit. And the mismatch of input differential signal is also the possible reason which causes the performance decay. If we could reduce the number of the external circuits, the performance would be much better.
Specification Measured Results
Signal Bandwidth 19.84 kHz
Sampling Frequency 2.5 MHz
Dynamic Range 47 dB
Peak SNDR 43.2 dB
Peak SNR 45.3 dB
Resolution 7 bits
Area 0.56×0.56=0.32 mm2
Power Dissipation @ 1.8V 198 μW
Technology Standard TSMC 0.18μm 1P6M
Chapter 6
Conclusions
Generally, the continuous-time technique is applied in higher frequency domain.
In order to achieve medium resolution and very low power in audio application domain, we use continuous-time technique to implement the SDM due to its important property of very low power consumption. This thesis presents the basic concepts for SDM including quantization noise, noise shaping strategy, and system overview of SDM are introduced. After system level simulation for building the behavior model to understand the characteristics of SDM and determine the specification, the circuit level and layout level design are presented.
In the thesis, a low power continuous-time SDM with active RC integrator is fabricated in TSMC CMOS 0.18 μm standard process. The resolution is 7 bits and the measured power consumption is only 0.198 mW for a 1.8-V supply. The influence of circuit design parameter and non-ideal effect like amplifier gain bandwidth and distortion on overall SDM has been studied. As a result, the low power consumption shows that the continuous-time technique is a good alternative to switched-capacitor realization.
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