Chapter 3 Turbo Decoder Design Consideration
3.2 The Parallel Turbo Decoder
3.2.3 The Interleaver of Parallel Turbo Decoders
registers would be needed, and the number of registers are N. The size of each register is: (number of states) (⋅ bits for forward metrics representations
Here, we would like to note several properties of the suggested PSW technique:
Owing to the memories and the processing hardware cost, the area grows linearly with the number of parallel SISO decoders N, and the decoding latency drops linearly with N, making this PSW method very suitable for a parallel architecture.
For the same decoding latency as parallel log-MAP decoding and almost the same amount of processing hardware much less intermediate memory is used.
The decoding performance can be very closely estimated using the results obtained for sliding window decoding.
Figure 3.3 Schedule of the parallel sliding window technique
3.2.3 The Interleaver of Parallel Turbo Decoders
process. The memory conflict problem is that the different SISO decoders work in parallel, it is necessary to access the extrinsic information by each SISO decoders in different RAM memories. In fact, depending on the specific permutation rule, it may happen that different SISO decoders try to access the same memory bank at the same time instant. We describe the problem in Figure 3.4, for a conventional turbo decoder in Figure 3.3 (a), it would not happen the collision problem as the only one SISO decoder stores or reads extrinsic information; while taking an example as 4-parallel SISO decoders in Figure 3.3(b), we permute the four extrinsic information in order and write the four extrinsic information according to interleaving order, then we find that SISO2 and SISO4 decoders simultaneously access the same memory bank. In the next cycle, we also find that SISO1 and SISO3 decoders access simultaneously the same memory bank.
Figure 3.4 (a) conventional turbo decoding without collision (b) parallel turbo decoding with collision problem
To solve the problem, [21] had proposed a feasible method that can be used for any interleaver rules. We explain this method as follows. Given banks of memory, each SISO decoder works on a sub-block with length
Nw
/Nw
w L= . If we number all extrinsic information from 1 to L, the j-th SISO exports those values from
to . We assume that all SISO decoders (i.e. to ) export their extrinsic information at time instant are those in position , , …,
, and those relative position after write in (interleaving) or read out (de-interleaving) the memory banks are
(j−1)w+
To formalize the problem of mapping from decoders to memory banks, we can define a pair of functions
(
M S,) {
: 1,...,L} {
→ 1,...,Nw} {
× 1,...,w}
, with the following meaning:For each decoder, the i-th output is written in the memory bank indexed by M i , in ( ) position . The condition of lack of collisions translates then into the following constrains on
Notice that the above constraints only depend on π, and that no constraint is imposed on the shift function S.
It is useful to represent the mapping function as a Nw× rectangular matrix, the w mapping matrix, whose ( , )i j -th element, i=1,...,Nw, j=1,...,w, represents the value of M i
( (
−1)
w j+)
. In this way, constraint (3.1) translates into a constraint on the columns of such a matrix, while constraint (3.2) that depends on permutation π ,two sets:
Given an interleaverπ , the problem is to find a mapping matrix that satisfies (3.1) and (3.2). Here, we present an algorithm that gives the desired mapping matrix for any interleaver π. The algorithm can be described as below:
¾ First step: Any step that produces an initial mapping matrix with the following properties: every column and tile contains at most one element equal to every symbol in
{
1,...,Nw}
. Nevertheless, there are some elements which are not assigned yet, and we label these unassigned elements as ‘-’.¾ Second step: This step accepts the initial mapping matrix output in the first step and fills all blank elements. This procedure of completing the mapping matrix is called annealing. This result is a mapping matrix with all elements in
{
1,...,Nw}
, satisfying (3.1) and (3.2).To understand how the annealing algorithm works, it is better to give an example.
Example 1: Suppose L = 30, Nw= , 5 w= , and suppose the permutation 6 π, for
Thus, the column and tiling of the mapping matrix in this example can be shown in Figure 3.5(a), (b), respectively.
Figure 3.5 (a) The column (b) The tiling of the mapping matrix in this example
Where the two sets are according to (3.3) and (3.4), for example, the indices 28 and 9 of the tiling matrix are:
[ ]
Suppose the output of the first step is the following initial mapping matrix:4 1 2 2 2
Where the blanks in its (1,3) and (4,6) elements. The procedure of annealing starts from one of them, and we choose the (1,3) element and fill in the blank with the value that is not represented in its column yet, i.e., the value is 5. However, this change will cause a collision to happen, because (1,3) and (4,2) belong to the same tile E and both have the value 5. Owing to this reason, (4,2) is changed to the value 1 that is not represented in
⎞⎟
Now, there is a collision happened in column 2 (the value 2 appears two times), so (1,2) is changed to 5. However, this change will cause a collision due to (1,2) and (3,4) belong to the same tile B and both have the value 5. So (3,4) is changed to the value 1 that is not represented in its tile E yet, as:
4 1 2 2 2 4 5 2 2 2
Repeat the same procedure above mentioned all the while until no iterant number appears to the same tile and column. Hence, the final result is the following mapping matrix and one can verify that constraint (4.1) and (4.2) are all satisfied:
4 5 5 2 2 2
The annealing procedure can be decomposed into several cycles, each of them starting with a blank element, picked at random, and ending when no collisions are produced. After a cycle is ended, a new one starts if there are still blanks in the mapping matrix, otherwise, the annealing procedure is over. In the previous example, there are 4 cycles.