CHAPTER 2 SYSTEM ASSUMPTIONS
2.2 FD-CFO
2.2.2 The Proposed Algorithm of FD-CFO
If neither gain nor phase error exist, then SG remains at unity, and MG decreases to zero.
Significantly, the phase rotation is inversed in the direction between the original signals and its conjugate if the CFO is present. Hence, the conventional compensation algorithm, which simply multiplies the data by an exponential term, must be modified in accordance with the gain and phase errors. This work mainly focuses on extracting the CFO value with the IQ-M error.
2.2.2 The Proposed Algorithm of FD-CFO
The FD-CFO adopts three frequency responses of identical training symbols for frequency offset estimation. First, r n
( )
iq, r n(
+Ns iq)
and r n(
+2Ns iq)
are defined as three consecutive short preambles, which are distorted by CFO and IQ-M. Then, the short preambles are transform to FD by FFT. The original frequency offset and the pseudo-frequency offset are assumed to be positive in the following mathematical derivations.The three preambles are then rotated by the pseudo-frequency offset.
where Δθ denotes the pseudo-frequency offset. The extra P-CFO is used to resolve the
transformation error resulting from AWGN. Finally,
Consequently, the frequency offset can be computed from (2.2.10).
( )
The same method also indicates that
{ } { } { } { }
From (2.2.12), the estimated frequency offset can be expressed as
( )
Therefore, the estimated frequency offset can be averaged according to (2.2.11) and (2.2.13).
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Sensitive to noise Pseudo CFO Shifter
Quasi-linear region
Figure 2-5 Inverse cosine function
Figure 2-5 shows the inverse cosine (arccosine) function for real element of z in the domain [-1, 1]. This figure indicates that the arccosine value should be zero if the original CFO value is 0ppm. However, there is a disadvantage of the cosine estimator (cos−1
( )
z ). It issensitive to even a small amount of noise disturbance when z is relatively small. Therefore, the noise disturbance will have great effect on the CFO estimation and lead to transformation errors. The proposed method to solve this problem is to multiply the training sequence by an extra exponential term and get a larger CFO value. A larger CFO value prevents inverse cosine from being affected by noise disturbance and reduces the possibility of transformation errors accordingly.
(a)
(b)
Figure2-6 PDF of 50 ppm: (a)FD-CFO algorithm (b)Moose’s algorithm
The estimated frequency offset under IQ-M can be characterized by a Gaussian
16
probability density function (PDF), as shown in Figure 2-6(a) and (b). Figure 2-6(a) clearly shows that the mean of the proposed FD-CFO algorithm was close that of the original CFO.
However, the Moose’s algorithm, as shown in Figure 2-6(b), always had bias. These figures indicate that the proposed FD-CFO algorithm allows the correct CFO to be extracted under IQ-M conditions. Figure 2-7 shows the mean square error (MSE) of frequency estimation versus signal-to-noise ratio (SNR) under different IQ-M conditions. Figure 2-7 indicates that for almost the entire SNR range, the FD-CFO algorithm under the condition of 2-dB gain error and 20 phase error performed better than Moose’s and Stefaan’s algorithm [16], under the same condition or moderate IQ-M scenario, i.e., 1dB gain error and 10 phase error. The FD-CFO algorithm thus has better estimation accuracy under IQ-M than Moose’s and Stefaan’s algorithm. Since there are some approximations in the derivation, the MSE of the FD-CFO algorithm is slightly weaker than the Moose’s algorithm under ideal I/Q. Although Stefaan’s algorithm is constructed by a simple algebraic deduction and the estimation is independent of the IQ-M. That means the estimation results will not have variations no matter how severe the IQ-M is. As shown in Figure 2-7, the Stefaan’s MSE lines overlap in the upper of the figure. Unfortunately, the Stefaan’s algorithm is sensitive to the noise. So, the estimation error is much worse than FD-CFO under AWGN. TABLE 2-1 summarizes the required SNR when the MSE is on the order of 10-6.
0 5 10 15 20 25 30
Figure 2-7 Mean square error (MSE) of frequency estimation versus SNR under different IQ-M with 50 ppm CFO
TABLE2-1REQUIRED SNRFOR 10-4MSE Required SNR [dB]
IQ-M
FD-CFO Moose Stefaan
No IQ 7 6 30
Gain: 1 dB, phase: 10-degree 7 6 30
Gain: 2 dB, phase: 20-degree 8 >30 30
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Chapter 3
FD-BD Implementation
After a new short preamble point arrives and then be pushed into the FFT window to acquire the frequency response of short preamble. The frequency response will be multiplied with multiple patterns in restricted time. In order to catch up with the transmitted rate, multiple correlation banks are required. But the correlation bank cost too high to use excessively. So, that is trade-off between cost and performance. The compromising method is to use two correlation banks simultaneously and raise the system clock to 80 MHz. Therefore, the implementation can be done.
The input/output port definition of FD-BD is showed in Figure 3-1.FD-BD will take the frequency response of short preamble as the inputs and its outputs will be the estimated offset when complete the boundary detection.
Figure 3-1 Input/output port definition of FD-BD
Figure 3-2 illustrates the VLSI architecture of the FD-BD algorithm, where the FD-BD scheme includes four main parts: FFT data buffer, Metric computation, Sorter and Interactive sequence searcher. There are two colours in the figure. The darker grey represents that operates at higher clock rate (77 MHz for DSSS or 80 MHz for OFDM). The lighter one operates at system clock rate (11 MHz for DSSS or 20 MHz for OFDM). When the frequency responses of training symbols are arrived, the Metric computation module is awakened to work. The task of Metric computation module is to compute the cross-correlation values between received training symbols and pre-stored frequency response of training symbol and its shift. In Figure 3-2, 4 ROMs are the role of lookup table to provide inputs of cross-correlations. When the computation is finished by the Metric computation module, Sorter module starts to sort the value of cross-correlation. As shown in Figure 3-2, inserter insert 2 values to sorted buffer each time until complete the sorting. After Sorter, the sorted values are sent to Interactive sequence searcher module. The task of Interactive sequence searcher module is to store candidates from sorted buffer and pass the candidates to
20
Memory module. Then, finger out where the symbol boundary is by Trellis rule checker module. Finally, the most frequency offset is the final boundary offset. The synthesis result of FD-BD is listed in TABLE 3-1 and the system clock rates are 11MHz for DSSS and 20MHz for OFDM in 0.18μm 1P6M CMOS, respectively. Summary is listed in TABLE 3-2. System parameters are listed in TABLE 3-3.
ROM2 Cross-correlator1max
2nd3rd
4th
5th
6th
7thmin State Transition rule checker
Length counter Memory module FFT data buffer
1st2nd10th Search Length = 5Cross-correlator2 max
2nd
3rd4th
5th
6th
7th Rt(0)Rt(1)Rt(2)Rt(3)
Rt(L-1)SortedBuffer CandidatesBuffer Multi-mode control unit
ROM1
ROM4ROM3
SorterInteractive sequence seacher Metric computation
Clock controller 77 MHz for DSSS80 MHz for OFDM11 MHz for DSSS, 20 MHz for OFDM
( )
,tkΦRPk ( )
,tkΦRPk
Conf.Figure 3-2 VLSI architecture of FD-BD
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TABLE3-1SYNTHESIS RESULT OF FD-BD
Module Gates Percentage
Cross-correlation 230587 90.0%
Sorter 20631 8.1%
Iterative Sequence Search 4729 1.8%
Other(Control Units & Buffers) 130 0.1%
Total 256078 100%
TABLE3-2SUMMARY OF FD-BD Technology 0.18-μm 1P6M CMOS
Gate Count 256 K
System Clock 80 MHz
Core Power 40.2 mW
TABLE3-3SYSTEM PARAMETER
Value Parameters
DSSS SISO-OFDM MIMO-OFDM
Preamble type (# of chips) ±barker code
Chapter 4
FD-CFO Implementation
Figure 4-1 shows the input/output port definition of FD-CFO. FD-CFO will take the frequency response of short preamble as the inputs and its outputs will be the estimated CFO when complete the CFO estimation.
Figure 4-1 Input/output port definition of FD-CFO
Figure 4-2 is the VLSI architecture of FD-CFO. The FD-CFO contains three main parts:
P-CFO shifter, CFO calculation and inverse cosine. The P-CFO shifter module begins to operate when the frequency responses of training symbols are arrival. The P-CFO shifter
24
module rotates the received frequency response of short preambles by the pseudo-frequency offset. As shown in Figure 4-2, the rotation is achieved by a look-up table and a complex multiplier. After the rotation is finished by the P-CFO shifter module, CFO calculation module begins to do estimation based on the FD-CFO algorithm. When the estimation of CFO is completed, the CFO calculation module sent its output to inverse cosine module. The assignment of inverse cosine module is to find the angle of the correction calculated from CFO calculation module, and then add/minus the pseudo frequency offset to extract the final CFO. The FD-BD is implemented via 0.18-μm CMOS library, which occupies approximately 49K gate count. The synthesis result of FD-CFO and summary of FD-CFP are listed in TABLE 4-1 and TABLE 4-2, respectively.
Trun catio n Trun catio n Trun catio n
θ−ΔθΔ fΔ
Figure 4-2 VLSI architecture of FD-CFO
26
TABLE4-1SYNTHESIS RESULT OF FD-CFO Combinational area 298984.000000 Noncombinational area 146828.937500 Total cell area 445800.812500
TABLE4-2SUMMARY OF FD-CFO Technology 0.18-μm 1P6M CMOS
Gate count 49 K
System clock 20 MHz
Chapter 5
Conclusion and Future Work
5.1 Conclusion
This work implements two synchronization algorithms in FD. The FD-BD adopts the MLSE-based iterative sequence search to find the offset in the symbols. Simulations results indicate the error rate is less than 1% in low-SNR environments. The results also hint that the SNR loss does not increase significantly even with the CFO is up to 100 ppm. Consequently, the FD-BD supporting DSSS and OFDM modes is implemented using an 0.18-μm 1P6M CMOS library. Although requires two correlation banks to keep up with the transmitted rate.
However, the correlation function is often used in the synchronizer. After the operation of FD-BD, the correlation banks can be reused by other modules.
In addition, this thesis implements the FD-CFO which transfer the operation based on P-CFO from TD to FD. The performance of FD-CFO is comparable with P-CFO under I/Q mismatch. The FD-CFO can adopt three training symbols to estimate the frequency offset from -50 ppm to 50 ppm under 2.4 GHz carrier frequency with 2dB gain error and 20-degree phase error in multipath environments. Simulation results indicate that the average estimation error of the proposed FD-CFO algorithm can fulfil many system requirements, preventing obvious performance loss under different I/Q mismatch conditions.
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5.2 Future Work
In IEEE802.11n, the standard is formulated the cyclic shift format of the short preambles in different antennas that are used to prevent unintentional beam-forming when the same signal or scalar multiples of one signal are transmitted through different spatial; streams or transmit chains. Cyclic shift means that every antenna transfers short preambles with different displacements contrast with original short preamble. Unfortunately, the cyclic shift will cause the correlation value of adjacent training symbols decreasing and then degrade FD-CFO performance. Simulation results show that there is 2dB degradation at least.
Furthermore, the continuous wave jamming (CW jamming) which is a kind of narrow band interference (NBI) can severely drop the performance of proposed algorithm and destroy the transmitted signal.
So some extensions to the research presented in this thesis will be included in out future work. In the future, the work is to improve the performance at low-SNR environments. The performance of FD-CFO should be ensured that will not be degraded under cyclic shift.
Finally, increase the ability of resistance under CW jamming.
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