Table 5.2: Comparison with prior works [5, 12, 1] on temperature mitigation tech-niques on maximum temperature (Tmax) and maximum temperature difference be-tween adjacent bins (δTS)
Original Chu et. al. [5] Liu et. al. [12] Aroonsantidecha et. al. [1] Our
GP/DP - DP DP GP DP
benchmarks Cell# Tmax δTS Tmax δTS Tmax δTS Tmax δTS Tmax δTS
adaptec1 211K 63.95 1.02 47.79 0.05 62.87 1.03 60.21 0.98 57.04 0.84 adaptec2 255K 50.44 1.04 35.92 0.09 49.88 1.01 50.45 1.01 48.40 0.94 adaptec3 452K 46.14 1.25 33.11 0.16 45.59 1.25 44.01 1.34 43.71 1.22 adaptec4 496K 46.57 1.25 33.91 0.15 46.24 1.24 45.18 1.22 45.26 1.25 bigblue1 278K 73.54 1.12 51.23 0.06 72.05 1.11 70.77 1.09 67.06 0.98 bigblue2 558K 52.09 1.05 41.04 0.11 51.79 1.05 51.03 1.02 50.59 1.01 bigblue3 1110K 73.79 2.92 39.98 0.42 71.86 2.95 65.46 2.84 64.16 2.60 bigblue4 2180K 75.35 3.01 45.41 0.30 75.05 3.01 72.37 2.98 66.16 2.72 Norm. - 1.078 1.093 0.744 0.101 1.068 1.089 1.035 1.077 1.000 1.000
Binaries from [4, 10] can not be obtained due to various reasons. Request for binary in [13] is unanswered. To make a fair comparison with [1]. Experiment is performed using legalized placement results without thermal consideration from [1]. Post-Placement temperature mitigation techniques based on matrix synthesis proposed in [5] and empty row insertion proposed in [12] are re-implemented to the very best of our understanding.
Fig. 5.1 is an illustration of temeprature distribution before and after optimiza-tion. We adopted mitigation technique as our idea to spread the hot region and
re-(a) Before Temperature Mitigation (b) After temperature mitigation
(c) Before temperature mitigation (d) After temperature mitigation
Figure 5.1: Temperature distribution before and after temperature mitigation. (a)-(b) is the benchmark of adaptec1, (c)-(d) is the benchmark of bigblue3.
bin. In Fig. 5.1, the temperature distribution is more alleviative after optimization.
In our work, we use the network algorithm method to alleviate temperature at post placement stage. In this regard, we demonstrate the relationship of the network dimension between temperature and displacement. The variation between temperature and displacement change a lot when network dimension increase in Fig. 5.2. Rn denote the number of times to find the hot region, and In denote the iteration number of optimization. Due to the consideration runtime, the number of Rn is set to 5, and the network dimensions are to 3 × 3 and 5 × 5. Fig. 5.3 is an illustration of In relation between temperature and displacement. When In rises to a certain extent, it will gradually converge together, and the value of In is 10 to 30
(a) Comparing with different network dimension for Adaptec3
(b) Comparing with different network dimension for Bigblue3
Figure 5.2: The relation of temperature and displacement by comparing the different network dimension(3×3, 5×5 and 7×7). (a) Rn=5, 0.1<= γ <=0.9, In=15. (b) Rn=5, 0.1<= γ <=0.9, In=30.
for each benchmarks.
Table 5.2 compares result of proposed technique with prior works on thermal aware placement. Original placed results are obtained from [1]. In implementation of [5], t is set to 2 and total bin number is set to 128 × 128. In implementation of [12], row insertion is achieved by shifting cells upward/downward since proposed technique does not consider the presence of hard macros. Row insertion number ranges from 20 to 66 depend on size of hot spot.
(a) The effect of the increase of iteration number on Adaptec3
(b) The effect of the increase of iteration number on Bigblue3
Figure 5.3: The curve will converge when the iteration number is rising for adaptec3.
(a) Rn=5, network dimension=5×5, γ=0.3, 1<= In <=50 increase by 5 unit. (b) Rn=5, network dimension=5×5, γ=0.4, 1<= In <=50 increase by 5 unit.
In Table 5.2, our proposed network based technique can significantly decrease maximum temperature difference δTS by 9.3% compared to our placer which is similar to simPL. Fig. 5.1 is the temperature distribution before and after our technique is conducted. Techniques proposed in [5] achieves best temperature re-duction by redistributing power across entire chip, however, such greedy approach also significantly increase displacement and leads to failure during legalization on all 8 testcases. Nevertheless, result from [5] offers an indication to the upper bound of temperature reduction.
Table 5.3: Comparison with Prior Works [5, 12, 1] on Total Displacement After Legalization
[5] [12] [1] Our
benchmarks Cell# Dis. Dis. Dis. Dis.
adaptec1 211K LG Fail 1.34 32.57 15.34 adaptec2 255K LG Fail 0.28 48.43 4.92 adaptec3 452K LG Fail 1.17 109.95 9.59 adaptec4 496K LG Fail 1.45 91.57 6.64 bigblue1 278K LG Fail 0.93 59.30 12.93 bigblue2 558K LG Fail 0.82 41.87 8.81 bigblue3 1110K LG Fail 2.72 277.78 58.30 bigblue4 2180K LG Fail 1.53 307.82 67.29
Norm. - - 0.075 5.948 1.000
We also compare our result with [1] which is performed at global placement stage.
It should be noted that techniques performed at global placement stage have more control to placement topology but heavily relied on placer. In contrast, techniques performed at post-placement stage are limited to given placement but offered more flexibility in integration with other optimizations. In comparison with [1], our pro-posed framework have 7.7% less δTS, 3.5% less maximum temperature with 494.8%
less in displacement. Experimental result in Table 5.3 shows that [12] may not be suitable in designs with high percentage of hard macros (e.g. adaptec3,adapatec4).
Chapter 6 Conclusion
In this thesis, a framework that tightly integrates analytical temperature profil-ing with network flow based power density mitigation technique is proposed. By modeling regional power density balancing problem as supply-demand problem, temperature profile can be effectively smoothed out with minimal increase to to-tal displacement. Regional movement of power density at global scale is inevitable to reduce maximum on chip temperature, rather than optimizing each bin sepa-rately, we cluster bin and optimize power density in regions. Implementation at post-placement stage also offers much more flexibility to integrate with other opti-mizations.
Bibliography
[1] S. Aroonsantidecha, S. S.-Y. Liu, C.-Y. Chin, and H.-M. Chen. A Fast Thermal Aware Placement with Accurate Thermal Analysis Based on Green Function.
In Asia and South Pacific Design Automation Conference, 2012.
[2] U. Brenner. Vlsi legalization with minimum perturbation by iterative augmen-tation. In Design, Automation Test in Europe Conference Exhibition, pages 1385 –1390, 2012.
[3] S. Chaudhury. A Tutorial and Survey on Thermal-Aware VLSI Design: Tools and Techniques. 2009.
[4] G. Chen and S. Sapatnekar. Partition-Driven Standard Cell Thermal Place-ment. In International Symposium on Physical Design, pages 75–80, 2003.
[5] C. C. N. Chu and M. D. F. Wong. A Matrix Synthesis Approach to Thermal Placement. In International Symposium on Physical Design, pages 163–168, 1997.
[6] J. Cong, J. Wei, and Y. Zhang. A Thermal-Driven Floorplanning Algorithm for 3D ICs. In International Conference on Computer Aided Design, pages 306–313, 2004.
[7] P. Ghosal and P. Dasgupta. Thermal Aware Placement in 3D ICs. In Advances in Recent Technologies in Communication and Computing, 2010.
[8] B. Goplen and S. Sapatnekar. Efficient thermal placement of standard cells in 3d ics using a force directed approach. In Computer Aided Design, 2003.
ICCAD-2003. International Conference on, pages 86 – 89, 2003.
[9] P.-Y. Huang and Y.-M. Lee. Full-Chip Thermal Analysis for the Early Design Stage via Generalized Integral Transforms. In Transaction on Very Large Scale Integration System, volume 17, pages 613–626, May 2009.
[10] A. B. Kahng, S. mo Kang, W. Li, and B. Liu. Analytical Thermal Place-ment for VLSI Lifetime ImprovePlace-ment and Minimum Performance Variation. In International Conference on Computer Design, pages 71–77, 2007.
[11] J. Li and H. Miyashita. Thermal-Aware Placement Based on FM Partition Scheme and Force-Directed Heuristic. Transaction on Fundamental Electronic Communication Computeter Science, pages 989–995, April 2006.
[12] W. Liu, A. Nannarelli, A. Calimera, E. Macii, and M. Poncino. Post-Placement Temperature Reduction Techniques. In Design Automation Test in Europe Conference, 2010.
[13] B. Obermeier and F. M. Johannes. Temperature-Aware Global Placement. In Asia and South Pacific Design Automation Conference, pages 143–148, 2004.
[14] M. Pan, N. Viswanathan, and C. C. N. Chu. An Efficient and Effective Detailed Placement Algorithm. In International Conference on Computer Aided Design, pages 48–55, 2005.
[15] H. R. Prasun Ghosal and P. Dasgupta. Minimizing Thermal Disparities During Placement in 3D ICs. In Computational Science and Engineering, 2010.
[16] C. H. Tsai and S. M. Kang. Cell-Level Placement for Improving Substrate Thermal Distribution. In IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems, volume 19, pages 253–266, Feb. 2000.
[17] J.-L. Tsai, C.-P. Chen, G. Chen, B. Goplen, H. Qian, Y. Zhan, S.-M. Kang, M. Wong, and S. Sapatnekar. Temperature-Aware Placement for SOCs. Pro-ceedings of the IEEE, 94(8):1502–1518, Aug. 2006.
[18] B. Wang and P. Mazumder. Accelerated Chip-Level Thermal Analysis Using Multilayer Green’s Function. In IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, volume 26, pages 325–344, Feb. 2007.
[19] Y. Zhan and S. S. Sapatnekar. High Efficiency Green Function-Based Thermal Simulation Algorithms. In IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems, volume 26, pages 1661–1675, Sept. 2007.