TSV utilization issue

Fig. 41(a) shows the areas of BSL and the four representative patterns of each architecture, IS20=SP(20, 1), ES2=SP(32, 2), SP(20, 2), SE(32, 2, 0.6, 8, 2), in which all values are normalized to BSL and Fig. 41(b) shows the corresponding average TSV utilization of these patterns. Initially, the TSV utilization of BSL is extremely low (<10%). After reducing the redundant TSVs by IS, ES, SP and SE, the TSV utilization increases but it is still low (≦30%) even with 52% area reduction at most. The main reason is that the dimension of a FPGA under a given layer is fixed regardless of the sizes of test cases. The problem arises when a small test case is put into a large capacity FPGA, lots of TSVs will be left unused and thus it decreases the overall TSV utilization. As a matter of fact, the TSV

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utilization from a single case clma under SE(32, 2, 0.6, 8, 2) in Fig. 41(b), which achieves 50% at most, is not as low as the utilization of overall average.

(a)

(b)

Fig. 41. The (a)normalized areas/(b)TSV utilizations among different patterns.

Chapter 6 Conclusion

In this thesis, we first show that the utilization of TSVs is extremely low (<

10%) in the baseline architecture (BSL) where all SBs are fully connected 3D-SBs.

Then we present two architectures for area (TSV) reduction: the internally-sparse (IS) architecture through reducing the number of TSVs in each 3D-SB, and the externally-sparse (ES) architecture through reducing the number of available 3D-SBs. In combination of IS and ES, we further develop the hybrid sparse architecture (SP). In the end, we propose the ultimate sunny egg (SE) architecture, which incorporates two different SP architectures with different TSV densities in the central and peripheral region respectively.

After extensive evaluations over all architecture styles, two generic 3D FPGA architectures are most recommended; that is, SP(20, 2) and SE(32, 2, 0.6, 8, 2), which maximize the area reduction (up to 52%) with an acceptable delay penalty (< 3%). Therefore, we believe that all the ideas and architecture styles revealed in this thesis can serve as a robust foundation for developing even more practical 3D FPGA architectures.

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