Voltage Control Oscillator (VCO)

The building blocks of the VCO include a four stages ring oscillator and a self-biased replica-feedback bias generator. Fig 3-10 and Fig 3-11 shows the schematic of the four stages VCO and the delay cell.

Figure 3-10 Schematic of the four stages VCO

Figure 3-11 Schematic of VCO delay cell with symmetric load elements

The voltage control oscillator is critical and sensitive block in the PLL system. In order to have the low jitter characteristic performance of the output clock signal. In the mixed mode circuit, the delay buffer used in the section should have the low

sensitivity to the noise of the supply and substrate voltage. Therefore, the basic building block of the VCO used in this thesis is based on the differential delay stages with symmetric loads[21]. I-V curve of the delay stage with symmetric load is shown as Fig 3-12[22]. Although the I-V curve is nonlinear but is symmetrical to the center of the output voltage swing, and the delay stage has high noise immunity.

Figure 3-12 The symmetric load I-V curve

Based on the scheme as shown as Fig 3-11, the effective resistance of the symmetric load, is directly proportion to the small signal resistance at the end of the swing range that is one over the transconductance (gm) for one of the two equally sized devices when biased at control voltage. Thus, the delay per stage can be expressed by the equation:

where Ceff is the effective delay cell output capacitance, Reff is the effective resistance of delay cell. The drain current for one of the two equally sized devices at Vctrl is given by

]2

) 2[(Vdd Vctrl Vtp

I_d = k − − (3-2)

where k is the device transconductance of the PMOS device. Taking the derivative with respect to (Vdd-Vctrl), the transconductance is given by

] )

[(Vdd Vctrl Vtp k

gm= − − (3-3)

Combining (3-1) with(3-3), the delay of each stage can be written as

Vtp

The period of a ring oscillator with N delay stages is approximately 2N times the delay per stage. This translates to a center frequency of

eff

The gain of the VCO is defined as the absolute value of the slope on the frequency-Vctrl curve. Thus, Kvco can be expressed as

vco

vco f

K Vctrl

= ∂

∂ (3-6)

As a result, the center frequency of the VCO is in direct proportion to (Vdd-Vctrl) and has no relationship to supply voltage. is independent of buffer bias current and the VCO has the first order linearity.

Kvco

Figure 3-12 Replica-feedback current source bias circuit

The VCO bias generator providing the bias voltage Vbn and Vbp is shown as Fig3-12. It is composed of an amplifier bias, a differential amplifier, a half-buffer replica and a control voltage buffer. The task of the framework is to adjust the bias buffer current and provide the correct Vctrl with lower swing limit for the buffer stage.

In order to accomplish the target, the differential amplifier and the half-buffer replica form a negative feedback, and the voltage Vx equals the voltage Vctrl so that the output swings vary with the control voltage rather than is fixed. In order to track all variations at frequency for the PLL design, the bandwidth of the bias generator is typically set at least equal to the center frequency of the delay stages.

The bias generator also provides a buffered version of Vctrl at the Vbp output using an additional half-buffer replica. This output isolates the Vctrl from the potential capacitance coupling in the buffer stages. There is an important issue. The noticeable the supply-independent bias exists on the “degeneration” bias point. If all the transistors carry no current at beginning, they may remain indefinitely while the supply turning on. The reason is that the loop can get balance when all devices carry

no current. Therefore, an additional start-up circuit is necessary to propel the loop circuit out of the degenerate bias point.

Figure 3-13 Schematic of differential-to-single-ended converter

The differential-to-single-ended converter is shown in Fig 3-13. It consists of two opposite phase NMOS differential amplifier driving two PMOS common-source amplifier connected by NMOS current mirror. The first level NMOS differential amplifier amplifies the input differential-small signal to drive the next level PMOS amplifier and a single-ended full-swing signal is generated. The two differential amplifiers use the same current source bias voltage, Vbn, generated by the self-biased generator for the VCO. According to Vbn, the circuit corrects the input common-mode voltage level and provides signal amplification. The inverters are added at the output to improve the driving ability.

The duty-cycle corrector is connected behind the differential-to-single-ended converter to ensure that the duty-cycle of the VCO will be 50% and shown as Fig3-14[23]. This duty-cycle correction circuit consists of only two transmission

gates and two inverters, the area is minimal and the power consumption is negligible.

The signal Vin+ selected from the multiphase signals turn on M3 and M4, and charges the output node Vout of the duty-cycle corrector almost instantaneously. Because the discharge path of the node Vin+ is already off due to the signal Vin-. The signal Vin-, which is also selected from the multiphase signals, is the one whose rising edge is shifted by 180° in phase from that of Vin+. Similarly, the signal Vin- rapidly discharges the node Vout and delivers the desired 50% duty-cycle signal. The advantage of duty-cycle corrector can apply to many aspects in this thesis, that will be described in the later section.

Figure 3-14 Schematic of duty-cycle corrector and its timing diagram