The evolution of the instruction set can be seen in the registers of the 80x86 (Figure K.30). Original registers are shown in black type, with the extensions of the 80386 shown in a lighter shade, a coloring scheme followed in subsequent fig-ures. The 80386 basically extended all 16-bit registers (except the segment regis-ters) to 32 bits, prefixing an“E” to their name to indicate the 32-bit version. The arithmetic, logical, and data transfer instructions are two-operand instructions that allow the combinations shown in Figure K.31.
To explain the addressing modes, we need to keep in mind whether we are talk-ing about the 16-bit mode used by both the 8086 and 80286 or the 32-bit mode available on the 80386 and its successors. The seven data memory addressing modes supported are
■ Absolute
■ Register indirect
■ Based
■ Indexed
■ Based indexed with displacement
■ Based with scaled indexed
■ Based with scaled indexed and displacement
FPR 0 FPR 1 FPR 2 FPR 3 FPR 4 FPR 5 FPR 6 FPR 7
0 79
0 15
0 15
8 7 31
GPR 0 EAX AX AH AL Accumulator
GPR 3 EBX BX BH BL Base addr. reg
GPR 1 ECX CX CH CL Count reg: string, loop
GPR 2 EDX DX DH DL Data reg: multiply, divide
GPR 6 ESI SI Index reg, string source ptr.
Code segment ptr.
CS
Stack segment ptr. (top of stack) SS
Data segment ptr.
DS
Extra data segment ptr.
ES
Data segment ptr. 2 FS
Data segment ptr. 3 GS
GPR 7 EDI DI Index reg, string dest. ptr.
GPR 5 EBP BP Base ptr. (for base of stack seg.)
PC
GPR 4 ESP SP Stack ptr.
EIP IP Instruction ptr. (PC)
EFLAGS FLAGS Condition codes
Top of FP stack, FP condition codes Status
80x86, 80x286 80x386, 80x486, Pentium
Figure K.30 The 80x86 has evolved over time, and so has its register set. The original set is shown in black and the extended set in gray. The 8086 divided the first four registers in half so that they could be used either as one 16-bit register or as two 8-bit registers. Starting with the 80386, the top eight registers were extended to 32 bits and could also be used as general-purpose registers. The floating-point registers on the bottom are 80 bits wide, and although they look like regular registers they are not. They implement a stack, with the top of stack pointed to by the status register. One operand must be the top of stack, and the other can be any of the other seven registers below the top of stack.
Displacements can be 8 or 32 bits in 32-bit mode, and 8 or 16 bits in 16-bit mode.
If we count the size of the address as a separate addressing mode, the total is 11 addressing modes.
Although a memory operand can use any addressing mode, there are restric-tions on what registers can be used in a mode. The section “80x86 Instruction Encoding” on page K-11 gives the full set of restrictions on registers, but the fol-lowing description of addressing modes gives the basic register options:
■ Absolute—With 16-bit or 32-bit displacement, depending on the mode.
■ Register indirect—BX, SI, DI in 16-bit mode and EAX, ECX, EDX, EBX, ESI, and EDI in 32-bit mode.
■ Based mode with 8-bit or 16-bit/32-bit displacement—BP, BX, SI, and DI in 16-bit mode and EAX, ECX, EDX, EBX, ESI, and EDI in 32-bit mode.
The displacement is either 8 bits or the size of the address mode: 16 or 32 bits.
(Intel gives two different names to this single addressing mode, based and indexed, but they are essentially identical and we combine them. This book uses indexed addressing to mean something different, explained next.)
■ Indexed—The address is the sum of two registers. The allowable combinations are BX+SI, BX+DI, BP+SI, and BP+DI. This mode is called based indexed on the 8086. (The 32-bit mode uses a different addressing mode to get the same effect.)
■ Based indexed with 8- or 16-bit displacement—The address is the sum of dis-placement and contents of two registers. The same restrictions on registers apply as in indexed mode.
■ Base plus scaled indexed—This addressing mode and the next were added in the 80386 and are only available in 32-bit mode. The address calculation is
Base register + 2Scale Index register
Source/destination operand type Second source operand r
e t s i g e R
e t a i d e m m I
y r o m e M
r e t s i g e R
e t a i d e m m I r
e t s i g e R
r e t s i g e R
r e t s i g e R
y r o m e M
y r o m e M
Figure K.31 Instruction types for the arithmetic, logical, and data transfer instruc-tions. The 80x86 allows the combinations shown. The only restriction is the absence of a memory-memory mode. Immediates may be 8, 16, or 32 bits in length; a register is any one of the 14 major registers in Figure K.30 (not IP or FLAGS).
where Scale has the value 0, 1, 2, or 3; Index register can be any of the eight 32-bit general registers except ESP; and Base register can be any of the eight 32-bit general registers.
■ Base plus scaled index with 8- or 32-bit displacement—The address is the sum of the displacement and the address calculated by the scaled mode immediately above. The same restrictions on registers apply.
The 80x86 uses Little Endian addressing.
Ideally, we would refer discussion of 80x86 logical and physical addresses to Chapter 2, but the segmented address space prevents us from hiding that infor-mation. Figure K.32 shows the memory mapping options on the generations of 80x86 machines; Chapter 2 describes the segmented protection scheme in greater detail.
The assembly language programmer clearly must specify which segment reg-ister should be used with an address, no matter which address mode is used. To save space in the instructions, segment registers are selected automatically depend-ing on which address register is used. The rules are simple: References to instruc-tions (IP) use the code segment register (CS), references to the stack (BP or SP) use the stack segment register (SS), and the default segment register for the other registers is the data segment register (DS). The next section explains how they can be overridden.