Random-Dopant-Induced Variability in Nano-CMOS
Devices and Digital Circuits
Yiming Li, Member, IEEE, Chih-Hong Hwang, and Tien-Yeh Li
Abstract—The impact of the number and position of
dis-crete dopants on device characteristics is crucial in determining the transient behavior of nanoscale circuits. An experimentally validated coupled device-circuit simulation was conducted to in-vestigate the discrete-dopant-induced timing-characteristic fluc-tuations in 16-nm-gate CMOS circuits. The random-doping effect may induce 18.9% gate-capacitance fluctuation, affecting the intrinsic device gate delay and circuit timing. For a 16-nm-gate CMOS inverter, 0.036-, 0.021-, 0.105-, and 0.108-ps fluctuations in rise time, fall time, low-to-high delay time, and high-to-low delay time are found. The timing fluctuations ofNANDandNORcircuits are increased, as the number of transistors increased. Because of the same number of transistors in circuits, the timing fluctuation ofNANDandNORare expected to be similar. However, due to the different function and device operation status of circuit, the timing fluctuation is quite different. The function- and circuit-topology-dependent characteristic fluctuations caused by random nature of discrete dopants are found. This paper provides an insight into random-dopant-induced intrinsic timing fluctuations, which can, in turn, be used to optimize nanoscale MOS field-effect-transistor circuits.
Index Terms—Characteristic fluctuation, modeling and
simula-tion, nanoscale digital IC, random-dopant effect, timing.
I. INTRODUCTION
S
ILICON-BASED devices are scaled down continually to increase density and speed. The gate lengths of scaled MOSFETs are under 30 nm in 45-nm-node high-performance circuit design [1]. Devices with sub-10-nm gate lengths have recently been studied [2], [3]. For state-of-the-art nanoscale circuits and systems, the local device variation and uncertainty of signal-propagation time have become crucial in the varia-tion of system timing and the determinavaria-tion of clock speed. Yield analysis and optimization, which take into account the manufacturing tolerances, model uncertainties, variations in the process parameters, and other factors are known as indispens-able components of the circuit-design procedure [4]–[10].Manuscript received March 11, 2009; revised April 24, 2009. First published June 26, 2009; current version published July 22, 2009. This work was supported in part by Taiwan National Science Council (NSC) under Contracts NSC-97-2221-E-009-154-MY2 and NSC-96-2221-E-009-210 and in part by a 2007–2009 grant from Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan. The review of this paper was arranged by Editor V. R. Rao.
Y. Li is with the Department of Communication Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, and also with the National Nano Device Laboratories, Hsinchu 300, Taiwan (e-mail: [email protected]).
C.-H. Hwang and T.-Y. Li are with the Parallel and Scientific Computing Laboratory, Department of Communication Engineering, National Chiao Tung University, Hsinchu 300, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2009.2022692
The intrinsic device parameter fluctuations that result from line edge roughness [11], [12], the granularity of the polysil-icon gate [13]–[15], and random discrete dopant [15]–[42] effects have substantially affected the device characteristics. With device scaling, various randomness effects resulting from the random nature of manufacturing process have induced significant fluctuations of electrical characteristics in nanoscale MOSFETs. The number of dopants is on the order of tens in the depletion region in a nanoscale MOSFET, whose influence on device characteristic is large enough to be distinct. Various random-dopant effects have been recently studied in both ex-perimental and theoretical approaches [15]–[42]. Fluctuations of characteristics are caused not only by a variation in an average doping density, which is associated with a fluctua-tion in the number of impurities, but also with a particular random distribution of impurities in the channel region. The randomness of the dopant position and number in device makes the fluctuation of device characteristics difficult to model and mitigate. Diverse approaches have recently been presented to investigate fluctuation-related issues in semiconductor devices [15]–[35] and circuits [36]–[42]. However, less attention has been paid to timing-characteristic fluctuations of active devices caused by random dopants. Additionally, the randomness of dopant positions in devices makes the fluctuation of the gate capacitance of a device nonlinear and difficult to model using present compact models [34].
Thus, this paper presents a large-scale statistically sound coupled device-circuit simulation approach to analyze the random-dopant effect in nanoscale CMOS circuits, concur-rently capturing the fluctuations associated with the number and the positions of discrete dopants. Based on the statistically generated large-scale doping profiles, device simulation is performed by solving a set of 3-D drift-diffusion equations with quantum corrections by the density-gradient method [43]–[51], which is performed using a parallel-computing system [52]–[54]. The density-gradient approximation [43]– [51] is used to smooth the singularities of the Coulomb potential [25], [26], [31] by properly introducing the related quantum–mechanical effects. To pursue high accuracy of timing fluctuation [55], a coupled device-circuit simulation [42], [55]–[58] with discrete dopant distribution is conducted to examine the associated timing behavior of the circuit. The characteristic fluctuation of the device was validated with reference to the experimentally measured data [32] to ensure the best accuracy. The results of this paper elucidate the random-dopant fluctuations in circuit timing and discuss the function- and circuit-topology-dependent characteristic fluctuations.
This paper is organized as follows. Section II introduces the simulation technique for studying the effect of random dopant in nanoscale devices and circuits. Section III studies the characteristic fluctuations in 16-nm devices and circuits. Finally, conclusions are drawn and future work is suggested.
II. NANO-MOSFET CIRCUIT AND SIMULATIONTECHNIQUE
The nominal channel doping concentration of the explored device is 1.48× 1018 cm−3. They have a 16-nm gate, a gate oxide thickness of 1.2 nm, and a work function of 4.4 eV. The source/drain and background doping concentrations are 1.1× 1020and 1× 1015cm−3, respectively. To study the effect of random fluctuations in the number and position of discrete dopants in the channel region, 758 dopants are randomly gen-erated in an (80 nm)3 cube, yielding an equivalent doping
concentration of 1.48× 1018 cm−3, as shown in Fig. 1(a). The (80 nm)3 cube is then partitioned into 125 subcubes of
(16 nm)3. The number of dopants varies from 0 to 14, and
the average number is 6, as shown in Fig. 1(b)–(d). These 125 subcubes are then mapped into the channel region of the device for the 3-D “atomistic” device simulation includ-ing discrete dopants, as shown in Fig. 1(e). The device is simulated by solving a set of 3-D density-gradient equations coupled with Poisson equation and electron–hole current con-tinuity equations [28]–[30], [32], [33], [42], [49]. A step func-tion NA is used to define the concentration and positions of
dopants NA= k i=0 NAdopant· [H(x − xl, y− yl, z− zl) −H(x − xu, y− yu, z− zu)] (1) where H(x, y, z) = 1, x≥ 0, y ≥ 0, z ≥ 0 0, otherwise. (2)
(xl, yl, zl) and (xu, yu, zu) are the lower and upper
coor-dinates of a discrete dopant, respectively; k is the number of dopants in the device channel; NAdopant is the associated doping concentration for a dopant within a box. Then, NA
is substituted into the source of the Poisson equation and solved with the electron–hole current continuity equations and density-gradient quantum-correction equations simultaneously for device characteristics. In “atomistic” device simulation, the resolution of individual charges within a conventional drift-diffusion simulation using a fine mesh creates problems asso-ciated with singularities in the Coulomb potential [25], [26], [31]. The potential becomes too steep with fine mesh, and therefore, the majority carriers are unphysically trapped by ionized impurities, and the mobile carrier density is reduced [25], [26], [31]. Thus, the density-gradient approximation is used to handle discrete charges by properly introducing the related quantum–mechanical effects [43]–[51]. Note that 3-D Monte Carlo device simulations with ab initio impurities
scat-Fig. 1. (a) Discrete dopants randomly distributed in the (80 nm)3cube with
the average concentration of 1.48× 1018 cm−3. (b)–(d) There will be 758
dopants within the cube, but dopants may vary from 0 to 14 (the average number is 6) within its 125 subcubes of (16 nm)3. The 125 subcubes are equivalently
mapped into the channel region for dopant-position/number-sensitive device simulation. The inverter,NAND, andNORcircuits, displayed in (f)–(h), are used as test circuits to study the fluctuation of timing characteristics. (e)–(i) Inverter,
NAND, andNORgates are used as test circuits for timing-variation estimation. A coupled device-circuit simulation is then conducted for circuit characteristic fluctuations.
tering [27], [35] will provide more rich physical insights and accurate estimations.
The inverter,NAND, andNORcircuits, shown in Fig. 1(f)–(h), are used as test circuits to study the fluctuation of timing characteristics. Similarly, 125 cases of PMOSFETs with discrete dopants are generated, as shown in Fig. 1(a)–(d). Then, 125 pairs of NMOSFETs and PMOSFETs are randomly selected and used to study the circuit characteristic fluctuations. To compare fairly the NMOSFET- and PMOSFET-induced
characteristic fluctuation and eliminate the effect of transistor size on fluctuation, the dimensions of the PMOSFET were the same as those of the NMOSFET, and the absolute value of the nominal threshold voltages for both the NMOSFET and PMOSFET were both 140 mV. All statistically generated devices and circuits with discrete dopants, shown in Fig. 1, are incorporated into the large-scale 3-D coupled device-circuit simulation which is performed using a parallel-computing system [52]–[54]. In estimating circuit characteristics, since no well-established compact model of ultrasmall nanoscale devices is available, to capture the discrete-dopant-position-induced fluctuations, a device-circuit coupled simulation approach [42], [55]–[58]. The nodal equations of the test circuit are formulated and then directly coupled to the device transport equations (in the form of a large matrix that contains both circuit and device equations), which are solved simultaneously to obtain the circuit characteristics. The device characteristics, such as potential and current density, obtained by device simulation are input in the circuit simulation through circuit nodal equations. The effect of discrete dopants in the transistor on circuit characteristics is thus properly estimated. The mobility model used in the device simulation, according to Mathiessen’s rule [59], [60], can be expressed as
1 μ = D μsurf_aps + D μsurf_rs + 1 μbulk (3)
where D = exp(x/lcrit), x is the distance from the interface,
and lcrit is a fitting parameter. The mobility consists of three
parts: 1) the surface contribution due to acoustic phonon scatter-ing μsurf_aps= (B/E) + [C(Ni/N0)τ/E1/3(T /T0)K], where Ni= NA+ ND, T0= 300 K, E is the transverse electric field
normal to the interface of semiconductor and insulator, B and
C are parameters which are based on physically derived
quan-tities, N0and τ are fitting parameters, T is lattice temperature,
and K is the temperature dependence of the probability of sur-face phonon scattering; 2) the contribution attributed to sursur-face roughness scattering is μsurf_rs= ((E/Eref)χ/δ + E3/η)−1,
where χ = A + α(n + p)Nref/(Ni+ N1)ν, Eref= 1 V/cm
is a reference electric field to ensure a unitless numerator in
μsurf_rs, Nref= 1 cm−3 is a reference doping concentration
to cancel the unit of the term raised to the power v in the denominator of χ, δ is a constant that depends on the details of the technology, such as oxide growth conditions, N1= 1 cm−3, A, α, and η are fitting parameters; and 3) the bulk mobility is μbulk= μL(T /T0)−ξ, where μL is the mobility due to bulk
phonon scattering and ξ is a fitting parameter. The mobility model is quantified with our device measurements for the best accuracy, and the characteristic fluctuation has been validated with the experimentally measured dc baseband data [32].
III. RESULTS ANDDISCUSSION
In this section, the device characteristic fluctuations consist-ing of threshold voltage (Vth) and gate capacitance (Cg) are
investigated. Then, the fluctuation of timing characteristics of the circuit is investigated.
Fig. 2. DC characteristic fluctuations of (a) ID–VGcharacteristics, (b) Ion,
(c) Ioff, and (d) Vth of the discrete-dopant-fluctuated 16-nm-gate planar
MOSFET. The solid line in ID–VG curves shows the capacitance of the
nominal case, and the dashed lines are random-dopant-fluctuated devices.
A. Intrinsic DC Characteristic Fluctuation in Nanoscale MOSFET
Fig. 2(a) shows the ID–VG characteristics of 16-nm planar
NMOSFETs with discrete dopant fluctuations; the solid line represents the nominal case (continuously doped channel with a doping concentration of 1.48× 1018 cm−3), and the dashed lines are random-dopant-fluctuated devices. The ON-state cur-rents (Ion), OFF-state currents (Ioff), and threshold voltage
(Vth) are shown in Fig. 2(b)–(d), respectively. Each line and
symbol shown in Fig. 2(a)–(d) indicates the dc characteristic for each device. The threshold voltage is determined from a current criterion that the drain current larger than 10−7(W/L) A. From the random-dopant-number point of view, the equiv-alent channel doping concentration increases when the dopant number increases; this substantially alters the threshold voltage and the ON- and OFF-state currents. Additionally, the random dopant position induced different fluctuations of characteristics in spite of the same number of dopants, as marked in inset shown in Fig. 2(d). Furthermore, the magnitude of the spread characteristics increases as the number of dopants increases. The detailed physical mechanism is described somewhere else [28]–[30], [32], [33]. Notably, the maximum and minimum Vth
are achieved for this specific set of 125 randomized channels and would be different (larger range) if a larger number of samples were taken. Note that, comparing with a simulation of 1000 discrete dopant devices, the difference of the obtained
σVthfor the set of 125 randomized channels is about 3 mV.
B. Gate Capacitance Fluctuation in Nanoscale MOSFET
Fig. 3(a) shows the capacitance–voltage (C–V ) character-istics of the 16-nm planar NMOSFETs with discrete dopant
Fig. 3. (a) Capacitance–voltage curves and (b) slope of the C–V curves for cases with and without taking random-dopant-position effect into consid-eration, where the solid line shows the nominal case and the dashed lines are random-dopant-fluctuated devices. The solid and dot lines in (a) are the cases with and without random-dopant-position effect, respectively. The dashed line in (b) indicates the cases without random-dopant-position effect, and the symbols are the cases with random-dopant-position effect. (c) Normalized gate-capacitance fluctuation and (d) maximum gate-capacitance fluctuation are calculated. (e) Cgfluctuation with different drain bias.
fluctuations. The solid and dot lines are the cases with and without random-dopant-position effect, respectively. The cases without random-dopant-position effect are simulated by chang-ing their channel dopchang-ing concentration continuously from 1.0× 1015 to 3.4× 1018 cm−3. Fig. 3(b) shows the slope of the
C–V curves, in which the gate capacitance (Cg) is fixed to
5× 10−18F.
The dash line indicates the cases without dopant-position effect, and the symbols are the cases with random-dopant-position effect. The slope of C–V curve for the cases without random-dopant-position effect is nearly independent of doping concentration, which implies the lateral shift of the
Fig. 4. (a) Cutoff frequency and (b) intrinsic gate delay of transistor for the discrete-dopant-fluctuated 16-nm-gate planar MOSFETs.
C–V curves. The lateral shift of gate capacitance is a result of
the variation of Vthand can be described by the corresponding
parameters in compact model. However, the slopes of C–V curves are substantially altered as the random-dopant-position effect is taken into consideration, as shown in Fig. 3(b). The variation of the slopes of C–V curves indicates the change of shape of C–V curves, as shown in Fig. 3(a). The variation of
C–V curves is a result of the randomness of the dopant position
in the depletion region of the channel and, therefore, is hard to describe in the current compact model [34]. To the best of the authors’ knowledge, the fluctuation in the gate capacitance (Cg) has not yet been modeled, and a coupled device-circuit
simulation must be performed to estimate its impact on circuit characteristics. Fig. 3(c) shows the normalized Cg fluctuation
as a function of gate bias. The Cg fluctuations are
normal-ized by the nominal Cg. The result implies the importance
of random-dopant-position effect. Moreover, the device under subthreshold operation suffers from the largest fluctuation. For the device with high gate voltage (VG), the screening effect
of the inversion layer of the device screens the variation of electrostatic potential and decreases the fluctuation of gate capacitance [34]. The normalized maximum variations of Cg
are summarized as shown in Fig. 3(d), in which the normalized maximum variation of Cg is about 18.9%. The neglect of
the random-dopant-position effect may underestimate the Cg
fluctuation by a factor of five. Fig. 3(e) shows the Cgfluctuation
with different drain bias. The device with high drain bias has a less gate capacitance fluctuation due to the pinch-off effect and smaller gate-to-drain capacitance at a high drain bias.
The intrinsic cutoff frequency and intrinsic gate delay of the studied device are shown in Fig. 4(a) and (b), respectively. The insets give the definition of these characteristics. As the number of dopants in the device channel is increased, the depletion width decreases and the gate capacitance increases. With the decreasing transconductance (gm) and increasing
gate capacitance, the intrinsic cutoff frequency of the device decreases with increasing dopant number. The intrinsic gate delay is increased as the dopant number increases due to the decreasing ON-state current and increasing gate capacitance. The fluctuations of cutoff frequency and intrinsic gate delay are 8.2 GHz and 0.069 ps, respectively, and the magnitude of fluctuation is increased as the dopant number increases. The
Fig. 5. (a) Voltage transfer curves for the studied 16-nm-gate planar MOSFET circuit. (b) Noise margins, NMLand NMH, as a function of the dopant number
in the NMOSFET and PMOSFET.
discrete dopant effect not only causes fluctuations in Vth and
current but also affects the gate capacitance of the transistor. Therefore, the transistor’s intrinsic gate capacitance is used as a load capacitance in circuit, and the intrinsic timing fluctuations that are induced by discrete dopants are focused.
C. Device-Variability-Induced Fluctuations in Circuits
Fig. 5(a) shows the voltage transfer curves for the 16-nm-gate CMOS inverters with discrete dopants. Two points on the voltage transfer curve determine the noise margins of the inverter. These are the maximum permitted logic “0” at the input VILand the minimum permitted logic “1” at the input VIH.
The two points on the voltage transfer curve are defined as those values of Vinwhere the incremental gain is unity; the slope is −1 V/V. The nominal value and fluctuations of VILand VIHare
shown in the insets of Fig. 5(a). σVILexceeds VIHbecause σVth
of NMOSFETs exceeds that of PMOSFETs. The maximum slope of the voltage transfer curve indicates the maximum voltage gain of the inverter. The 7% of normalized voltage gain fluctuation of the inverter is therefore estimated, as shown in the inset of Fig. 5(a). Fig. 5(b) shows the noise margins for the logic “0” and “1,” NMHand NML, respectively, as a function
of the dopant number. The NMHand NMLare defined in insets.
The NML is increased with the increasing dopant number in
Fig. 6. (a) Input and output signals for the studied discrete-dopant-fluctuated 16-nm-gate inverter circuit. The zoom-in plots of the (b) fall and (c) rise transitions, where the fluctuation of the tHL, t90%, and t10%are defined.
the NMOSFET due to the increased Vthof the device. For the
NMH, as numbers of dopant in the PMOSFET increase, the
increased Vth of the device may decrease the VIH of voltage
transfer curve and, thus, increase the NMH. We notice that,
even for cases with the same number of dopants within the device channel, their noise margins are still quite different due to the different distribution of random dopants. The noise margins of the inverter circuit increase as the dopant number increases; however, the fluctuations of the noise margins are also increased due to the more sources of fluctuation in the device channel region.
Fig. 6 shows the input and output transition characteristics for the inverter circuit. Fig. 6(a) shows the input and output signals; the solid line represents the nominal case (continuously doped channel with a channel doping concentration of 1.48× 1018cm−3), and the dashed lines represent cases with discrete dopant fluctuations. The rise time (tr), fall time (tf), and
hold time of the input signal are 2, 2, and 30 ps, respectively. Fig. 6(b) and (c) shows the zoom-in plots of the falling and rising transitions, respectively. The term tris the time required
for the output voltage (VOUT) to rise from 10% of the logic
“1” level to 90% of the logic “1,” and the tf denotes the time
required for the output voltage to fall from 90% of the logic “1” level to 10% of the logic “1” level. The low-to-high delay time (tLH) and high-to-low delay time (tHL) are defined as the
difference between the times of the 50% points of the input and output signals during the rising and falling of the output signal, respectively. For the high-to-low transition, the NMOSFET is
Fig. 7. Fluctuations of (a) fall and (b) rise signal transition points as a function of dopant number in n- and p-type MOSFETs for the discrete-dopant-fluctuated inverter circuits, in which the transition points are defined in Fig. 5(b) and (c), respectively.
on and starts to discharge load capacitance, causing the output signal to transit from logic “1” to logic “0.” Similarly, for the low-to-high transition characteristics, the PMOSFET is turned on and starts to charge the load capacitance, causing the output voltage to transit from logic “0” to logic “1.” The 90% (t90%)
and 10% (t10%) of the logic “1” level are defined as starting
points for the high-to-low and low-to-high transitions and are shown in Fig. 7(a) and (b), respectively. During the high-to-low signal transition, the output signal falls as the NMOSFETs is turned on. Therefore, the fluctuation of the starting points for high-to-low signal transition is determined by the σVth
of the NMOSFET. With the increasing number of dopants in NMOSFET, the increased Vth delays the starting point of
signal transition (t90%) and increases the high-to-low delay
time (tHL), as shown in Fig. 8(a). Similarly, the starting point of
low-to-high transition (the time of 10% of the logic “1” level) is influenced by Vth of the PMOSFET and increased as numbers
of dopants in the PMOSFET, as shown in Fig. 7(b). Fig. 8(a) and (b) shows the high-to-low delay time (tHL) and
low-to-high delay time (tLH) for the inverter circuits with discrete
dopants, respectively. Since the delay time is dependent on the start of the signal transition, the tHLand tLH are increased as
the channel dopant number increases. Notably, even with the same dopant number inside the channel, the delay time can still vary significantly. Take the cases of six dopants inside the NMOSFETs as an example; the maximum tHL difference is
about 0.3 ps, where the nominal tHL is 0.59 ps. We refer to
this effect as discrete-dopant-position-induced fluctuation. The magnitude of discrete-dopant-position-induced fluctuations
Fig. 8. Fluctuations of (a) high-to-low and (b) low-to-high delay times as a function of dopant number in n- and p-type MOSFETs for the discrete-dopant-fluctuated inverter circuits.
TABLE I
SUMMARIZEDTRANSITION-TIMEVARIATION FOR THE16-nm-GATE
INVERTERCIRCUITS(∗NORMALIZED BY THENOMINALVALUE)
increases as the dopant number increases because of the in-creasing number of fluctuation sources (dopants). Table I sum-marized the normalized timing-characteristic fluctuations (the standard deviation/nominal value× 100%). For the 16-nm-gate CMOS inverter, as the number of discrete dopants varies from 0 to 14, fluctuations of tr, tf, tLH, and tHLof 0.036, 0.021, 0.105,
and 0.108 ps, respectively, may occur. The normalized fluctua-tion for tr, tf, tLH, and tHLare 3.5%, 2.4%, 13.2%, and 18.3%,
respectively. The rise/fall-time fluctuations depend on the charge/discharge capability of the PMOSFETs/NMOSFETs. Therefore, σtr exceeds the σtf because the driving capability
of PMOSFETs is weaker than that of NMOSFETs in the given device dimensions scenario. The device with larger driving capability requires less time to charge and discharge a given load capacitance and so exhibits less fall-time fluctuations. The delay-time fluctuations dominate the timing characteristics. The normalized maximum fluctuations (the maximum variation of time/nominal value × 100%) of the high-to-low and low-to-high delay times are about 101.8% and 73.5%. Notably, the
Fig. 9. Input and output signals for the studied discrete-dopant-fluctuated 16-nm-gate (a) two-inputNANDand (b) two-inputNORcircuits.
maximum and minimum delays associated with this specific set of 125 randomized channels would vary such that their range would increase, as the number of samples increased. For the high-to-low signal transition of the output signal, the delay time is dominated by the starting points of the signal transition and then controlled by theON/OFF-state of the NMOSFETs in the inverter circuit. Therefore, the fluctuation of the threshold voltage of the NMOSFETs substantially affects the high-to-low delay-time characteristic. Similarly, the low-to-high delay-time fluctuation is strongly influenced by the σVth of PMOSFETs. σtHL exceeds σtLHbecause the σVthof NMOSFETs exceeds
that of PMOSFETs. Notably, the rise- and fall-time fluctuations generally may not be as important as the delay-time fluctuation in circuit timing; however, their maximum variations can ex-ceed 0.237 and 0.110 ps, respectively, which exex-ceed the delay-time fluctuation and should therefore be considered in statistical timing analysis in circuit and system design. Moreover, fluctu-ations in the rise and fall times can be added to the delay time and increasing the delay-time fluctuations.
Fig. 9(a) and (b) shows the input and output transition characteristics for the two-inputNAND, and the two-inputNOR circuits, respectively. The solid line represents the nominal case (continuously doped channel with a channel doping concentration of 1.48× 1018 cm−3), and the dashed lines represent cases with discrete dopant fluctuations. The timing characteristics are summarized in Table II. As expected, the timing fluctuations ofNANDandNORcircuits are increased as the number of transistors is increased. The fluctuation of timing characteristics may suffer from the increase of fluctuation sources in circuit. It is thus reasonable to infer that theNAND
TABLE II
SUMMARIZEDTRANSITION-TIMEVARIATION FOR THE16-nm-GATE NAND AND NORCIRCUITS(∗NORMALIZED BY THENOMINALVALUE)
and NOR circuits may exhibit larger timing fluctuations than the inverter circuit. In addition, they may have similar timing fluctuations due to the same number of transistors in the circuit. However, the obtained results show that the σtr and σtf for
theNANDcircuit are 0.53 and 1.87 times larger than that of the NORcircuit. The different characteristic of timing fluctuation is resulted from the different operation status of the device with different input signal. For the fall-time transition characteristics of NAND andNORcircuits, their output signal transitions are determined by the devices N M 2 and N M 4 in Fig. 1(g) and (h), respectively. The N M 2 and N M 4 are operated in the linear and saturation regions, respectively. As aforementioned, the device operated in the saturation region exhibits a better discharge capability to reduce the timing fluctuations. Therefore, the σtfof theNANDcircuit exceeds that of theNOR
due to the different operation status of transistors. Moreover, for the NMOSFETs in series (N M 2 and N M 3 in the NAND circuit), the N M 2 may inherit the fluctuations resulted from
N M 3, such as the current fluctuation and intrinsic resistance
fluctuation to influence the operation of N M 2. Similarly, we can infer that σtr of the NOR circuit is larger than that of
the NAND circuit. The fluctuation of timing characteristics is influenced by the different input signal in circuit. In addition, the transistors in series are found to accumulate fluctuations and increase the fluctuations of circuits. Additionally, we can expect that the timing fluctuation can be reduced by the use of shunt transistors. The effect of the shunt transistor is similar to the increase of the device width of the most fluctuation-sensitive element in the circuits. The function- and circuit-topology-dependent characteristic fluctuations resulted from the random nature of the discrete dopants is, for the first time, briefly discussed and worth to be explored for future digital-circuit applications in nano-CMOS era.
IV. CONCLUSION
In this paper, a 3-D “atomistic” coupled device-circuit simulation approach was adopted to investigate the random-dopant-induced timing-characteristic fluctuations in nanoscale CMOS inverter circuits, concurrently capturing the discrete-dopant-number- and discrete-dopant-position-induced fluctu-ations. The discrete-dopant-induced fluctuations of the gate capacitance, cutoff frequency, and intrinsic gate delay are investigated. The experimentally calibrated simulation tech-nique predicted that the discrete-dopant-fluctuated 16-nm CMOS inverter circuit may exhibit 0.036-, 0.021-, 0.105-, and 0.108-ps fluctuations in the rise time, fall time, low-to-high
delay time, and high-to-low delay time, respectively. The delay-time fluctuations dominate the timing characteristics. The normalized maximum fluctuations of the high-to-low and low-to-high delay times are about 101.8% and 73.5%. However, the maximum variations of rise- and fall-time fluctuations can ex-ceed 0.237 and 0.110 ps, respectively, which exex-ceed the delay-time fluctuation and should therefore be considered in statistical timing analysis in circuit and system design. For theNANDand NOR circuits, the timing fluctuation is further increased with increasing number of transistors in circuit. Generally, circuits with the same transistors may have a similar variation of char-acteristics due to the same fluctuation sources. However, due to the device-operation status and circuit topology of circuits, the characteristic fluctuations inNANDandNORare different. The function- and circuit-topology-dependent characteristic fluctu-ations resulted from random nature of discrete dopants are discussed. The transistors in series may accumulate fluctua-tions and increase the fluctuafluctua-tions of circuits. It is considered that links should be established between circuit design and fundamental device technology to allow circuits and systems to accommodate the individual behavior of every transistor on a silicon chip. This paper provides an insight into random-dopant-induced timing-characteristic fluctuations, which may benefit the development of state-of-the-art digital circuits with robust timing characteristics.
REFERENCES
[1] D. M. Fried, J. M. Hergenrother, A. W. Topol, L. Chang, L. Sekaric, J. W. Sleight, S. McNab, J. Newbury, S. Steen, G. Gibson, Y. Zhang, N. Fuller, J. Bucchignano, C. Lavoie, C. Cabral, D. Canaperi, O. Dokumaci, D. Frank, E. Duch, I. Babich, K. Wong, J. Ott, C. Adams, T. Dalton, R. Nunes, D. Medeiros, R. Viswanathan, M. Ketchen, M. Ieong, W. Haensch, and K. W. Guarini, “Aggressively scaled (0.143 μm2) 6T-SRAM cell for the 32 nm node and beyond,” in IEDM
Tech. Dig., Dec. 2004, pp. 261–264.
[2] F.-L. Yang, D.-H. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu, C.-C. Huang, T.-X. Chung, H.-W. Chen, C.-C. Huang, Y.-H. Liu, C.-C. Wu, C.-C. Chen, S.-C. Chen, Y.-T. Chen, Y.-H. Chen, C.-J. Chen, B.-W. Chan, P.-F. Hsu, J.-H. Shieh, H.-J. Tao, Y.-C. Yeo, Y. Li, J.-W. Lee, P. Chen, M.-S. Liang, and C. Hu, “5 nm-gate nanowire FinFET,” in VLSI Symp. Tech. Dig., Jun. 2004, pp. 196–197.
[3] H. Wakabayashi, T. Ezaki, T. Sakamoto, H. Kawaura, N. Ikarashi, N. Ikezawa, M. Narihiro, Y. Ochiai, T. Ikezawa, K. Takeuchi, T. Yamamoto, M. Hane, and T. Mogami, “Characteristics and modeling of sub-10-nm planar bulk CMOS devices fabricated by lateral source/drain junction control,” IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 715– 720, Sep. 2006.
[4] A. Hafid Zaabab, Q.-J. Zhang, and M. Nakhla, “A neural network model-ing approach to circuit optimization and statistical design,” IEEE Trans.
Microw. Theory Tech., vol. 43, no. 6, pp. 1349–1358, Jun. 1995.
[5] Q. Li, J. Zhang, W. Li, J. S. Yuan, Y. Chen, and A. S. Oates, “RF circuit performance degradation due to soft breakdown and hot-carrier effect in deep-submicrometer CMOS technology,” IEEE Trans. Microw. Theory
Tech., vol. 49, no. 9, pp. 1546–1551, Sep. 2001.
[6] P. R. Kinget, “Device mismatch and tradeoffs in the design of analog circuits,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1212–1224, Jun. 2005.
[7] P. Crippa, C. Turchetti, and M. Conti, “A statistical methodology for the design of high-performance CMOS current-steering digital-to-analog converters,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 21, no. 4, pp. 377–394, Apr. 2002.
[8] J. Jaffari and M. Anis, “Variability-aware bulk-MOS device design,”
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 2,
pp. 205–216, Feb. 2008.
[9] L. Brusamarello, R. da Silva, G. I. Wirth, and R. A. L. Reis, “Probabilis-tic approach for yield analysis of dynamic logic circuits,” IEEE Trans.
Circuits Syst. I, Reg. Papers, vol. 55, no. 8, pp. 2238–2248, Sep. 2008.
[10] H. Nho, S.-S. Yoon, S. S. Wong, and S.-O. Jung, “Numerical estimation of yield in sub-100-nm SRAM design using Monte Carlo simulation,”
IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 9, pp. 907–911,
Sep. 2008.
[11] A. Asenov, S. Kaya, and A. R. Brown, “Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness,” IEEE
Trans. Electron Devices, vol. 50, no. 5, pp. 1254–1260, May 2003.
[12] G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy, and A. Asenov, “Sim-ulation study of individual and combined sources of intrinsic parame-ter fluctuations in conventional nano-MOSFETs,” IEEE Trans. Electron
Devices, vol. 53, no. 12, pp. 3063–3070, Dec. 2006.
[13] H. P. Tuinhout, A. H. Montree, J. Schmitz, and P. A. Stolk, “Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistor,” in IEDM Tech. Dig., 1997, pp. 631–634.
[14] A. R. Brown, G. Roy, and A. Asenov, “Poly-Si gate related variability in decananometre MOSFETs with conventional architecture,” IEEE Trans.
Electron Devices, vol. 54, no. 11, pp. 3056–3063, Nov. 2007.
[15] R. W. Keyes, “Effect of randomness in distribution of impurity atoms on FET thresholds,” Appl. Phys., vol. 8, no. 3, pp. 251–259, Nov. 1975. [16] R. P. Joshi and D. K. Ferry, “Effect of multi-ion screening on the
elec-tronic transport in doped semiconductors: A molecular-dynamics analy-sis,” Phys. Rev. B, Condens. Matter, vol. 43, no. 12, pp. 9734–9739, Apr. 1991.
[17] P. Francis, A. Terao, and D. Flandre, “Modeling of ultrathin double-gate NMOS/SOI transistors,” IEEE Trans. Electron Devices, vol. 41, no. 5, pp. 715–720, May 1994.
[18] J.-R. Zhou and D. K. Ferry, “3D simulation of deep-submicron devices. How impurity atoms affect conductance,” IEEE Comput. Sci. Eng., vol. 2, no. 2, pp. 30–37, Jun. 1995.
[19] X.-H. Tang, V. K. De, and J. D. Meindl, “Intrinsic MOSFET parameter fluctuations due to random dopant placement,” IEEE Trans. Very Large
Scale Integr. (VLSI) Syst., vol. 5, no. 4, pp. 369–376, Dec. 1997.
[20] K. Noda, T. Tatsumi, T. Uchida, K. Nakajima, H. Miyamoto, and C. Hu, “A 0.1-μm delta doped MOSFET fabricated with post-low-energy implanting selective epitaxy,” IEEE Trans. Electron Devices, vol. 45, no. 4, pp. 809–813, Apr. 1998.
[21] P. A. Stolk, F. P. Widdershoven, and D. B. M. Klaassen, “Modeling statistical dopant fluctuations in MOS transistors,” IEEE Trans. Electron
Devices, vol. 45, no. 9, pp. 1960–1971, Sep. 1998.
[22] D. Vasileska, W. J. Gross, and D. K. Ferry, “Modeling of deep-submicrometer MOSFETs: Random impurity effects, threshold voltage shifts and gate capacitance attenuation,” in Proc. Extended Abstracts Int.
Workshop Comput. Electron., Oct. 1998, pp. 259–262.
[23] W. J. Gross, D. Vasileska, and D. K. Ferry, “A novel approach for introducing the electron–electron and electron–impurity interactions in particle-based simulations,” IEEE Electron Device Lett., vol. 20, no. 9, pp. 463–465, Sep. 1999.
[24] H.-S. Wong, Y. Taur, and D. J. Frank, “Discrete random dopant dis-tribution effects in nanometer-scale MOSFETs,” Microelectron. Reliab., vol. 38, no. 9, pp. 1447–1456, Sep. 1999.
[25] N. Sano, K. Matsuzawa, M. Mukai, and N. Nakayama, “Role of long-range and short-long-range Coulomb potentials in threshold characteristics under discrete dopants in sub-0.1 μm Si-MOSFETs,” in IEDM Tech. Dig., Dec. 2000, pp. 275–278.
[26] N. Sano, K. Matsuzawa, M. Mukai, and N. Nakayama, “On discrete random dopant modeling in drift-diffusion simulations: Physical meaning of ‘atomistic’ dopants,” Microelectron. Reliab., vol. 42, no. 2, pp. 189– 199, Feb. 2002.
[27] P. Dollfus, A. Bournel, S. Galdin, S. Barraud, and P. Hesto, “Effect of discrete impurities on electron transport in ultrashort MOSFET using 3D MC simulation,” IEEE Electron Device Lett., vol. 51, no. 5, pp. 749–756, May 2004.
[28] Y. Li and S.-M. Yu, “Comparison of random-dopant-induced threshold voltage fluctuation in nanoscale single-, double-, and surrounding-gate field-effect transistors,” Jpn. J. Appl. Phys., vol. 45, no. 9A, pp. 6860– 6865, Sep. 2006.
[29] Y. Li and C.-H. Hwang, “Discrete-dopant-induced characteristic fluctua-tions in 16 nm multiple-gate silicon-on-insulator devices,” J. Appl. Phys., vol. 102, no. 8, p. 084 509, Oct. 2007.
[30] Y. Li and S.-M. Yu, “A coupled-simulation-and-optimization approach to nanodevice fabrication with minimization of electrical characteristics fluctuation,” IEEE Trans. Semicond. Manuf., vol. 20, no. 4, pp. 432–438, Nov. 2007.
[31] N. Sano and M. Tomizawa, “Random dopant model for three-dimensional drift-diffusion simulations in metal–oxide–semiconductor field-effect-transistors,” Appl. Phys. Lett., vol. 79, no. 14, pp. 2267–2269, Oct. 2001.
[32] Y. Li, S.-M. Yu, J.-R. Hwang, and F.-L. Yang, “Discrete dopant fluctuated 20 nm/15 nm-gate planar CMOS,” IEEE Trans. Electron Devices, vol. 55, no. 6, pp. 1449–1455, Jun. 2008.
[33] Y. Li, C.-H. Hwang, and H.-M. Huang, “Large-scale atomistic ap-proach to discrete-dopant-induced characteristic fluctuations in silicon nanowire transistors,” Phys. Stat. Sol. (A), vol. 205, no. 6, pp. 1505–1510, May 2008.
[34] A. Brown and A. Asenov, “Capacitance fluctuations in bulk MOSFETs due to random discrete dopants,” J. Comput. Electron., vol. 7, no. 3, pp. 115–118, Sep. 2008.
[35] C. L. Alexander, G. Roy, and A. Asenov, “Random impurity scattering induced variability in conventional nano-scaled MOSFETs: Ab initio impurity scattering Monte Carlo simulation study,” in IEDM Tech. Dig., Nov. 2006, pp. 1–4.
[36] X. Tang, K. A. Bowman, J. C. Eble, V. K. De, and J. D. Meindl, “Impact of random dopant placement on CMOS delay and power dissipation,” in
Proc. 29th Eur. Solid-State Device Res. Conf., Sep. 1999, pp. 184–187.
[37] A. Balasubramanian, P. R. Fleming, B. L. Bhuva, A. L. Sternberg, and L. W. Massengill, “Implications of dopant-fluctuation-induced Vt
varia-tions on the radiation hardness of deep submicrometer CMOS SRAMs,”
IEEE Trans. Device Mater. Rel., vol. 8, no. 1, pp. 135–144, Mar. 2003.
[38] H. Mahmoodi, S. Mukhopadhyay, and K. Roy, “Estimation of delay vari-ations due to random-dopant fluctuvari-ations in nanoscale CMOS circuits,”
IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1787–1796, Sep. 2005.
[39] S. K. Springer, S. Lee, N. Lu, E. J. Nowak, J.-O. Plouchart, J. S. Watts, R. Q. Williams, and N. Zamdmer, “Modeling of variation in submicrom-eter CMOS ULSI technologies,” IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2168–2178, Sep. 2006.
[40] R. Tanabe, Y. Ashizawa, and H. Oka, “Investigation of SNM with ran-dom dopant fluctuations for FD SGSOI and FinFET 6T SOI SRAM cell by three-dimensional device simulation,” in Proc. Simul. Semicond.
Processes Device Conf., Sep. 2006, pp. 103–106.
[41] B. Cheng, S. Roy, G. Roy, and A. Asenov, “Impact of intrinsic parameter fluctuations on SRAM cell design,” in Proc. Int. Solid-State Integr. Circuit
Technol. Conf., Oct. 2006, pp. 1290–1292.
[42] Y. Li and C.-H. Hwang, “High-frequency characteristic fluctuations of nano-MOSFET circuit induced by random dopants,” IEEE Trans. Microw.
Theory Tech., vol. 56, no. 12, pp. 2726–2733, Dec. 2008.
[43] G. J. Iafrate, H. L. Grubin, and D. K. Ferry, “Utilization of quantum dis-tribution functions for ultra-submicron device transport,” J. Phys. Colloq., vol. 42, no. C7, pp. C7-307–C7-312, 1981.
[44] M. G. Ancona and H. F. Tiersten, “Macroscopic physics of the silicon inversion layer,” Phys. Rev. B, Condens. Matter, vol. 35, no. 15, pp. 7959– 7965, May 1987.
[45] J.-R. Zhou and D. K. Ferry, “Ballistic phenomena in GaAs MESFETS: Modeling with quantum moment equations,” Semicond. Sci. Technol., vol. 7, no. 3B, pp. B546–B548, Mar. 1992.
[46] J.-R. Zhou and D. K. Ferry, “Simulation of ultra-small GaAs MESFETs using quantum moment equations. II. Velocity overshoot,” IEEE Trans.
Electron Devices, vol. 39, no. 8, pp. 1793–1796, Aug. 1992.
[47] J.-R. Zhou and D. K. Ferry, “Simulation of ultra-small GaAs MESFET us-ing quantum moment equations,” IEEE Trans. Electron Devices, vol. 39, no. 3, pp. 473–478, Mar. 1992.
[48] J.-R. Zhou and D. K. Ferry, “Modeling of quantum effects in ultrasmall HEMT devices,” IEEE Trans. Electron Devices, vol. 40, no. 2, pp. 421– 427, Feb. 1993.
[49] T.-W. Tang, X. Wang, and Y. Li, “Discretization scheme for the density-gradient equation and effect of boundary conditions,” J. Comput.
Elec-tron., vol. 1, no. 3, pp. 389–393, Oct. 2002.
[50] G. Roy, A. R. Brown, A. Asenov, and S. Roy, “Quantum aspects of resolving discrete charges in “atomistic” device simulations,” J. Comput.
Electron., vol. 2, no. 2–4, pp. 323–327, Dec. 2003.
[51] S. Odanaka, “Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures,” IEEE Trans.
Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 6, pp. 837–842,
Jun. 2004.
[52] Y. Li and S.-M. Yu, “A parallel adaptive finite volume method for nanoscale double-gate MOSFETs simulation,” J. Comput. Appl. Math., vol. 175, no. 1, pp. 87–99, Mar. 2005.
[53] Y. Li, H.-M. Lu, T.-W. Tang, and S. M. Sze, “A novel parallel adaptive Monte Carlo method for nonlinear Poisson equation in semiconductor devices,” Math. Comput. Simul., vol. 62, no. 3–6, pp. 413–420, Mar. 2003. [54] Y. Li, S. M. Sze, and T. S. Chao, “A practical implementation of parallel dynamic load balancing for adaptive computing in VLSI device simula-tion,” Eng. Comput., vol. 18, no. 2, pp. 124–137, Aug. 2002.
[55] T. Grasser and S. Selberherr, “Mixed-mode device simulation,”
Micro-electron. J., vol. 31, no. 11/12, pp. 873–881, Dec. 2000.
[56] Y. Li, “A two-dimensional thin-film transistor simulation using adaptive computing technique,” Appl. Math. Comput., vol. 184, no. 1, pp. 73–85, Jan. 2007.
[57] K.-Y. Huang, Y. Li, and C.-P. Lee, “A time-domain approach to simulation and characterization of RF HBT two-tone intermodulation distortion,”
IEEE Trans. Microw. Theory Tech., vol. 51, no. 10, pp. 2055–2062,
Oct. 2003.
[58] Y. Li, J.-Y. Huang, and B.-S. Lee, “Effect of single grain boundary posi-tion on surrounding-gate polysilicon thin film transistors,” Semicond. Sci.
Technol., vol. 23, no. 1, p. 015 019, Jan. 2008.
[59] M. N. Darwish, J. L. Lentz, M. R. Pinto, P. M. Zeitzoff, T. J. Krutsick, and H. H. Vuong, “An improved electron and hole mobility model for general purpose device simulation,” IEEE Trans. Electron Devices, vol. 44, no. 9, pp. 1529–1538, Sep. 1997.
[60] S. Selberherr, Analysis and Simulation of Semiconductor Devices. New York: Springer-Verlag, 1984.
Yiming Li (M’02) received the B.S. degree in ap-plied mathematics and electronics engineering, the M.S. degree in applied mathematics, and the Ph.D. degree in electronics from National Chiao Tung Uni-versity (NCTU), Hsinchu, Taiwan, in 1996, 1998, and 2001, respectively.
In 2001, he joined the National Nano Device Laboratories (NDL), Hsinchu, as an Associate Re-searcher and the Microelectronics and Information Systems Research Center (MISRC), NCTU, as an Assistant Professor, where he has been engaged in the field of computational science and engineering, particularly in modeling, simulation, and optimization of nanoelectronics and very large scale inte-gration (VLSI) circuits. In Fall 2002, he was a Visiting Assistant Professor with the Department of Electrical and Computer Engineering, University of Massachusetts, Amherst. From 2003 to 2004, he was a Research Consultant with the System on a Chip (SoC) Technology Center, Industrial Technology Research Institute, Hsinchu. From 2003 to 2005, he was the Director of the Departments of Nanodevice and of Computational Nanoelectronics, NDL. He is currently the Deputy Director General of NDL. In Fall 2004, he became an Associate Professor with the Department of Communication Engineering, NCTU, where he has been a Full Professor since Fall 2008. He is also the Deputy Director of the Modeling and Simulation Center, NCTU, and conducts the Parallel and Scientific Computing Laboratory, NCTU. His current research areas are in computational electronics and physics, physics of semiconductor nanostructures, device modeling, parameter extraction, VLSI circuit simula-tion, development of technology computer-aided design (TCAD) and electronic CAD tools and SoC applications, bioinformatics and computational biology, advanced numerical methods, parallel and scientific computing, optimization techniques, and computational intelligence. He is the author or a coauthor of more than 120 research papers appearing in international book chapters, journals, and conferences. He has served as a Reviewer, Guest Associate Editor, Guest Editor, Associate Editor, and Editor for many international journals.
Dr. Li is a member of Phi Tau Phi, Sigma Xi, the American Physical Society, the American Chemical Society, the Association for Computing Machinery, the Institute of Electronics, Information and Communication Engineers, Japan, and the Society for Industrial and Applied Mathematics. He is included in Who’s Who in the World. He was the recipient of the 2002 Research Fellowship Award presented by the Pan Wen-Yuan Foundation, Taiwan, and the 2006 Outstanding Young Electrical Engineer Award from the Chinese Institute of Electrical Engineering, Taiwan. He has served as a Reviewer for the IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, the IEEE TRANSACTIONS ON NANOTECHNOLOGY, the IEEE TRANSACTIONS ON
MICROWAVE THEORY AND TECHNIQUES, the IEEE TRANSACTIONS ON
COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, the IEEE ELECTRONDEVICELETTERS, and the IEEE TRANSACTIONS ON
ELECTRONDEVICES. He has organized and served on several international conferences and was an Editor for proceedings of international conferences.
Chih-Hong Hwang received the B.S. degree in en-gineering and system science and the M.S. degree in electronics engineering from National Tsing Hua University, Hsinchu, Taiwan, in 2001 and 2003, re-spectively. He is currently working toward the Ph.D. degree in the Parallel and Scientific Computing Lab-oratory, Department of Communication Engineering, National Chiao Tung University, Hsinchu.
His research interests focus on modeling and sim-ulation of semiconductor nanodevices and variability of nano-CMOS devices and circuits.
Mr. Hwang was the recipient of the Bronze Medal of the 2008 TSMC Outstanding Student Research Award presented by Taiwan Semiconductor Manufacturing Company, Hsinchu, and the 2008 EDA Top-Notch International Conference Paper Award from the Electronic Design Automation Consortium, Taiwan.
Tien-Yeh Li received the B.S. degree in electrical engineering from National Taiwan Ocean University, Keelung, Taiwan, in 2006. He is currently working toward the M.S. degree in the Parallel and Scientific Computing Laboratory, Department of Communica-tion Engineering, NaCommunica-tional Chiao Tung University, Hsinchu, Taiwan.
His research interests focus on modeling and sim-ulation of semiconductor nanodevices; in particular, for nanomemory devices.
Mr. Li was the recipient of the 2008 EDA Top-Notch International Conference Paper Award from the Electronic Design Automation Consortium, Taiwan.
