Novel Full-Chip Gridless Routing Considering Double-Via Insertion

Huang-Yu Chen†_{, Mei-Fang Chiang}†_{, Yao-Wen Chang}†

Lumdo Chen‡, and Brian Han‡

Novel Full-Chip Gridless Routing

Considering Double-Via Insertion

†_{The Electronic Design Automation Laboratory}

Graduate Institute of Electronics Engineering Department of Electrical Engineering

National Taiwan University Taiwan

Outline

 _Introduction

 _{Redundant-Via Aware Two-Pass Routing System}

 _{Post-Layout Double-Via Insertion Algorithm}

 _{Experimental Result}

Outline

 _Introduction

 _{Redundant-Via Aware Two-Pass Routing System}

 _{Post-Layout Double-Via Insertion Algorithm}

 _{Experimental Result}

Redundant-Via Insertion

 _{Via-open defects are one of the dominant failures due Via-open defects}

to the low-k, copper metal process in the nanometer era

 _{Redundant-via insertion is highly recommended Redundant-via insertion}

by foundries to improve via yield and reliability

 Double vias have 10X 100X smaller failure rates than single vias

90nm copper interconnect (source: TSMC) double-via insertion metal 1 metal 2 via redundant via

Dead, Alive, and Critical Vias

 _{For a via, a redundant-via candidate is its adjacent redundant-via candidate}

position where a redundant via can be inserted

 _{Via categories:}

 Dead via: the via with no redundant-via candidateDead via:

 Alive via: the via with at least one redundant-via candidateAlive via:  Critical via: the via with exactly one redundant-via candidateCritical via:

critical via dead via alive vias metal 1 metal 2 via redundant-via candidate

S S T T S S T T

Redundant-Via Aware Routing

 _{Traditionally, double-via insertion is focused on the}

post-layout stage

 _{Minimizing dead and critical vias during routing can Minimizing dead and critical vias during routing}

increase the post-layout double-via insertion rate by 15 25%

 Dead vias cannot be paired with redundant vias

 Critical vias may not be paired due to competition with others

S

S

T

T

Outline

 _Introduction

 _{Redundant-Via Aware Two-Pass Routing System}

 _{Post-Layout Double-Via Insertion Algorithm}

 _{Experimental Result}

Multilevel Routing

 _{Billions of transistors may be fabricated in a single chip}

 _{Multilevel routing has demonstrated the superior Multilevel routing}

capability of handling large-scale designs

Already-routed net

To-be-routed net

coarsening uncoarsening

‧global routing ‧detailed routing

‧failed nets rerouting ‧refinement

Observations

 _{In the coarsening stage, global and detailed routing global and detailed routing}

are intertwined with each other

are intertwined with each other at each level

 _Advantage:

 Routing resource estimation is accurate

 Information of previously routed nets is exactly

known

 _{Disadvantage:}

 Optimization freedom is limited

 Refinement takes a lot of efforts and the solution

easily falls into local optima

Need more flexibility to address

Need more flexibility to address

nanometer electrical effects

nanometer electrical effects

 _{Separate global routing and detailed routingSeparate}

 Effectively perform global and detailed routing optimization

 _{Pre-analyze Pre-analyze congestion to assist resource estimationcongestion}

 Apply bottom-up routing approaches to handle local _bottom-up

circuit effects

 Better for routability, congestion, and via minimization  Redundant-via planning is a local effect

Maximize the optimization freedom

Ideas for Improvements

Our Two-Pass, Bottom-Up Routing Framework

To-be-routed net Already-routed net

G₀

G₁

G₂

coarsening

First Pass Stage

First Pass Stage Second Pass StageSecond Pass Stage Prerouting Stage Prerouting Stage high low coarsening G₀ G₁ G₂ coarsening coarsening

Apply global routing global routing

for local nets and iteratively refine the solution

Use detailed routing detailed routing

for local nets, reroute failed nets, and

estimate resources level by level

Identify congestion congestion hot spots

hot spots based on

the routing topology of each net

Redundant-Via Aware Routing

Congestion-Prediction Prerouting

Congestion-Prediction Prerouting

Congestion-Prediction Prerouting

Via-Minimization Global Routing

Via-Minimization Global Routing

Via-Minimization Global Routing

Via-Minimization Global Routing

Redundant-Via Aware Detailed Routing

Redundant-Via Aware Detailed Routing

Redundant-Via Aware Detailed Routing

congestion-prediction prerouting

Congestion-Prediction Prerouting

 _{Predict congestion hot spots to guide the following routing}

for better congestion minimization

 _{Help to reduce detours and thus the via count}

 Alleviate post-layout double-via insertion efforts

global tile

congestion-minimization global routing

routing topology

S

S

T

T

Probabilistic Congestion Model

 _{Predict congestions based on the probabilistic distribution}

of 1- and 2-bend global routes

probabilistic congestions S S T T +3/5 +1/5 +1/5 +2/5 +1/5 +2/5 +1/5 +1/5 +3/5 +1/5 +1/5 +1/5 +2/5 +1/5 +1/5 +2/5 +1/5

five 1- and 2-bend global routes

Via-Minimization Global Routing

 _{Apply congestion-driven global pattern routing pattern routing}

[TCAD’02] to reduce via counts

 Uses L-shaped (1-bend) and Z-shaped (2-bend) connections

to route nets

 Has lower time complexity than maze routing

 _{The objective is to minimize dead and critical vias}

 _{Router should select a path that passes through the}

fewest redundant-via candidates in the routing graph

 It may incur more detours and thus more vias

 _{Must consider (1) redundant-via planning and (2) via}

minimization simultaneously

 _{Take the via count and via count redundant-via related penalty redundant-via related penalty}

as the cost to guide the detailed maze routing

Redundant-Via Aware Detailed Routing

Cost function for a net n:

V_n: #via, P_n: redundant-via related penalty.n n

V

P

Redundant-Via Related Penalty

 Degree of Freedom of via v (DoF_v):

 # of redundant-via candidates of v

 _{Set the cost of redundant-via candidate r as}

S T 1/3 1/3 1/3 1/4 1/4 1/4 1/4 1/2 1/2 S T penalty = 5/6 penalty = 1/4

?

?

Outline

 Introduction

 _{Redundant-Via Aware Two-Pass Routing System}

 _{Post-Layout Double-Via Insertion Algorithm}

 _{Experimental Result}

Post-Layout Double-Via Insertion Problem

 _{Given a post-routing layout, pair each via with one}

redundant via as many as possible without incurring any design-rule violation

 _{Different approaches may affect the insertion result}

2 vias are paired 3 vias are paired

metal 1 metal 2 via redundant via Better Yield

Previous Work

 _{Yao et al. [GLSVLSI’05] mentioned that post-layout}

double-via insertion can be solved by maximum bipartite matching

 _{Lee and Wang [ASPDAC’06] showed that maximum maximum}

bipartite matching formulation is incorrect for some

bipartite matching formulation is incorrect for some

cases

cases

 _{Lee and Wang used maximum independent set (MIS) maximum independent set (MIS)}

to solve the problem and applied heuristics to speed up

MIS is NP-complete,

MIS is NP-complete,

high time complexity

high time complexity

A Troublesome Example

(horizontal design-rule conflict)

v₂ v₃ v₁ v₁ r₂ v₂ v₃ v₂ v₃ v₁ v₁ r₁ v₂ v₃ V₁ and V₃ cannot be paired simultaneously (vertical design-rule conflict)

routing layout _{cross-section view}

metal 1 metal 2 via12 redundant-via candidate metal 3 via13

Bipartite Graph Formulation Problem

?

Outline

 Introduction

 _{Redundant-Via Aware Two-Pass Routing System}

 _{Post-Layout Double-Via Insertion Algorithm}

 Optimal Algorithm for up to 3 Routing LayersOptimal Algorithm for up to 3 Routing Layers  On-Track/Stack Redundant-Via Enhancement  Two-Stage Double-Via Insertion (TDVI) Algorithm

 _{Experimental Result}

Our Bipartite Formulation

 _{If stack via is treated as one unit via, the double-via stack via is treated as one unit via}

insertion for designs with up to 3 layers can be optimally up to 3 layers

solved by maximum bipartite matchingmaximum bipartite matching

 A polynomial-time optimal algorithm for the restricted case

 _{The troublesome example can be accurately formulated}

v_{1 v2}

routing layout redundant-via candidate

metal 1 metal 2 via12 metal 3 via13 r₂ v₂ v₃ r v₁ v₂ v₁ v₂ cross-section view v₂ v₁ r2 v₂ v₃ r v₁ v₂ v₂ v₁

r_4,5 v₁ v₂ r₁ r₂ r₃ r₆ Alive Vias Redundant-Via Candidates v₃ r₉ r_7,8

final bipartite graph

Optimal Algorithm for up to 3 Layers

v₁ v₂ r₁ r₂ r₃ r₄ r₅ r₆ Alive Vias Redundant-Via Candidates v₃ r₇ r₈ r₉ v₁ v₂ r₁ r₆ v₃ r₈ r₂ r₃ r4 r7 r₉ r₅ r₈ v₂ r₇ v₃ design-rule conflict between r₇ and r₈ routing layout

Outline

 Introduction

 _{Redundant-Via Aware Two-Pass Routing System}

 _{Post-Layout Double-Via Insertion Algorithm}

 Optimal Algorithm for up to 3 Routing Layers

 On-Track/Stack Redundant-Via EnhancementOn-Track/Stack Redundant-Via Enhancement  Two-Stage Double-Via Insertion (TDVI) Algorithm

 _{Experimental Result}

Preference for On-Track/Stack Redundant Via

 _{Redundant vias can be placed on-track or off-track.}

 If a redundant via is placed on the wire segment of its

corresponding via, it is on-track; otherwise, it is off-track

 _{Prefer on-track andon-track stack redundant vias for double- stack}

via insertion

 On-track redundant vias consume fewer routing resources  Better to protect stack vias which have lower yield than

single vias r₁ r₂ r₃ r4 r₆ r₅ v₁ v₂ on-track metal 1 metal 2 via12 redundant-via candidate metal 3 via23 off-track

On-Track/Stack Redundant-Via Enhancement

 _{Construct the weighted bipartite graph and use weighted bipartite graph}

minimum weighted bipartite matching

minimum weighted bipartite matching to solve

 _{For via v and its redundant-via candidate r, define}

weight w(v, r) as follows:

stack redundant via preference

on-track redundant via preference

w(v,r) = tr/N, if v is a stack via containing N single vias;

tr, if v is a single via.

Double-Via Insertion with Preference

weighted bipartite graph

redundant via r₄ v₁ v₂ r₁ r₂ r₃ r₆ r₇ v₃ r₉ r₈ r₅ metal 3 metal 1 metal 2 redundant-via candidate via23 via12 via24 metal 4 insertion result with preference v₁ v₂ v₃ r₁ r₆ r₉

Outline

 Introduction

 _{Redundant-Via Aware Two-Pass Routing System}

 _{Post-Layout Double-Via Insertion Algorithm}

 Optimal Algorithm for up to 3 Routing Layers  On-Track/Stack Redundant-Via Enhancement

 Two-Stage Double-Via Insertion (TDVI) AlgorithmTwo-Stage Double-Via Insertion (TDVI) Algorithm

 _{Experimental Result}

L_b

L_b

L_t

L_t

Two-Stage Double-Via Insertion Algorithm

1. Partition the layout into sublayouts with at most 3 layers, s.t. # of design-rule conflicts between sublayouts is

minimized v₁ v₂ v₃ v₄ r₃ r₇ v₆ r₄ r₈

metal 1 metal 2 via

r₁ r₂

r₆ r5

v₅

criticality = 2 criticality = 0

Two-Stage Double-Via Insertion Algorithm

2. Decide the priority of each sublayout by criticalitycriticality

 For redundant-via candidate r that has design-rule conflicts with

the different sublayout, criticality cr = # of induced dead vias after

inserting r; otherwise, cr = 0

 Criticality of sublayout L = Σ c_r, where r is inside L

v₁ r₁ r₄ v₅ v2 v₃ v₄ r₇ r₅ v₆ r₈ Criticality: 0 r₂ r₃ r_{6 L Criticality: 2} b L_b L_t L_t

Two-Stage Double-Via Insertion Algorithm

3. Solve sublayouts in the non-decreasing order of criticality

 If one sublayout is solved, update its adjacent sublayouts by

removing the infeasible redundant-via candidates

v₁ r₁

r₄

v₃

r₃

r₆ r5

metal 1 metal 2 via

Criticality: 0 Criticality: 2 L_b L_b r₁ r₂ v₁ v₂ v₃ v₄ v₅ v r7,8 r_4,5 r₃ v₅ conflict L_t L_t v₂ v₄ r₇ v₆ r₈ r₂

Outline

 Introduction

 _{Redundant-Via Aware Two-Pass Routing System}

 _{Post-Layout Double-Via Insertion Algorithm}

 _{Experimental Result}

35

Experimental Setting

 _Platforms

 Routing system: 1.2 GHz Sun Blade 2000

 Double-via insertion algorithm: 3.2 GHz Intel Pentium 4

 _{DRC verification: Cadence SoC Encounter}

 _{MCNC benchmark:}

Circuit Size (um2_{) #Layer #Net #Pin}

Mcc1 45000 × 39000 4 1693 3101 Mcc2 152400 × ₁₅₂₄₀₀ 4 7541 2502₄ Struct 4903 × 4904 3 3551 5471 Primary 1 7522 × 4988 3 2037 2941 Primary 2 10438 × 6488 3 8197 11226 S5378 435 × 239 3 3124 4818 S9234 404 × 225 3 2774 4260 S13207 660 × 365 3 6995 1077₆ S15850 705 × 389 3 8321 1279₃ S38417 1144 × 619 3 2103₅ 3234₄

Gridless Routing Comparison

 _{Compared with the gridless router}

 Reduce the via count 20% over MGR [ASPDAC’05]  Reduce the via count 24% over VMGR [ASPDAC’06]

Redundant-Via Aware Detailed Routing

 _{Consider redundant vias during detailed routing}

 1.4X fewer dead vias and 1.1X fewer critical vias  2% slight increase in the via count

Post-Layout Double-Via Insertion

 _{Compared with H3K [ASPDAC’06]}

 71X runtime speedup

Outline

 _Introduction

 _{Redundant-Via Aware Two-Pass Routing System}

 _{Post-Layout Double-Via Insertion Algorithm}

 _{Experimental Result}

Conclusion

 _{We have developed a redundant-via aware gridless}

routing system

 Reduced via counts

 Obtained fewer dead vias and critical vias

 _{We have proposed a post-layout double-via insertion}

algorithm

 Resulted in a higher insertion rate  Resulted in a higher on-track rate