Investigation of random dopant fluctuation for multi-gate metal-oxide-semiconductor field-effect transistors using analytical solutions of three-dimensional Poisson's equation

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Investigation of Random Dopant Fluctuation for Multi-Gate Metal–Oxide–Semiconductor

Field-Effect Transistors Using Analytical Solutions of Three-Dimensional Poisson's Equation

View the table of contents for this issue, or go to the journal homepage for more 2008 Jpn. J. Appl. Phys. 47 2097

(http://iopscience.iop.org/1347-4065/47/4R/2097)

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Investigation of Random Dopant Fluctuation for Multi-Gate Metal–Oxide–Semiconductor

Field-Eﬀect Transistors Using Analytical Solutions of Three-Dimensional Poisson’s Equation

Yu-Sheng WUand Pin SU

Department of Electronics Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 30013, Taiwan (Received September 28, 2007; accepted January 29, 2008; published online April 18, 2008)

This paper investigates the random dopant fluctuation of multi-gate metal–oxide–semiconductor field-effect transistors (MOSFETs) using analytical solutions of three-dimensional (3D) Poisson’s equation verified with device simulation. Especially, we analyze the impact of aspect ratio on the random dopant fluctuation in multi-gate devices. Our study indicates that with a given total width, lightly doped fin-type FET (FinFET) shows the smallest threshold voltage (Vth) dispersion

because of its smaller Vth sensitivity to the channel doping. For heavily doped devices, quasi-planar shows smaller Vth

dispersion because of its larger volume. The Vthdispersion caused by random dopant ﬂuctuation may still be signiﬁcant in the

lightly doped channel, especially for tri-gate and quasi-planar devices. [DOI:10.1143/JJAP.47.2097]

KEYWORDS: multi-gate MOSFETs, FinFET, tri-gate, 3-D Poisson’s equation, random dopant fluctuation

1. Introduction

Due to its better gate control, multi-gate structure is an important candidate for complementary metal–oxide–semi-conductor (CMOS) scaling.1–3)_{Dependent on the aspect ratio}

(AR), fin-type field-effect transistor (FinFET) (AR > 1), tri-gate (AR ¼ 1) and quasi-planar (AR < 1) devices are typical options in the multi-gate device design. Whether there is an optimum choice among the three options merits investigation.

With the scaling of device geometry, random dopant ﬂuctuation has become a crucial issue to device design. Although Thean et al.4)_{have examined the threshold voltage}

(Vth) variations of doped and undoped FinFET devices

experimentally, a detailed analysis of the random dopant ﬂuctuation in multi-gate MOSFETs has rarely been seen. In this work, we compare the Vth dispersion caused by

random dopant ﬂuctuation for FinFET, tri-gate and quasi-planar devices with both heavily doped and lightly doped channels using analytical solution of three-dimensional (3-D) Poisson’s equation. Through our theoretical model, the impact of device aspect ratio on the random dopant ﬂuctuation in multi-gate MOSFETs is examined.

This paper is organized as follows. In §2, we derive an analytical potential distribution for a generic multi-gate device structure. The threshold voltage can then be determined based on the potential solution. In §3, we investigate the Vth variation caused by random dopant

ﬂuctuation for multi-gate devices with various aspect ratio based on our theoretical calculation. The conclusion will be drawn in §4.

2. Potential Solution and Vth Calculation

An analytical potential solution is crucial to the deriva-tion of device subthreshold characteristics such as Vth.

Figure 1(a) shows the schematic sketch of a multi-gate silicon-on-insulator (SOI) structure. The Si-fin body covered by gate insulator is a cuboid with six faces, and each face is connected to a voltage bias. In the subthreshold regime, the Si-fin body is fully depleted with negligible mobile carriers. Therefore, the potential distribution, ðx; y; zÞ, satisfies the Poisson’s equation: @2ðx; y; zÞ @x2 þ @2ðx; y; zÞ @y2 þ @2ðx; y; zÞ @z2 ¼ qNa "si ; ð1Þ where Na is the doping concentration of the Si-fin. The

required boundary conditions can be described as ðWfin; y; zÞ þ ti,f "si "i @ðx; y; zÞ @x x¼Wfin ¼VfgVfb; ð2aÞ y BOX x z Hfin

W

fin

0

Leff insulator Si-body

t

i,f

t

i,b

t

i,t

t

ox,u = fin 0 3-D Poisson’s equ.+ 1-D Poisson’s equ. 2-D B.C. 2-D approx. B.C. 2-D Laplace equ. 3-D Laplace equ. 3-D approx. B.C. 1-D B.C. 3 2 1 φ φ φ φ= + +

1

φ

2

φ

3 ( − = − DS H fin 0 W kT z) y x q eff kT qV a i dz dx e L e q kT N n q I , , 2 min 1 1 φ μ Vth (a) (b) original 3-D B.C. 3-D B.C. DS

Fig. 1. (a) Schematic sketch of the multi-gate device structure inves-tigated in this study. (b) Flow chart demonstrating the Vthcalculation of multi-gate devices. Approximation was made to simplify the 2-D and 3-D boundary conditions (B.C.) to obtain a simpliﬁed channel potential solution form.

E-mail address: [email protected] #2008 The Japan Society of Applied Physics

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ð0; y; zÞ ti,b "si "i @ðx; y; zÞ @x _x¼0¼VbgVfb; ð2bÞ ðx; y; HfinÞ þti,t "si "i @ðx; y; zÞ @z _z¼H fin ¼VtgVfb; ð2cÞ ðx; y; 0Þ tox,u "si "ox @ðx; y; zÞ @z z¼0 ¼VugVfb; ð2dÞ ðx; 0; zÞ ¼ ms; ð2eÞ ðx; Leff; zÞ ¼ msþVDS; ð2fÞ

where "si, "i, and "ox are dielectric constants of the Si-ﬁn,

gate dielectric, and oxide, respectively. Wfin, Hfin, and Leff

are defined as fin width, fin height, and channel length, respectively. ti,t, ti,f, ti,b, and tox,u are thicknesses of top gate

dielectric, front gate dielectric, back gate dielectric, and

buried oxide, respectively. Vfg, Vbg, Vtg, Vug, and VDSare the

voltage biases of front gate, back gate, top gate, buried gate and drain terminal, respectively. Vfb is the ﬂat-band voltage

for these gate terminals. ms is the built-in potential of the

source/drain to the channel.

Figure 1(b) shows the ﬂow chart of the Vthcalculation by

solving the 3-D boundary value problem. This 3-D boundary value problem can be divided into three sub-problems, including one-dimensional (1-D) Poisson’s equation, two-dimensional (2-D) and 3-D Laplace equation. Using the superposition principle, the complete potential solution is ¼ 1þ2þ3, where 1, 2, and 3are solutions of the

1-D, 2-D, and 3-D sub-problem, respectively. The 1-D solution 1 can be expressed as

1ðzÞ ¼ qNa 2"si z2þaz þ b; ð3aÞ a ¼ ðVtgVfbÞ ðVugVfbÞ þ qNa 2"si Hfin2þ2 "si "i ti,tHfin Hfinþ "si "i ti,tþ "si "ox tox,u ; ð3bÞ b ¼ "si "ox tox,ua þ ðVugVfbÞ: ð3cÞ

In solving the 2-D and 3-D sub-problems, approximation was made to avoid the numerical iteration required in ﬁnding the eigenvalues5)_{and to simplify the solution form. The boundary conditions [eqs. (2a)–(2d)] are simpliﬁed by converting the}

gate dielectric thickness to ("si="i) times and replacing the gate dielectric region with an equivalent Si region.6)The electric

field discontinuity across the gate dielectric and Si-fin interface can thus be eliminated. In other words, the Si-fin body and the gate dielectric region are treated as a homogeneous silicon cuboid with an effective width Weff and an effective height Heff

given by eqs. (4) and (5), respectively.

Weff¼Wfinþ "si "i ðti,fþti,bÞ; ð4Þ Heff ¼Hfinþ "si "i ti,tþtox,u: ð5Þ

The 2-D solution 2 can be obtained using the method of separation of variables:

2ðx; zÞ ¼ X1 i¼1 cisinh i Heff x þ"si "i ti,b þc0_isinh i Heff Weff x þ "si "i ti,b sin i Heff ðz þ tox,uÞ ; ð6aÞ where ci¼ 1 sinh iWeff Heff " 2ðVfgVfbbÞ 1 ð1Þi i þ2a tox,u i þ ðHefftox,uÞð1Þi i ! þqNa "si ðtox,uÞ2 i ðHefftox,uÞ2ð1Þi i þ2Heff 2ð1Þ i₁ ðiÞ3 # ; ð6bÞ c0_i¼ 1 sinh iWeff Heff " 2ðVbgVfbbÞ 1 ð1Þi i þ2a tox,u i þ ðHefftox,uÞð1Þi i þqNa "si ðtox,uÞ2 i ðHefftox,uÞ2ð1Þi i þ2Heff 2ð1Þ i₁ ðiÞ3 # : ð6cÞ

Similarly, the 3-D solution 3 can also be obtained and expressed as

3ðx; y; zÞ ¼

X1 m¼1

X1 n¼1

½em;nsinhðkyyÞ þ e0m;nsinhðkyðLeffyÞÞ sin

m Weff x þ"si "i ti,b sin n Heff ðz þ tox,uÞ ; ð7aÞ where

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ky¼ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi m Weff 2 þ n Heff 2 s ; ð7bÞ em;n¼ 1 sinðkyLeffÞ 8 > > > > > < > > > > > : & $ðmsþVDSbÞ 1 ð1Þm m þ qNa 2"si Weff "si "i ti,b 2 ð1Þm _" si "i ti,b 2 m þ 2Weff2ðð1Þm1Þ ðmÞ3 0 B B B @ 1 C C C A þa Weff "si "i ti,b ð1Þmþ"si "i ti,b m 0 B B B @ 1 C C C A ’ % 4 ð1 ð1ÞnÞ n þ2cm ð1Þn n sinh mHeff Weff 1 þ m n Heff Weff 2 2c 0 m 1 nsinh mHeff Weff 1 þ m n Heff Weff 2 9 > > > > > = > > > > > ; ; ð7cÞ e0_m;n¼ 1 sinðkyLeffÞ 8 > > > > > < > > > > > : & $ðmsbÞ 1 ð1Þm m þ qNa 2"si Weff "si "i ti,b 2 ð1Þm "si "i ti,b 2 m þ 2Weff2ðð1Þm1Þ ðmÞ3 0 B B B @ 1 C C C A þa Weff "si "i ti,b ð1Þmþ"si "i ti,b m 0 B B B @ 1 C C C A ’ % 4 ð1 ð1ÞnÞ n þ2cm ð1Þn n sinh mHeff Weff 1 þ m n Heff Weff 2 2c 0 m 1 nsinh mHeff Weff 1 þ m n Heff Weff 2 9 > > > > > = > > > > > ; : ð7dÞ

Our potential solution has been veriﬁed by 3-D device simulation.7)_{Figures 2(a) and 2(b) compare the derived channel}

potential distribution with device simulation for heavily doped and lightly doped devices, respectively. Note that a smaller equivalent oxide thickness (EOT) is used in the lightly-doped case to sustain the electrostatic integrity.3)_{It can be seen that}

our model shows satisfactory accuracy.

After deriving the channel potential solution, the subthreshold current can be calculated by8)

IDS¼q ni2 Na kT q 1 exp qVDS kT 1 Leff ZHfin 0 Z Wfin 0 exp qðx; ymin; zÞ kT dx dz ð8Þ

where ðx; ymin; zÞ is the minimum potential (i.e., the highest

barrier for carrier ﬂow) along the y (channel length) direction.9) _{For devices biased in the linear region, the}

minimum potential occurs at ymin¼Leff=2 because of the

nearly symmetrical potential distribution along the channel. We deﬁne the Vthas the gate voltage at which the calculated

subthreshold current IDS¼300nA Wtotal=Leff,10) where

Wtotal¼2HfinþWfin is the total width of the multi-gate

device.

Compared with the computer-aided-design for semicon-ductor manufacturing technology (TCAD) device simula-tion, our methodology shows higher eﬃciency in determin-ing the Vth of a multi-gate device. The central processing

unit (CPU) time needed for a single Vth using TCAD

simulation is about tens of minutes, while in our calculation only several seconds is needed. More importantly, this theoretical framework provides more scalable and predictive results than experimental or TCAD simulation does.

0.0 0.2 0.4 0.6 0.8 1.0 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 x 0 W_fin/2 L_eff/2 0 W_fin/2 0 z L_eff=20nm, t_ox=1nm potential (V) normalized position V_GS=-0.2V, V_DS=0.05V y simulation model (a)

W_fin L_eff/2 H_fin/2 H_fin L_eff H_fin/2 doping=6 x1018_cm-3_{, W} fin=Hfin=30nm 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 VGS=-0.2V, VDS=0.05V L_eff=20nm, t_HfO2=2nm x z simulation model normalized position potential (V) (b) 0 W_fin/2 L_eff/2 0 W_fin/2 0

W_fin L_eff/2 H_fin/2 H_fin L_eff H_fin/2 doping=1x1017 cm-3 , W_fin=H_fin=30nm y

Fig. 2. (Color online) Analytical potential distribution compared with the result of 3-D device simulation. For the lightly doped case, a midgap workfunction is used (4.7 eV).

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3. Vth Dispersion Caused by Random Dopant

Fluctuation

We have derived the 3-D analytical potential solution for multi-gate MOSFETs with uniformly doped channel. Al-though the actual 3-D charge distribution is not uniform, we can incorporate the dopant number ﬂuctuation in our theoretical framework to assess the feasibility of various multi-gate device designs. The dopant number in the channel has been found to follow Poisson distribution13)_{and the V}

th

distribution caused by random dopant ﬂuctuation can be approximated as Gaussian distribution.13–15)_{With MOSFET}

scaling, the Vthdistribution gradually changes its shape from

the Gaussian to a Poisson-like distribution.15)_{To assess the}

Vthvariation of multi-gate devices caused by dopant number

ﬂuctuation, in this work, we assume that the dopant number in the channel follows Poisson distribution11,15) and the standard deviation () of the dopant number is na1=2, where

na is the average dopant number in the Si-body. The Vth

variation for dopant number ﬂuctuation can then be calculated as Vth¼ jVthðþ3Þ Vthð3Þj=2.

To compare the multi-gate devices with various aspect ratio (AR ¼ Hfin=Wfin), we focus on the FinFET (AR ¼ 2),

tri-gate (AR ¼ 1), and quasi-planar (AR ¼ 0:5) structures (Fig. 3). The total width (Wtotal¼2HfinþWfin) of various

AR devices are all equal to 75 nm to make fair comparison. Besides heavily doped devices, we also examined the impact of random dopant ﬂuctuation on the Vthdispersion of lightly

doped devices. For heavily doped devices, the channel doping is equal to 6 1018_cm3_{. For lightly doped channel}

the channel doping is 1 1017_cm3_{. Note that gate oxide}

(tox ¼1 nm) is used for heavily doped devices, while high-k

dielectric (tHfO2¼2 nm and the dielectric constant of HfO2 is 25) is used for lightly doped ones to sustain the device electrostatics.3)

Figure 4 shows the AR dependence of Vth caused by

random dopant ﬂuctuation, and the results are veriﬁed with device simulation.7) _{For heavily doped channel, the V}

th

increases with AR, and the minimum Vth occurs at

AR ¼ 0:5, i.e., quasi-planar device. This is because for a given total width, the devices with AR ¼ 0:5 possess the largest channel volume (Fig. 5). Since

Vth¼ dVth dNa Na; ð9Þ Na¼ na V / ffiffiffiffiffi na p V ¼ ffiffiffiffiffiffiffiffiffiffiffiffi NaV p V ¼ ffiffiffiffiffi Na p ffiffiffiffi V p ; ð10Þ

where V is the channel volume, the devices with larger channel volume show smaller Vth. In addition to channel

volume, eq. (9) demonstrates that the Vth sensitivity to the

channel doping (dVth=dNa) may also determine the Vth.

Figure 6 shows the channel doping dependence of Vth for

devices with heavily doped channel. It can be seen that FinFET, tri-gate and quasi-planar devices show similar Vth

sensitivity. Therefore, for heavily doped channel, quasi-planar device shows better immunity to random dopant ﬂuctuation than FinFET and tri-gate because of its larger channel volume.

Figure 7 shows that for lightly doped channel, the Vth

increases as AR decreases. This is because for lightly doped channel, devices with diﬀerent AR show diﬀerent Vth

sensitivity to channel doping (Fig. 8). For lightly doped channel, FinFET shows the smallest Vth sensitivity to

channel doping because of its narrower Wfin for a given

total width. In other words, Wfin scaling enhances the gate

control and reduces the Vth dependence on the channel

doping. Therefore, FinFET shows the best immunity to dopant ﬂuctuation for lightly doped channel.

Tri-gate

(b) (a)

FinFET

Quasi-planar

(c)

Fig. 3. (Color online) Illustration of three diﬀerent AR devices for a given total width: (a) FinFET (AR ¼ 2), (b) tri-gate (AR ¼ 1), and (c) quasi-planar device (AR ¼ 0:5).

0.5 1.0 1.5 2.0 35 40 45 50 55 simulation

Heavily doped channel W_total=75nm, L_eff=25nm V_DS=0.05V Δ Vth (mV) Aspect Ratio model

Fig. 4. The AR dependence of Vthcaused by random dopant ﬂuctuation in the heavily doped channel.

0.0 1.0 1.5 2.0 Quasi-planar Tri-gate W_total=75nm L_eff=25nm c hannel v olume (10 -17 cm 3 ) Aspect Ratio FinFET 0.5 1.0 1.5 2.0 2.5

Fig. 5. For a given total width, devices with AR ¼ 0:5 possess the largest channel volume. Devices with larger volume will show less doping variation caused by random dopant ﬂuctuation.

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To assess the impact of random dopant ﬂuctuation on the overall Vth variation, we have calculated the proportion of

Vth dispersion due to random dopant ﬂuctuation to the

overall Vth variation (Fig. 9). The Vth caused by Leff

variation (Vth;Leff), Wfin variation (Vth;Wfin), Hfinvariation (Vth;Hfin) and random dopant ﬂuctuation (Vth;RDF) are considered in our calculation. We assume that the 3 process variations of these device parameters are 10% of their nominal values, and the Vth variation is deﬁned as Vth¼

jVthðþ10%Þ Vthð10%Þj=2.11) The overall Vth variation

is deﬁned as V2 th¼V 2 th;LeffþV 2 th;WfinþV 2 th;Hfinþ V2

th;RDF. Figure 9(a) shows that for heavily doped channel,

random dopant ﬂuctuation dominates the overall Vth

dis-persion and the quasi-planar device shows better immunity than devices with other aspect ratio to dopant ﬂuctuation. Our theoretical result is consistent with the experimental data from Thean et al.,4)_{who showed that for doped channel,}

the Vth of the devices with smaller volume is larger than

that of the devices with larger volume. Although lightly doped channel has been suggested12) _{to suppress the V}

th

variation caused by dopant ﬂuctuation, Fig. 9(b) shows that the Vth variation caused by dopant ﬂuctuation is still

signiﬁcant for lightly-doped tri-gate and quasi-Planar de-vices. The impact of random dopant ﬂuctuation may still be an issue to the Vthdispersion of lightly doped channel unless

devices with good electrostatic integrity such as FinFET are used.

4. Conclusions

We have investigated the Vthdispersion caused by random

dopant fluctuation of multi-gate MOSFETs using analytical solutions of 3-D Poisson’s equation verified with device simulation. Especially, we analyze the impact of aspect ratio on the dopant fluctuation in multi-gate devices. With a given total width, lightly doped FinFET shows the smallest Vth

dispersion because of its smaller Vth sensitivity to the

channel doping. For heavily doped channel, quasi-planar device shows smaller Vth dispersion because of its larger

channel volume. The Vth dispersion due to random dopant

ﬂuctuation may still be signiﬁcant in the lightly doped channel, especially for tri-gate and quasi-planar devices.

0.5 1.0 1.5 2.0 0 5 10 15 20 25 30 simulation Lightly doped channel

Δ Vth (mV) Aspect Ratio model W_total=75nm, L_eff=25nm V_DS=0.05V

Fig. 7. The AR dependence of Vthcaused by dopant number ﬂuctuation in the lightly doped channel.

0.0 5.0x1017_1.0x1018_1.5x1018_2.0x1018 0.25 0.30 0.35 0.40 0.45 0.50 0.55 W_total=75nm, L_eff=25nm t_HfO2=2nm, V_DS=0.05V AR=0.5 Vth (V) Doping concentration (cm-3) AR=1 AR=2

Fig. 8. (Color online) Model prediction of the doping dependence of Vth for lightly doped channel with the same total width.

95 96 97 98 99 100 L_eff=25nm AR=0.5 AR=1 AR=2 Δ Vth,RDF

/

Δ Vth,T otal (%)

Heavily doped channel

0 10 20 30 40 L_eff=25nm AR=0.5 AR=1 AR=2 Δ Vth,RDF

/

Δ Vth,T otal (%)

Lightly doped channel

(a) (b)

Fig. 9. (Color online) The proportional of the Vth caused by dopant number ﬂuctuation to the overall Vthfor (a) heavily doped channel and (b) lightly doped channel.

4x1018 _5x1018 _6x1018 _7x1018 0.55 0.60 0.65 0.70 AR=0.5 W_total=75nm, L_eff=25nm t_ox=1nm, V_DS=0.05V Vth (V) Doping concentration (cm-3₎ AR=1 AR=2

Fig. 6. (Color online) Model prediction of the doping dependence of Vth for heavily doped channel with the same total width.

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Acknowledgements

This work was supported in part by the National Science Council of Taiwan under contract NSC95-2221-E-009-327-MY2, the Ministry of Education in Taiwan under ATU Program, and Taiwan Semiconductor Manufacturing Com-pany.

1) O. Faynot, G. Barna, R. Ritzenthaler, and P. Gidon: Ext. Abstr. Solid State Devices and Materials, 2004, p. 764.

2) J. W. Yang and J. G. Fossum:IEEE Trans. Electron Devices 52 (2005) 1159.

3) J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W. Rachmady, M. Radosavljevic, U. Shah, N. Zelick, and R. Chau: Proc. VLSI Technology Symp. (2006) p. 50. 4) A. V. Thean, Z. H. Shi, L. Mathew, T. Stephens, H. Desjardin, C. Parker, T. White, M. Stoker, L. Prabhu, R. Garcia, B. Y. Nguyen, S. Murphy, R. Rai, J. Conner, B. E. White, and S. Venkatesan: IEDM

Tech. Dig., 2006, p. 881.

5) G. Katti, N. DasGupta, and A. DasGupta: IEEE Trans. Electron Devices 51 (2004) 1169.

6) T. N. Nguyen: Dr. Thesis, Stanford University, Stanford, CA (1984). 7) ISE TCAD Rel. 10.0 Manual (DESSIS, 2004).

8) Y. Taur and T. H. Ning: Fundamentals of Modern VLSI Devices (Cambridge University Press, Cambridge, U.K., 1998).

9) D. S. Havaldar, G. Katti, N. DasGupta, and A. DasGupta:IEEE Trans. Electron Devices 53 (2006) 737.

10) G. Pei, J. Kedzierski, P. Oldiges, M. Ieong, and E. C. Kan: IEEE Trans. Electron Devices 49 (2002) 1411.

11) T. Ohtou, N. Sugii, and T. Hiramoto: Proc. Silicon Nanoelectronics Workshop, 2006, p. 15.

12) International Technology Roadmap for Semiconductors [http:// www.itrs.net/].

13) T. Mizuno, J. I. Okamura, and A. Toriumi:IEEE Trans. Electron Devices 41 (1994) 2216.

14) N. Sano, K. Matsuzawa, A. Hiroki, and N. Nakayama:Jpn. J. Appl. Phys. 41 (2002) L552.

15) S. Toriyama and N. Sano:Physica E 19 (2003) 44.