Characterization of the low temperature activated N(+)/P junction formed by implant into silicide method

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Characterization of the low temperature activated N

+

/P junction formed

by implant into silicide method

Kow-Ming Chang

*

, Jian-Hong Lin, Chih-Hsiang Yang

Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, 1001 Ta Hsueh Road, Hsinchu 30050, Taiwan, ROC

1. Introduction

For future MOS device fabrication, shallow junction is a necessary requirement. The shallow junction formed by the implant into silicide (IIS) method has been discussed in many researchers using SIMS, current–voltage (I–V) methods[1,2], and most results show that the junction formed by IIS method is suitable for nano-scaled devices manufacturing. However, few literatures have mentioned the inner process of the junction formation about the IIS method. There are two possibilities may explain why IIS method can provide high activation ability at low activation temperature. First, the silicidation process (ﬁrst RTA) will create a thin amorphous silicon layer below silicide/silicon due to the process-induced stress[3]. This thin layer may just play the role which like the implanted induced amorphous layer in the traditional solid phase epitaxial regrowth (SPER)[4,5]process. An important concept of the SPER process is that dopant activated in amorphous silicon can be activated at a quantity higher than their thermal solubility in crystal silicon at same activation temperature [6]. This factor may provide a good explaining about the high activation ability of SPER method and so as IIS method. And secondly, nickel silicide can reduce the energy required for amorphous silicon to regrowth to crystal silicon[7],

this phenomenon is what the so-called metal-induced crystal-lization[8], which is famous in TFT industry. The second factor provides lower temperature requirement to active dopant than traditional SPER process. In this work, we follow these two assumptions and combine the SIMS, I–V, C–V, and four points probe measurements to study the junction formation behavior of the IIS method.

2. Device fabrication

Thirty-nanometer silicon dioxide was thermally grown on (1 0 0) p-type silicon wafer as the isolation oxide, after defining the active region, a 20-nm nickel film was then deposited by E-gun evaporation system. All samples were treated with first RTA 350 8C 30 s, after un-reacted Ni was removed, all samples were ion implanted with phosphorous (doping density: 5 1015_cm 2_),

followed different second RTA temperature treatments 60 s from 400 8C to 650 8C, 50 8C per step. At the ﬁnal step, Al was thermally coated as back contact. No post-metal annealing was treated for thermal budget control consideration.

3. Results and discussions 3.1. C–V measurement

The effective phosphorous concentration (Neff) estimated from

C–V measurement [9] is demonstrated inFig. 1. The measured capacitance is composed by of three different capacitances in

Applied Surface Science 254 (2008) 6155–6157

A R T I C L E I N F O Article history:

Available online 18 March 2008 PACS:

61.72.Tt 81.20. n Keywords: Nickel silicide Implant into silicide Solid phase epitaxial regrowth Rapid thermal anneal

A B S T R A C T

Shallow junction formation and low thermal budget control are important for advanced device manufacturing. Implant into silicide (IIS) method is a candidate to achieve both requirements. In this work we show that the high activation ability of the implant into nickel silicide method at low activated temperature is strongly related to the solid phase epitaxial regrowth (SPER) process. The SIMS, capacitance–voltage (C–V), four points probe (FPP), and current–voltage (I–V) measurements are combined to demonstrate that the SPER process of the IIS method is starting from the silicide/silicon (M/ S) interface. The best N+_{/P interface is formed when SPER is complete. After SPER process ﬁnished,}

additional thermal budget may cause junction performance degradation at the temperature higher than 550 8C.

* Corresponding author. Tel.: +886 3 5712121x54205; fax: +886 3 5724361. E-mail address:kmchang@faculty.nctu.edu.tw(K.-M. Chang).

C o n t e n t s l i s t s a v a i l a b l e a tS c i e n c e D i r e c t

Applied Surface Science

j o u r n a l h o m e p a g e : w w w . e l s e v i e r . c o m / l o c a t e / a p s u s c

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series, silicide/silicon (M/S) junction capacitance, N+_{/P junction}

capacitance, and back contact capacitance. Based on the results in Ref.[10], it shows that there present high dopant activation level at the M/S interface formed by IIS method, either it will become an ohmic contact or exits a relative large capacitance compared to the N+_{/P junction capacitance where the lightly doped substrate}

dominate the small capacitance value. The M/S capacitance term could be neglect with little inﬂuence in the analysis. On the other hand, the area of the back contact is about the full wafer size, which is several orders of magnitude larger than the area of N+_{/P junction,}

so the capacitance at the back contact can also not take into consideration. As the result, the measured capacitance was mainly contributed due to p-subdepletion junction at the N+_{/P junction.}

From analyzing the C–V data, the p-subdoping density can be obtained from the differential capacitance–voltage proﬁling technique[9].Fig. 1shows the relationship between the depletion capacitance and the applied reverse voltage, the building voltage of the N+_{/P junction can be obtained from the projection of the 1/C}2_–V

curve to where 1/C2_{= 0. The high linearity of the 1/C}2_{–V curve}

implies that the abruptness of the N+_{/P junction is good and using}

abrupt junction formula to express the experimental results is suitable. The Neffis then calculated from the averaged substrate

doping density and the building voltage. The relation of Neffto the

second RTA temperature is shown inFig. 2, it seems that the Neff

presents at the N+/P interface is negatively related to the second RTA temperature. The lowest Neffextracted at this study is above

1019_cm 3_{, which is four order larger than the substrate doping}

density. This supports the assumption that the capacitance measured is mainly due to the depletion in substrate at the N+_/

P junction.

3.2. FPP and SIMS measurements

Some papers appointed that defects might cause dopant deactivated [11,12] at higher RTA temperature. However, from the study about the M/S junction[10], we did not ﬁnd signiﬁcant deactivation to take place at the silicide/silicon interface at the same process window in this study. In order to make sure the origin of the decreased Neff, a test structure designed for FPP

measurement is used. By removing NiSi using silicide etch solution (the etch selectivity of NiSi to bare Si is larger than 50), the results of measured resistance are displayed inFig. 3. It shows that the resistances become smaller with higher second RTA temperatures, which means that either doping concentration or the junction depth is extended at higher second RTA temperature. With the assistance of SIMS proﬁle inFig. 4, suggesting that the lower Neff

Fig. 1. An example of the measured 1/C2_{–V curve, the sample was treated with}

second RTA 650 8C 60 s.

Fig. 2. Phosphorous doping density estimated from C–V measurement with different second RTA temperatures.

Fig. 4. SIMS proﬁle of phosphorous-doped sample treated with second RTA 650 8C 60 s.

Fig. 3. Resistance measured by four points probe method. K.-M. Chang et al. / Applied Surface Science 254 (2008) 6155–6157

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measured at higher temperature is mainly due to that where the N+_{/P interface presented are at the deeper position away from}

the M/S interface. The result implies that the dopant activation behavior is starting from the NiSi/Si interface extended to the silicon substrate. If the high activated doping concentration is related to the SRER process as we assumed, it is recommended that the SPER process is starting from the M/S interface. As a consequence of C–V, FPP, and SIMS measurements, the suggested phosphorous activation behavior of the IIS method is illustrated in Fig. 5.

3.3. I–V measurement

In addition to analyze the junction forming behavior, I–V measurement are adapted. The N+/P diode I–V measurement results are summarized as Jon(at VA= 1 V) and Joff(at VA= 2 V)

exhibited in Fig. 6. The sample with second RTA 550 8C 60 s treatment has the lowest Joffvalue among all samples. The high Joff

current densities presented at second RTA temperature below

500 8C are explained as that there may exist high defect densities at the P/N junction interface. The defects may originate from the remained amorphous region where is still not recrystallized due to the short activation time or the low activation temperature. As the result, with increasing second RTA temperatures, the SPER process continuous going, and the Joffcurrents decreased. At second RTA

550 8C 60 s, the SPER process seen to be completed (this can be observed by the relative consistent resistances measured in FPP method, seeFig. 3), the sample exhibits the maximum on/off ratio. However, the on/off ratios (Fig. 5) and Neff (Fig. 2) diminish at

second RTA higher than 550 8C 60 s. Since the SPER process looks like completed above second RTA 550 8C 60 s, the facts described above may originated by defect (dislocations start to form at the temperature range from 500 8C to 600 8C[13]) itself or by some defect-induced dopant deactivation at the P+_{/N interface. In}

addition, deactivation from phosphorous super-saturated solubi-lity to thermal equilibrium solubisolubi-lity in silicon[14]might also play an important role when the thermal budget is higher than which required for SPER process completion. (The experiments of thermal stability about dopant super-saturated will be given in future publication.)

4. Conclusion

With the starting idea that SPER is the main response to the high activation ability with IIS method in low activation temperature, we combine the SIMS, C–V, FPP, and I–V measurements to construct the doping activation behavior of the IIS method. All experiment results suggested that SPER process is starting from the M/S interface and extend into the silicon substrate. The best N+_/P

interface is formed when SPER process is complete. After SPER process ﬁnished, samples with additional thermal budget treat-ment above 550 8C cause the defect formation at the bulk silicon and the dopant deactivation phenomenon may occur, both factors will decay the N+_{/P junction’s performance. Sample treated with}

second RTA 550 8C 60 s forms the best N+/P junction among all controls in this study.

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Fig. 5. The behavior of phosphorous activation is shown schematically. The P/N junction interface becomes deeper away from M/S interface with higher second RTA temperature.