Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology

Design of dynamic-¯oating-gate technique for output ESD

protection in deep-submicron CMOS technology

Hun-Hsien Chang

_{, Ming-Dou Ker}

_{, Jiin-Chuan Wu}

a_{Integrated Circuits and Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan} b_{VLSI Design Division, Computer and Communication Research Laboratories (CCL), Industrial Technology Research Institute}

(ITRI), U400, 195-11, Section 4, Chung-Hsing Road, Chutung, Hsinchu 310, Taiwan Received 13 May 1998; received in revised form 19 June 1998

Abstract

A novel dynamic-¯oating-gate technique is proposed to improve ESD robustness of the CMOS output bu€ers with small driving/sinking currents. This dynamic-¯oating-gate design can e€ectively solve the ESD protection issue which is due to the di€erent circuit connections on the output devices. By adding suitable time delay to dynamically ¯oat the gates of the output NMOS/PMOS devices which are originally unused in the output bu€er, the human-body-model (machine-model) ESD failure threshold of a 2-mA output bu€er can be practically improved from the original 1.0 kV (100 V) up to greater than 8 kV (1500 V) in a 0.35-mm bulk CMOS process. # 1998 Elsevier Science Ltd. All rights reserved.

1. Introduction

Electrostatic discharge (ESD) robustness of CMOS IC's had been founded to be seriously degraded by the advanced deep-submicron CMOS technologies [1±3]. It is necessary to improve ESD protection for the output bu€ers through either process modi®cation or more e€ective ESD protection circuit design [4]. In the TSMC (Taiwan Semiconductor Manufacturing Company) 0.35-mm CMOS technology, two extra pro-cess modi®cations had been used to improve ESD robustness of the output bu€ers. One is the modi®ed ESD-implant process and the other uses the resist-pro-tection-oxide (RPO) layer to block the silicided di€u-sion in the output bu€ers [5].

The lightly-doped-drain (LDD) structure had been used to reduce the electrical ®eld around the drain region and therefore to overcome the hot-carrier e€ect of the short-channel transistors in submicron and deep-submicron CMOS technologies. The schematic cross-sectional view of an output NMOS with the LDD structure is shown in Fig. 1(a). But, the LDD structure has a di€usion peak extending from the drain region into the channel. Due to the peak-discharging

e€ect in the ESD events, the ESD current is often dis-charged through the LDD peak structure of the drain. Owing to the much shallow junction depth of the LDD structure, the drain of the output NMOS is easily damaged by the ESD current to cause a very low ESD reliability [1±3]. To improve ESD robustness of the output NMOS, the ESD-implant process had been widely used to eliminate the LDD peak structure in the output NMOS [3, 4]. The schematic cross-sec-tional view of the output NMOS with the convencross-sec-tional ESD-implant process is shown in Fig. 1(b), which is similar to the early long-channel device with a deeper junction depth. In the ESD-implanted output NMOS, the channel length has to be enlarged to reduce the hot-carrier e€ect on the output NMOS. Such an ESD-implanted output NMOS has a di€erent device par-ameters to those having the LDD structure. So, the ad-ditional HSPICE parameters of the ESD-implanted output NMOS have to be extracted for circuit simu-lation.

In the TSMC 0.35-mm CMOS technology, a modi-®ed ESD-implant process is used to lowered the junc-tion breakdown voltage of the drain juncjunc-tion, which is under the drain contact [5]. The schematic cross-sec-0038-1101/98/$19.00 # 1998 Elsevier Science Ltd. All rights reserved.

tional view to illustrate the output NMOS with the modi®ed ESD-implant process is shown in Fig. 1(c), where the ESD implantation is deeply implanted into the drain junction only around the drain contact to lower the junction breakdown voltage from the orig-inal 8 V to 6.5 V. The output NMOS with the modi-®ed ESD-implant process still keeps the LDD structure and a shorter channel length. The lower breakdown voltage of the modi®ed ESD-implanted drain junction causes the ESD current to be discharged through the modi®ed ESD-implanted drain region, which is far away from the LDD peak and the channel of the out-put NMOS. So, the modi®ed ESD-implant process can e€ectively improve the ESD robustness of the output NMOS and still keep the LDD structure in the

short-channel output NMOS to achieve better hot-carrier re-liability.

To improve the operating speed of the integrated circuits in the deep-submicron CMOS technology, the silicided di€usion had been widely used to reduce the sheet resistance of the drain and source of the MOSFET. The sheet resistance of the silicided N+ di€usion in the 0.35-mm CMOS process is only 3.39 O/ square, whereas the non-silicided N+ di€usion in the same process has a sheet resistance of 87 O/square. The schematic cross-sectional view of an NMOS with the silicided di€usion is illustrated in Fig. 2(a). Such silicided di€usion can e€ectively improve the operating speed of the CMOS circuits. But, if the silicided di€u-sion is used in the output bu€ers, the ESD current Fig. 1. The schematic cross-sectional views of (a) the output NMOS device with the LDD structure, (b) the output NMOS with the conventional ESD-implant process and (c) the output NMOS with the modi®ed ESD-implant process.

coming from the output pad is diverted into the drain region and only ¯ows on the drain surface with the low-resistance silicided di€usion. The ESD current ¯owing through the drain surface easily touches the drain LDD peak structure and the channel of the out-put NMOS to cause a much lower ESD robustness. In the non-silicided di€usion process, a suitable layout spacing about 3±5 mm from the drain contact to the poly-gate edge is often used to improve ESD robust-ness of the output bu€ers [6]. But, in the silicided di€u-sion process, even a wider spacing from the drain contact to the poly-gate edge still can not improve

ESD level of the output bu€ers due to the much low sheet-resistance of silicided di€usion on the drain sur-face.

The process modi®cation in the TSMC 0.35-mm CMOS technology to overcome the negative impact of silicided di€usion on ESD protection is to use an extra resist-protection-oxide (RPO) layer to block the sili-cided di€usion in the output transistors [5]. The sche-matic cross-sectional view of the silicided-blocking output NMOS is shown in Fig. 2(b). A ®nger-type lay-out example to realize the silicide-blocking lay-output NMOS by using the extra RPO mask layer is shown in

Fig. 2. (a) The schematic cross-sectional view of an NMOS device with the silicided di€usion, (b) the schematic cross-sectional view of an NMOS device with the silicide-blocking di€usion and (c) a layout style for using the RPO layer to block the silicided di€u-sion in the output NMOS.

Fig. 2(c). The RPO mask layer provides the output NMOS with the non-silicided di€usion in both the drain and source of the output NMOS to rescue ESD level of the output bu€er. An output NMOS with a device dimension (W/L) of 420/0.5 (mm/mm) and a spa-cing from the drain contact to poly-gate edge of 3.4 mm in the 0.35-mm CMOS process without process modi®cation for ESD protection fails to the human-body-model (HBM) ESD stress of 2 kV. But, if the RPO layer and the modi®ed ESD-implant process are used, such an output NMOS can sustain the HBM

ESD stress of above 5 kV. This shows the e€ectiveness of ESD protection through the advanced process modi®cations.

Besides the advanced process modi®cations to improve ESD robustness of the output bu€ers, the symmetrical layout structure is much emphasized to realize the large-dimension output transistors by ensur-ing the uniform turn-on phenomenon along the mul-tiple ®ngers of the output transistor [7]. To more enhance the uniform turn-on phenomenon among the multiple ®ngers of the output transistors, a

gate-Fig. 3. (a) The schematic layout of an output NMOS in a cell library with a small driving speci®cation. (b) The equivalent circuit of the layout in (a) with a small-driving-current NMOS Mn1 and a large-dimension but unused NMOS Mn2.

coupled design had been reported to achieve uniform ESD power distribution on the large-dimension output transistors [8±12]. But in the practical applications, the output bu€ers in a cell library have di€erent driving speci®cations. For example, the output bu€ers may have the driving capability of 2, 4, 8, . . . or 24 mA. But, the cell layouts of the output bu€ers with di€erent driving capabilities are still drawn in the same layout style and area for programmable application. To adjust di€erent output sinking (driving) currents of the output bu€er, di€erent ®ngers of the poly gates in the output NMOS (PMOS) are connected to the pre-bu€er circuit, but the other unused poly-gate ®ngers are con-nected to ground (VDD). A typical layout example of the ®nger-type output NMOS with a small driving cur-rent is shown in Fig. 3(a), whereas the equivalent cir-cuit is shown in Fig. 3(b). In Fig. 3(a), there are 10 poly-gate ®ngers in the NMOS layout, but only a poly-gate ®nger (Mn1) is connected to the pre-bu€er circuit to provide the sinking current from the output pad. The other 9 poly-gate ®ngers (Mn2) are connected to ground to keep the NMOS (Mn2) o€ which is unused but inside the cell layout of the output bu€er. Due to the asymmetrical connection on the poly-gate ®ngers of the output NMOS in the layout, the ESD turn-on phenomenon among the ®ngers becomes quite di€erent even if the layout in Fig. 3(a) is so symmetri-cal. The output Mn1 is often turned on ®rst and damaged by the ESD voltage, whereas the unused Mn2 with a much larger channel width is always o€ during the ESD stress. This generally causes a very low ESD level for the output bu€er, even if the output bu€er has a very large total device dimension (Mn1 + Mn2).

In this paper, a novel dynamic-¯oating-gate tech-nique is proposed to improve ESD level of the output bu€ers with di€erent driving speci®cations in the cell library [13]. The gates of the unused NMOS/PMOS in the output bu€er are dynamically ¯oated during the ESD stress, so such unused NMOS/PMOS with large device dimensions can be turned on in time to bypass the ESD current. Thus, the overall ESD level of such output bu€ers can be signi®cantly improved.

2. Traditional gate-coupled output ESD protection The ESD test to verify the ESD level of an output pin is shown in Fig. 4, where there are four modes of testing combinations from the output pin to the VDD or VSS pins [14]. In the ND-mode (PS-mode) ESD stress, the output PMOS (NMOS) is reverse biased and broken down by the ESD voltage. But, in the NS-mode (PD-NS-mode) ESD stress, the parasitic drain-to-bulk diode in the NMOS (PMOS) is forward biased to bypass the ESD current. Due to the low operating vol-tage, the diode in the forward-biased condition can sustain much high ESD stress. However, the NMOS or PMOS in the breakdown condition with high snap-back voltage are easily damaged by the ESD energy. Thus, the worst cases of the ESD stresses on an output bu€er are the ND- and PS-mode ESD events.

To enhance the turn-on uniformity of the output bu€ers by using the traditional gate-coupled technique, the poly gates of the unused NMOS (PMOS) in the output bu€ers are connected to VSS (VDD) through a small-dimension NMOS Mdn1 (PMOS Mdp1) [11], as shown in Fig. 5. The Mdn1 (Mdp1) cooperated with

the parasitic drain-to-gate capacitance in the Mn2 (Mp2) performs the gate-coupled e€ect to turn on the Mn2 (Mp2) during the ESD stress [10±12]. In the nor-mal operating conditions, the gate of Mp2 (Mn2) is connected to VDD (VSS) through the turned-on Mdp1 (Mdn1) to keep the unused Mp2 (Mn2) o€. For an output bu€er with a smaller driving/sinking current, such as only 2 mA, the device dimension of the Mn1 (Mp1) is much smaller than that of the Mn2 (Mp2). In a 0.35-mm CMOS cell library, the 2-mA output bu€er has the device dimension (W/L) of 30/0.5 (mm/mm) for both the Mn1 and Mp1. But, in the cell layout of the 2-mA output bu€er, it also has the device dimension of 450/0.5 (690/0.5) for the Mn2 (Mp2). The device dimensions of the Mdn1 and Mdp1 are both designed as 20/0.35 (mm/mm).

In the PS-mode ESD stress shown in Fig. 4, the VDD is ¯oating and the VSS is relatively grounded. When the PS-mode ESD voltage attaches the output pad of Fig. 5, some transient voltage is coupled through the parasitic drain-to-gate capacitor to the gates of Mn1 and Mn2. The coupled voltage is expected to be held on the gates of Mn2 by the Mdn1. Therefore, the unused Mn2 with a large device dimen-sion is expected to be turned on to bypass the ESD current from the pad to VSS. However, the positive ESD voltage on the pad is also diverted into the VDD power line through the parasitic diode Dp2 (Dp1) in the Mp2 (Mp1). The Mdn1 with its gate connected to the VDD power line is quickly turned on during the PS-mode ESD transition. The coupled voltage on the gate of Mn1 is held on its gate, but the coupled vol-tage on the gate of Mn2 is discharged by the turned-on Mdn1. During the ESD transititurned-on, the Mn1 with a

smaller device dimension is actually triggered on and damaged by the ESD energy but the large-dimension Mn2 with the gate-coupled design is still kept o€. On the other hand, in the ND-mode ESD stress, the coupled voltage on the gate of Mp2 is discharged by the turned-on Mdp1, because the negative ESD voltage on the pad is conducted into the VSS power line through the parasitic diode Dn2 (Dn1) in the Mn2 (Mn1) to turn the Mdp1 on. The ND-mode ESD cur-rent is still mainly discharged through the Mp1 with a smaller device dimension. Thus, such an output bu€er with the gate-coupled design still has a very low ESD level even if the modi®ed ESD-implant process and silicided-blocking di€usion are used in the output buf-fer.

The output bu€ers with di€erent driving/sinking cur-rent speci®cations are tested in the HBM (human-body-model) ESD event by the Zapmaster ESD tester. The advanced process modi®cations with both the modi®ed ESD-implant process and the silicide-blocking di€usion are used in all the output bu€ers. The PS-mode and ND-PS-mode ESD test results are summarized in Table 1. Due to the di€erent connections on the gates of the output Mn1 and the unused Mn2, the PS-mode ESD level of the 2-mA output bu€er is only 1 kV. But the 8-mA output bu€er can sustain the PS-mode ESD voltage of 2 kV. While the driving/sinking current of the output bu€er is increased with a larger device dimension on Mn1, the output bu€er has a higher ESD level (>2.5 kV). Although the cell layout areas and the total device dimensions (Mn1 + Mn2) of these output bu€ers (2 mA, 4 mA, . . .) are all the same in the cell library, the ESD level of these output bu€ers are quite di€erent. Even if using the NMOS

Fig. 5. The output bu€er of a small driving/sinking current in a 0.35-mm cell library. The gate of the unused Mn2 (Mp2) is con-nected to VSS (VDD) through a small-dimension Mdn1 (Mdp1) to perform the gate-coupled e€ect for ESD protection.

Mdn1 (PMOS Mdp1) to perform the gate-coupled e€ect to help the uniform turn-on between the Mn1 and Mn2 (Mp1 and Mp2), the HBM ESD level of the output bu€er with a small Mn1 (Mp1) but a large Mn2 (Mp2) is still below the general industrial HBM ESD speci®cation of 2000 V. Detailed failure analysis by de-layer process is applied to ®nd the ESD failure location on a 4-mA output bu€er which is stressed and damaged by a PS-mode ESD voltage of 2 kV. The SEM picture of the ESD failure on the 4-mA output bu€er is shown in Fig. 6(a), where the ESD damage indicated by an arrow is located on the Mn1 device of the output bu€er. The ESD damage in Fig. 6(a) is zoomed in and shown in Fig. 6(b). The ®ngers of the Mn2 device have no ESD damage in the de-layered output bu€er.

To investigate the gate-coupled e€ect in more details, the 2-mA output bu€er with the circuit con-®guration in Fig. 5 is simulated by HSPICE. In the HSPICE circuit simulation, a ramp voltage with a rise time of 10 ns and a pulse height of 7 V is applied to the output pad to simulate the rising edge of the HBM PS-mode ESD voltage. The pulse height in the simu-lation is set as 7 V to ®nd the gate-coupled e€ect before the drain of the output NMOS is broken down by the ESD voltage, because the drain breakdown vol-tage of NMOS in the 0.35-mm CMOS process is about 8 V. The rise time of an HBM ESD pulse has been speci®ed as 2 to 10 ns in the EOS/ESD association standard [14], therefore the rise time of the stress vol-tage in the HSPICE simulation is set as 10 ns. The in-itial voltage at all nodes of the circuit in Fig. 5 is set to 0 V before the ESD-simulated ramp voltage is applied to the output pad. The simulated gate-coupled voltage waveforms on the gates of Mn1 and Mn2 are shown in Fig. 7(a), whereas the simulated drain current waveforms in the time domain through the Mn1 and Mn2 are shown in Fig. 7(b). During the simulation time period from 10 to 20 ns, the applied ramp voltage is risen from 0 to 7 V. The coupled voltage on the gate of Mn1 is kept at about 0.56 V, but the coupled vol-tage on the gate of Mn2 is discharged by the Mdn1 to 0 V. In Fig. 7(b), the drain current of Mn1 is increased and kept at about 61 mA. The raising edge of the ramp voltage generates the transient current about 300±400

mA through the parasitic capacitance of the Mn2, but after the rising transition the drain current of Mn2 is dropped to zero. Because the coupled voltage on the gate of Mn2 is discharged by the Mdn1, the Mn2 is almost o€ during the PS-mode ESD transition. The traditional gate-coupled design on the Mn2 with the Mdn1 device can not really turn the Mn2 on before the Mn1 is triggered on in such CMOS output bu€ers.

Similar simulation is also applied to investigate the turn-on behavior during the ND-mode ESD stress on the output bu€er of Fig. 5. A ramp voltage with a fall time of 10 ns and a pulse height of ÿ7 V is used to simulate the falling edge of the HBM ND-mode ESD voltage before the output bu€er is broken down by the ESD voltage. During the ND-mode ESD stress, the VDD is grounded but the VSS is ¯oating. The initial voltage at all nodes is also set as 0 V before the ND-mode ESD voltage is applied to the output pad. The simulated voltage waveforms on the gates of Mp1 and Mp2 are shown in Fig. 8(a), whereas the simulated drain current waveforms of Mp1 and Mp2 are shown in Fig. 8(b). After the triggering of the 10-ns falling edge, the gate voltage of Mp1 is kept at about ÿ0.69 V but that of the Mp2 is returned to 0 V. In Fig. 8(b), The 10-ns falling edge of the simulated ND-mode ESD voltage generates a peak transient current about ÿ750 mA on the drain of Mp2. After the falling-edge trigger-ing, the drain current of Mp2 is returned to zero but that of Mp1 is kept at about ÿ8.5 mA. This veri®es that the gate-coupled design in Fig. 5 can not really turn the Mp2 on to bypass the ND-mode ESD cur-rent.

Through the detailed investigation, the HSPICE simulation and ESD test results have proved that the traditional gate-coupled design in Fig. 5 by only using the Mdn1 (Mdp1) to hold the coupled voltage on the gate of Mn2 (Mp2) can not improve ESD robustness of the output bu€ers. Such output ESD protection issue due to di€erent connections on the gates of the output Mn1 (Mp1) and the unused Mn2 (Mp2) can not be improved by only using the advanced process modi®cations. Some circuit design technique has to be invented to really improve ESD robustness of the out-put bu€ers with di€erent driving/sinking currents in a cell library.

Table 1

The human-body-model (HBM) ESD level of the output bu€er protected by the traditional gate-coupled design (Fig. 5)

HBM ESD stress Output bu€ers (kV)

2-mA bu€er 4-mA bu€er 8-mA bu€er 12-mA bu€er 24-mA bu€er ND-Mode 1.5 2 2.5 > 2.5 > 2.5 PS-Mode 1.0 1.5 2.0 > 2.5 > 2.5

Fig. 6. (a) The SEM picture of the ESD damage location on the Mn1 of a 4-mA output bu€er in the 0.35-mm CMOS process. (b) The zoom-in picture to show the ESD damage located on the Mn1 due to the PS-mode ESD stress with the HBM ESD voltage of 2 kV.

3. Output ESD protection with the dynamic-¯oating-gate technique

As shown in Section 2, the low ESD level of an out-put bu€er with a small driving/sinking current is due to the loss of the gate-coupled voltage on the gates of

the unused Mn2 and Mp2 during ESD transition. If the gate-coupled voltage can be really held on the gates of the Mn2 and Mp2, the output bu€er with a small driving/sinking current but with the unused Mn2 and Mp2 of large device dimensions can be e€ectively improved.

Fig. 7. (a) The simulated voltage waveforms on the gates of Mn1 and Mn2 and (b) the simulated drain current waveforms of Mn1 and Mn2, in the output circuit of Fig. 5, due to the triggering of a PS-mode ESD voltage with a rise time of 10 ns and a pulse height of 7 V.

3.1. Circuit con®guration

The proposed dynamic-¯oating-gate technique to improve ESD robustness of a small-driving output buf-fer is shown in Fig. 9. As compared to the gate-coupled output bu€er in Fig. 5, two additional MR2

and MC2 devices are designed to dynamically ¯oat the gate of Mp2 during the ND-mode ESD-stress con-dition, but the gate of Mp2 is connected to VDD in the normal operating condition. Two additional MR1 and MC1 devices are also used to dynamically ¯oat the gate of Mn2 during the PS-mode ESD-stress con-Fig. 8. (a) The simulated voltage waveforms on the gates of Mp1 and Mp2 and (b) the simulated drain current waveforms of Mp1 and Mp2, in the output circuit of Fig. 5, due to the triggering of a ND-mode ESD voltage with a fall time of 10 ns and a pulse height of ÿ7 V.

dition, but the gate of Mn2 is connected to VSS in the normal operating condition. The MC1 and MC2 devices are functioned as the capacitors and the MR1 and MR2 devices are functioned as the resistors. Because the gate of Mn2 (Mp2) is ¯oated in a time period during the PS-mode (ND-mode) ESD tran-sition, the coupled voltage through the drain-to-gate capacitance can be really held on the gate of Mn2 (Mp2) to turn on the Mn2 (Mp2) to bypass ESD cur-rent. Because the Mn2 and Mp2 have large device dimensions, the turned-on Mn2 and Mp2 can sustain a much higher ESD level. Therefore, the ESD robustness

of the output bu€ers in the 0.35-mm cell library can be signi®cantly improved.

A practical layout example of a 2-mA output bu€er with the dynamic-¯oating-gate design is demonstrated in Fig. 10. The additional MR1 and MR2 have the device dimension (W/L) of 1.7/45 (mm/mm) to perform a high resistance and the MC1 and MC2 have the device dimension of 65/8 (mm/mm) to perform a high capacitance to realize the dynamic-¯oating-gate design. The typical cell layout of the 2-mA output bu€er in a 0.35-mm SPQM CMOS process occupies a total layout area of only 84  235 mm2 _{which includes the double}

guard rings to prevent latchup issue.

Fig. 9. The dynamic-¯oating-gate design to improve ESD level of the small-driving output bu€ers in a 0.35-mm cell library.

3.2. The dynamic-¯oating-gate mechanism

In the PS-mode ESD stress, the positive ESD vol-tage is applied to the output pad with grounded VSS but VDD is ¯oating. Due to the sharp rising edge of the ESD voltage, the gates of Mn2 and Mn1 are coupled with some positive voltage through the drain-to-gate parasitic capacitance in the Mn2 and Mn1. During the PS-mode ESD stress, the positive ESD vol-tage on the pad is also diverted into the ¯oating VDD power line through the parasitic diode Dp2 (Dp1) in the Mp2 (Mp1). The drain of MR1 is therefore charged by the ESD voltage on the VDD power line. The gate-grounded PMOS MR1 functions as a resistor to charge the gate of Mdn1. The NMOS MC1 func-tions as a capacitor to store the gate voltage of Mdn1. Initially, the voltage stored on the capacitor MC1 is zero before the ESD voltage is applied to the output pad. But, the voltage stored on the capacitor MC1 is increased through the MR1 after the VDD power line is charged by the ESD current through the Dp2 and Dp1. The speed of the increase on the gate voltage, which is stored on the MC1, is strongly dependent on the RC time constant of the resistor MR1 and the ca-pacitor MC1. The MR1 is especially designed with a high resistance and the MC1 is drawn with a large ca-pacitance. Such design causes the gate voltage of Mdn1 to be kept below its threshold voltage in a long time. Because the Mdn1 is kept o€ in a long time, the gate of the unused Mn2 is therefore dynamically ¯oated in the corresponding time period. A larger resistor MR1 and a lager capacitor MC1 lead to a longer time period to ¯oat the gate of the unused Mn2. By using this dynamic-¯oating-gate design, the coupled voltage through the drain-to-gate capacitance of Mn2 can be held on the gate of Mn2 in an enough long time period. So, the unused Mn2 with a large device dimension in the small-driving output bu€er can be instantaneously turned on to bypass ESD current from the output pad to VSS. Owing to the e€ective turn-on of the unused large-dimension Mn2, the PS-mode ESD level of such a small-driving output bu€er can be signi®cantly improved.

In the ND-mode ESD stress, the negative ESD vol-tage is applied to the output pad with grounded VDD but VSS is ¯oating. The negative ESD voltage on the pad is diverted into the ¯oating VSS power line through the parasitic diode Dn2 (Dn1) in the Mn2 (Mn1). The NMOS MR2 with its gate connected to VDD functions as a resistor, whereas the PMOS MC2 functions as a capacitor. The negative ESD voltage on the VSS power line charges the gate of Mdp1 through the MR2. The speed of the decrease on the gate vol-tage of Mdp1 is strongly dependent on the RC time consist of the resistor MR2 and the capacitor MC2. A high-resistance MR2 and a large-capacitance MC2 are

therefore designed to keep the Mdp1 o€ in a longer time, so the gate of the unused Mp2 can be dynami-cally ¯oated in a longer time period. The dynamic-¯oating time on the gate of Mp2 can be adjusted by simply changing the RC time constant of the resistor MR2 and the capacitor MC2. By this dynamic-¯oat-ing-gate design, the negative ESD-coupled voltage through the drain-to-gate capacitance of Mp2 can be held on the gate of Mp2 in an enough long time period. So, the unused Mp2 with a large device dimen-sion can be instantaneously turned on to bypass the negative ESD voltage from the output pad to the grounded VDD. Owing to the turn-on of the unused large-dimension Mp2, the ND-mode ESD level of such a small-driving output bu€er can be signi®cantly improved.

3.3. HSPICE simulation

To investigate the eciency of the dynamic-¯oating-gate technique in the 2-mA output bu€er, the output circuit is simulated by the HSPICE. The device dimen-sions of the 2-mA output bu€er including the ad-ditional devices to realize the dynamic-¯oating-gate design have been described in Section 3.1.

3.3.1. PS-mode ESD-stress condition

An ESD-like ramp voltage pulse is added to the out-put pad with a pulse height of 7 V and a rise time of 10 ns to simulate the rising edge of the PS-mode ESD voltage. The transient voltages on the gates of Mn1 and Mn2 are monitored and shown in Fig. 11(a), whereas the discharging currents through the drains of Mn1 and Mn2 are shown in Fig. 11(b). As comparing to the simulation waveforms in Fig. 7, the dynamic-¯oating-gate design really keeps the transient-coupled voltage on the gate of Mn2. The coupled voltages on the gate of Mn1 in Fig. 7(a) and Fig. 11(a) are still the same, but those on the gate of Mn2 between the Fig. 7(a) and Fig. 11(a) are quite di€erent. The gate voltage of Mn2 in Fig. 11(a) can be risen up to 0.96 V, therefore the Mn2 can be turned on to provide a drain current of 52.2 mA in Fig. 11(b). Such a drain current of 52.2 mA in the Mn2 is due to the triggering of a 7-V ramp voltage to simulate the turn-on behavior of the 2-mA output bu€er with the dynamic-¯oating-gate design. In the real ESD events, the ESD voltage can be up to several thousands volts with the ESD current in the order of several Amperes. With such high ESD voltage and current, the Mn2 is triggered into the snapback region to bypass the ESD current. The simu-lation waveforms shown in Fig. 11 are only used to prove that the coupled voltage can be actually held on the gate of Mn2 during the rising edge of the ESD vol-tage. So, the Mn2 can be guaranteed to be quickly

turned on to discharge ESD current before the Mn1 is damaged by the ESD voltage.

The turn-on time of Mn2, shown in Fig. 11(a), is de®ned as the time period when the coupled voltage on the gate of Mn2 is greater than its threshold

voltage. The threshold voltage of NMOS in the 0.35-mm SPQM CMOS process under 3.3 V bias is 0.65 V. The turn-on time of Mn2 due to the 7-V PS-mode vol-tage triggering is about 33.7 ns. A higher ESD volvol-tage on the pad couples a higher voltage to the gate of Fig. 11. (a) The transient voltages on the gates of the output Mn1 and the unused Mn2 and (b) the discharging currents through the output Mn1 and the unused Mn2, during the PS-mode simulation on the 2-mA output bu€er with the dynamic-¯oating-gate design.

Mn2 and also causes a longer turn-on time on the Mn2. Changing the device dimensions of the MR1 and MC1 can modify the RC time constant in the dynamic-¯oating-gate design, therefore the turn-on time of Mn2 can be adjusted. The simulation results on the turn-on time of Mn2 by changing the channel length and width of MR1 with a ®xed W/L of 65/8

(mm/mm) in the MC1 are shown in Fig. 12(a). The MR1 with a longer channel length or a narrower chan-nel width leads to a longer turn-on time on the Mn2 due to the 7-V PS-mode voltage triggering. As shown in Fig. 12(a), the turn-on time of Mn2 is linearly dependent on the channel length and the channel width of MR1. The dependence of the turn-on time of

Fig. 12. The simulation results on the variation of the turn-on time in Mn2 by (a) changing the channel length and width of MR1 with a ®xed W/L of 65/8 (mm/mm) in the MC1 and (b) changing the gate area (W  L) of MC1 under di€erent W/L of the MR1, during the PS-mode simulation on the 2-mA output bu€er with the dynamic-¯oating-gate design.

Mn2 on the gate area (W  L) of MC1 due to the 7-V PS-mode triggering is shown in Fig. 12(b) with di€er-ent device dimensions of the MR1. In Fig. 12(b), the

turn-on time of Mn2 is linearly dependent on the gate area of the MC1 in the output bu€er with the dynamic-¯oating-gate design. A larger gate area of

Fig. 13. (a) The transient voltages on the gates of the output Mp1 and the unused Mp2 and (b) the discharging currents through the output Mp1 and the unused Mp2, during the ND-mode simulation on the 2-mA output bu€er with the dynamic-¯oating-gate design.

MC1, which provides a larger capacitance, leads to a longer turn-on time on the Mn2. Because the turn-on time of Mn2 is linearly dependent on the device dimen-sions of the MR1 and MC1, it is easy to adjust the turn-on time of Mn2 for di€erent applications by simply changing the device dimensions in the cell lay-out.

3.3.2. ND-mode ESD-stress conduction

The turn-on behavior of a 2-mA output bu€er with dynamic-¯oating-gate design in the ND-mode ESD-stress condition is also simulated by HSPICE. An ESD-like ramp voltage with a pulse height of ÿ7 V and a fall time of 10 ns is applied to the output pad of Fig. 9 to simulate the falling edge of the ND-mode ESD voltage, while the VDD is relatively grounded but the VSS is ¯oating. The simulated gate voltages and the drain currents on the output Mp1 and the unused Mp2 are shown in Fig. 13(a) and (b), respect-ively. The coupled voltage on the gate of Mp1 in Fig. 13(a) is the same as that in Fig. 8(a), but the gate voltage of Mp2 in Fig. 13(a) is quite di€erent to that in Fig. 8(a). The coupled gate voltage in Fig. 13(a) has a peak value of ÿ1.2 V but that in Fig. 8(a) is only ÿ0.27 V. The dynamic-¯oating-gate design causes the main di€erence on the coupled gate voltage of Mp2 in the output bu€er. As compared to the simulation results in Fig. 8(b), the Mp2 in the output bu€er with the dynamic-¯oating-gate design has a signi®cant drain current during the ND-mode simulation in Fig. 13(b). Such simulation results have theoretically veri®ed that the dynamic-¯oating-gate design can really hold the coupled voltage on the gate of Mp2 to quickly turn on the Mp2 during the ND-mode ESD stress. Due to the large device dimension of Mp2, the Mp2 can sustain much higher ESD voltage than the output Mp1. By using this dynamic-¯oating-gate design, the Mp2 can be turned on in time to bypass ESD current before the Mp1 is damaged by the ESD voltage. Therefore, the ESD level of the small-driving output bu€er can be signi®cantly improved by the Mp2 with the dynamic-¯oating-gate design.

The turn-on time of Mp2 is de®ned as the time period when the negative coupled voltage on the gate of Mp2 is lower than its threshold voltage of ÿ0.75 V. In Fig. 13(a), the turn-on time of Mp2 due to the trig-gering of the ND-mode simulation with a pulse voltage of ÿ7 V is about 20.5 ns. A larger ESD voltage on the pad couples more voltage to the gate of Mp2 and causes a longer turn-on time on the Mp2. The turn-on time of Mp2 can be also adjusted by changing the device dimensions of the MR2 and MC2 to modify the RC time constant in the dynamic-¯oating-gate design. The simulation results on the turn-on time of Mp2 by

changing the channel length and width of MR2 with a ®xed W/L of 65/8 (mm/mm) in the MC2 are shown in Fig. 14(a). The dependence of the turn-on time of Mp2 on the gate area (W  L) of MC2 due to the ÿ7 V ND-mode triggering is shown in Fig. 14(b) under di€erent device dimensions of MR2. As shown in Fig. 14(a) and (b), the turn-on time of Mp2 is linearly dependent on the channel length of MR2 and the gate area of the MC2. The MR2 with a narrower channel width has a higher resistance to cause a longer turn-on time on the Mp2. The turn-on time of Mp2 is linearly dependent on the device dimensions of the MR2 and MC2, so the turn-on time of Mp2 can be easily adjusted by simply changing the device dimensions of such devices in the cell layout.

3.3.3. Normal-operating tri-state condition

In Fig. 9, the dynamic-¯oating-gate design is used to impermanently ¯oat the gate of Mn2 (Mp2) to hold the transient-coupled voltage on the gate of Mn2 (Mp2) under the ESD-stress conditions, therefore the unused Mn2 (Mp2) can be turned on betimes to bypass the PS-mode (ND-mode) ESD current away from the small-dimension output Mn1 (Mp1). But in the normal operating conditions with the 3.3-V VDD and 0-V VSS biases, the gate of Mdn1 (Mdp1) in Fig. 9 is biased at VDD (VSS) through the turned-on MR1 (MR2). So, the Mdn1 (Mdp1) with a device dimension of 20/0.35 is fully turned on to keep the gate voltage of Mn2 (Mp2) at VSS (VDD). The Mn2 (Mp2) has to be guaranteed o€ when the output bu€er is in the normal operating conditions. In some bi-direction I/O applications, the output bu€er may be operated in the tri-state condition, where both the out-put Mp1 and Mn1 are kept o€ and the outout-put pin becomes an input pin. Under such a tri-state con-dition, the input signal with a sharp rising/falling edge on the pad may trigger on the unused Mn2 or Mp2 in the output bu€er with the dynamic-¯oating-gate de-sign. To clearly verify this point, the output bu€er in Fig. 9 is also simulated by the HSPICE in the tri-state condition. An input voltage waveform with both the rise time and fall time of only 2 nS and the pulse height of 3.3 V is applied to the output pad under the tri-state condition. The coupled voltages on the gates of Mn2 and Mp2 are monitored and shown in Fig. 15. The coupled gate-to-source voltage of the Mn2 (Mp2) due to the rising-edge triggering from the input signal is only 11 mV (ÿ84 mV), whereas the coupled gate-to-source voltage of the Mn2 (Mp2) due to the falling-edge triggering is only ÿ11 mV (85 mV). Such coupled gate-to-source voltage on the Mn2 (Mp2) is much smaller than its threshold voltage, so the Mn2 (Mp2)

is guaranteed o€ in the tri-state condition. Moreover, the overshooting (undershooting) voltage pulse attached to the pad can be clamped by the parasitic drain diode Dp2 (Dn2) in the Mp2 (Mn2), when the output bu€er is in the normal operating conditions.

Thus, the Mn2 (Mp2) in the output bu€er with the dynamic-¯oating-gate design is not triggered on by the sharply rising or falling voltage waveforms on the pad. This dynamic-¯oating-gate design on the output bu€er does not destroy the output function at all, but it Fig. 14. The simulation results on the variation of the turn-on time in Mp2 by (a) changing the channel length and width of MR2 with a ®xed W/L of 65/8 (mm/mm) in the MC2 and (b) changing the gate area (W  L) of MC2 under di€erent W/L of MR2, during the ND-mode simulation on the 2-mA output bu€er with the dynamic-¯oating-gate design.

can e€ectively improve ESD robustness of the output bu€er.

4. Experimental results

The output bu€ers with the dynamic-¯oating-gate design have been designed and fabricated in a 0.35-mm SPQM CMOS process. The human-body-model (HBM) ESD test results of the output bu€ers in Fig. 5 with the traditional gate-coupled design has been listed in Table 1. For an output bu€er with a higher driving/ sinking current, the Mn1 and Mp1 in the output bu€er have larger device dimensions, which can sustain higher ESD stress. So, the output bu€er in Table 1 with higher driving/sinking current has a higher ESD level. The HBM ESD test results of the output bu€ers in Fig. 9 with the proposed dynamic-¯oating-gate

de-sign are listed in Table 2. The Mn1, Mp1, Mn2 and Mp2 devices in both the output bu€ers of Figs. 5 and 9 have the same modi®ed ESD-implanted drain region and silicide-blocking di€usion. The HBM ND-mode (PS-mode) ESD level of the 2-mA output bu€er with the traditional gate-coupled design in Fig. 5 is only 1.5 kV (1.0 kV). But, the HBM ND-mode (PS-mode) ESD level of the 2-mA output bu€er with the same device dimensions can be improved greater than 8 kV (8 kV) by using the dynamic-¯oating-gate design. In Table 2, the dynamic-¯oating-gate design is not used in the out-put bu€ers with the driving/sinking current greater than 12 mA, because the device dimension of the out-put Mn1 (Mp1) is greater than that of the unused Mn2 (Mp2). With a current speci®cation greater than 12 mA, the Mn1 (Mp1) has a device dimension greater than 240/0.5 (360/0.5), which can sustain the HBM ESD level of greater than 8 kV under the help of the Fig. 15. The simulated gate-to-source voltages of the Mn2 and Mp2 in Fig. 9 due to the triggering of a voltage pulse attached to the output pad with a rise/fall time of 2 ns and a pulse height of 3.3 V when the output bu€er is operating in the tri-state con-dition.

Table 2

The human-body-model (HBM) ESD level of the output bu€er protected by the proposed dynamic-¯oating-gate design (Fig. 9)

HBM ESD stress Output bu€ers (kV)

2-mA bu€er 4-mA bu€er 8-mA bu€er 12-mA bu€er 24-mA bu€er ND-Mode > 8 > 8 > 8 > 8 > 8 PS-Mode > 8 > 8 > 8 > 8 > 8

modi®ed ESD-implant process and the silicided-block-ing di€usion.

The machine-model (MM) ESD test results of the 2-mA output bu€ers between the designs in Figs. 5 and 9 are compared in Table 3. The 2-mA output bu€er with the traditional gate-coupled design in Fig. 5 can sustain the MM PS-mode (ND-mode) ESD level of only 100 V (150 V), but the 2-mA output bu€er with the dynamic-¯oating-gate design in Fig. 9 can pass the MM ESD stress of 1500 V. These ESD test results have further veri®ed the e€ectiveness of the proposed dynamic-¯oating-gate design to improve the ESD robustness of the output bu€er with a small-dimension output Mn1 (Mp1) but a large-dimension unused Mn2 (Mp2).

The output bu€ers with the dynamic-¯oating-gate design are also tested by the ®eld-induced charged-device-model (CDM) ESD stress. Such output bu€ers with di€erent driving speci®cations from 2 mA to 24 mA in the 0.35-mm CMOS process can sustain the ®eld-induced CDM ESD voltage of greater than 4 kV. 5. Conclusion

A dynamic-¯oating-gate design has been successfully used to improve ESD level of the small-driving output bu€ers. The gates of the unused NMOS/PMOS in the output bu€ers are dynamically ¯oated during the ESD stress, so the unused NMOS/PMOS with large device dimensions can be instantaneously turned on to bypass the ESD current. The theoretical principles and the operating mechanism of the dynamic-¯oating-gate de-sign to improve ESD robustness of the output bu€er

have been explained in details and veri®ed by HSPICE simulation. The turn-on time of the unused NMOS/ PMOS in the output bu€er can be linearly adjusted by changing the device dimensions in the ing-gate circuit. By using the proposed dynamic-¯oat-ing-gate design, the HBM ND-mode (PS-mode) ESD level of the 2-mA output bu€er in a 0.35-mm CMOS process has been signi®cantly improved from the orig-inal 1.5 kV (1.0 kV) up to greater than 8 kV. The MM ND-mode (PS-mode) ESD level of the 2-mA output bu€er has been also e€ectively improved from the orig-inal 150 V (100 V) up to greater than 1500 V. This dynamic-¯oating-gate design has been practically used in TSMC 0.35-mm and 0.25-mm CMOS cell libraries to service the ASIC's which are manufactured in TSMC. Acknowledgements

This work was supported by the Design Service Division in Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan, under the con-tract of C87084.

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Table 3

The machine-model (MM) ESD level of the 2-mA output bu€er

MM ESD

stress Output bu€ers (V) 2-mA bu€er with

traditional gate-coupled design (Fig. 5)

2-mA bu€er with dynamic-¯oating-gate design (Fig. 9) ND-Mode 150 1600 PS-Mode 100 1500