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(3) A Low-Dropout Regulator with Negative Active-Feedback Frequency Compensation. . . . . . . .

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(6) A Low-Dropout Regulator with Negative Active-Feedback Frequency Compensation. .

(7). . . StudentPo-Hsuan Huang. . . AdvisorChung-Chih Hung . . A Thesis Submitted to Department of Communication Engineering College of Electrical Engineering and Computer Science National Chiao Tung University in partial Fulfillment of the Requirements for the Degree of Master in Communication Engineering January 2006 Hsinchu, Taiwan, Republic of China. . . . . . . . . . . .

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(15) Abstract The thesis describes low-dropout regulator with negative active-feedback frequency compensation. It is divided into three parts. The first part of this thesis discusses three-stage operational amplifiers. Using current-reused technique fits the demand of low-power dissipation. It improves the shortcoming of the conventional Nested-Miller Compensation (NMC) skill. This circuit has been fabricated by TSMC 0.35- m N-well CMOS process. Under almost the same performance of CRNMC and NMC amplifiers, the power dissipation is reduced to half of NMC amplifiers. Another three-stage op-amp is proposed by negative active-feedback frequency compensation (NAFFC) techniques. The compensation technique exploits the negative active–feedback path to create a left-half-plane (LHP) zero. By means of the LHP zero adding positive phase, it can cancel out the negative phase-shift pole. At the mean time, a feedforward path is added to the NAFFC amplifier to obtain the better frequency-domain and time-domain performance. Moreover, only one compensation capacitor is needed and no additional transistors are required with comparison to the nested-Miller compensation (NMC) topology. This circuit has been fabricated by TSMC 0.18- m CMOS process. The second part of this work discusses how to implement the MOSFET-only voltage reference circuit. The current source of the core circuit mirrors the current coming from a self-biased circuit. This self-biased circuit can compensate the channel-length modulation effect where drain current is increased with supply voltage. Especially in the advanced process, the channel-length modulation effect is becoming more and more prominent when channel length is shorter. Moreover, by means of the characteristics of the subthreshold region, the reference voltage independent of temperature is obtained. This circuit has been implemented in TSMC 0.35- m N-well CMOS process. The final part of this work presents the low-dropout (LDO) regulator. The circuit combines the negative active-feedback frequency compensation skill and the voltage reference circuit. In order to make certain the system is stable, using the negative active-feedback path creates a LHP zero to compensate the pole. And the voltage ii.

(16) reference circuit generates the voltage independent of supply voltage and temperature. It is the input voltage of the LDO regulator. . iii.

(17) Acknowledgment I extend my sincere appreciation to my advisor, Professor Chung-Chih Hung, who provides me considerable freedom in my research. Besides, I would like to thank all the members in the Analog Integrated Circuit Laboratory. I would thank National Chip Implementation Center for providing the TSMC CMOS 0.18 m and 0.35 m SPICE model and chip fabrication. Finally, I would like to express my greatest appreciation to my parents for their without end encouragement and support.. iv.

(18) Table of Contents Chapter 1 Introduction…………………………………………………………………………..1 1.1 Introduction………………………………………………………………....1 1.2 Multistage amplifiers………………………………………………………..2 1.3 Voltage reference circuits…………………………………………………...3 1.4 Low-dropout regulators……………………………………………………..4 Chapter 2 A Low-Power Multistage Operational Amplifier with Current-Reused Technique………………………………………..........................................................5 2.1 Introduction…………………………………………………………..……..5 2.2 Nested-Miller Compensation……………………………………………….5 2.3 Current-Reused NMC……………………………………………………….7 2.4 Simulation and Experimental Results............................................................8 Chapter 3 Negative Active-Feedback Frequency Compensation Technique for Multistage Amplifiers……………………………………………………………….13 3.1 Introduction………………………………………………………………..13 3.2 Proposed Negative Active-Feedback Frequency Compensation Amplifier.13 3.2.1 Topology………………………………………...…………14 3.2.2 Small-signal analysis………………………………………15 3.2.3 Stability issues…………..…………………………………16 3.2.4 Slew rate and settling time………………………………...18 3.2.5 Circuit description…………………………………...…….19 3.3 Simulation and Experimental Results………………………………..……19 Chapter 4 A Self-Biased CMOS Voltage Reference Based on Weak Inversion Operation……………………………………………………………………………23 4.1 Introduction…………………………………………………………..……23 4.2 Sensitivity Formulas……………………………………………………….23 v.

(19) 4.3 General Principles of Bandgap Votlage Reference………………………..25 4.4 Subthreshold Characteristics of MOSFET………………………………...25 4.5 Self-Biased Voltage Reference Circuit…………………………………….26 4.5.1 Self-biased circuit………………………………………….27 4.5.2 Compensation of channel-length effect……………………28 4.5.3 Output reference voltage………….……………………….30 4.6 Experimental Results………………………………………………………31 Chapter 5 A Low-Dropout Regulator with Negative Active-Feedback Frequency Compensation …………………………………………………………………...….35 5.1 Introduction…………………………………………………………..……35 5.2 Brief review of LDO regulators……………………………………………35 5.3 The proposed LDO regulators……………………………………………..36 5.3.1. Without off-chip capacitor and ESR………………………37 5.3.2. With off-chip capacitor and ESR………………………….39 5.4 Circuit descriptions………………………………………………………..42 5.5 Simulation results……………...…………………………………………..42 Chapter 6 Conclusions……………………………………………………………...47 References……………………………………………………………………….......49. vi.

(20) List of Tables Table 2-1: NMC amplifier with different g m 3 …………………………...…………...7 Table 2-2: Comparison of NMC and CRNMC amplifiers…………………………...12 Table 3-1 Performance of NAFFC amplifier………………………………………...20 Table 3-2: Comparison of different multistage amplifiers…………………………...22 Table 4-1: Performance summary……………………………………………………34. vii.

(21) List of Figures Figure 1-1:. Power management of the mobile phone.…………………...………...2. Figure 2-1:. Block diagram of the NMC amplifier…………………………...…….6. Figure 2-2:. Illustration of the current-reuse technique……………………..….…..7. Figure 2-3:. Schematic of the NMC amplifier………………………………….…..8. Figure 2-4:. Schematic of the CRNMC amplifier…………………………………..9. Figure 2-5:. Chip photo of the NMC and CRNMC amplifiers…………….……….9. Figure 2-6:. The frequency response of the NMC amplifier………………...…….10. Figure 2-7:. The frequency response of the CRNMC amplifier…………………...10. Figure 2-8:. Transient responses of input step and (a) NMC (b) CRNMC……..…11. Figure 3-1:. Block diagram of the NAFFC amplifier.……………………………..14. Figure 3-2:. Equivalent small-signal circuit of the NAFFC amplifier…….……….14. Figure 3-3:. The pole and GBW locations (a) without zero (b) with zero……...….16. Figure 3-4:. Schematic of the NAFFC amplifier…………….…………………….18. Figure 3-5:. Chip photo of the NAFFC amplifier……………….….……………...19. Figure 3-6:. Simulated frequency response of the NAFFC amplifier with 25k //100pF load. (a) Magnitude response (b) Phase response……..21. Figure 3-7:. Transient Response of the NAFFC amplifier in unit-gain feedback topology with a 0.5-V step input………………..………………...….22. Figure 4-1:. General principles of bandgap voltage reference……………………..24. Figure 4-2:. MOS subthreshold characteristics. [23]..………………………....…..25. Figure 4-3:. The structure of the self-biased CMOS voltage reference…………....27. Figure 4-4:. Block diagram of a self-biased reference……………………………..27. Figure 4-5:. Definition of operating point…………………………………………28. Figure 4-6:. Determination of channel-length modulation reduction……………..29. Figure 4-7:. Chip photo…………………...……………………………………….31. Figure 4-8:. Start-up time of voltage reference circuit………………...…………..32 viii.

(22) Figure 4-9:. The steady-state reference voltage………………….………………...32. Figure 4-10: Comparison of reference voltage with and without compensation of channel-length modulation effect……………………...……………..33 Figure 4-11: Experimental reference voltage versus supply voltage at room temperature…………………...………………………………………33 Figure 4-12: Experimental reference voltage versus temperature for VDD = 1.3 V……………………………………………………………………...34 Figure 5-1:. Topology of conventional LDO regulator………………………...….36. Figure 5-2:. Topology of proposed LDO regulator……………..…………………37. Figure 5-3:. Open-loop gain of LDO regulator without COUT and ESR (a) Magnitude response (b) Phase response. The load current is 0 (solid line) and 80 (dash line) mA………………………………………………………..40. Figure 5-4:. Open-loop gain of LDO regulator with COUT = 10 F and Re = 0.1 (a) Magnitude response (b) Phase response. The load current is 0 (solid line) and 80 (dash line) mA…………………………………………..41. Figure 5-5:. The schematic of proposed LDO regulator…………………………...42. Figure 5-6:. Chip photo……………………………………………………………43. Figure 5-7:. Output voltage of LDO regulator vs. load current……………………43. Figure 5-8:. Load transient response without off-chip capacitor as load current is varied from 0 to 80 mA………………………………………………44. Figure 5-9:. Load transient response with COUT = 10 F and ESR = 0.1. as load. current varied from 0 to 80 mA………………………………………44 Figure 5-10: Load transient response with COUT = 10 F as output current is varied from 0 to 80 mA. For the ESR, the resistance Re is 0.1, 0.3, 0.5, 1 and 2 ……………………………………………………………………45 Figure 5-11: Power-supply rejection of the regulator for 10-mA load current (a) without off-chip capacitor (b) with COUT = 10 F and ESR = 0.1 ....46. ix.

(23) Chapter 1. Introduction. 1.1 INTRODUCTION The power management is a very important issue today because the mobile electronics are getting more and more popular than ever before. The need for capacity and lifetime of laptop batteries or cell phones are required a lot. However, it isn’t suitable to add another battery to our system that is contradictive to the small area demand. Figure 1-1 shows the power management of the mobile phone. It monitors to reduce the standby power consumption and the low-dropout regulator (LDO) is a critical part widely used in it. There are some reasons to use the LDO circuits. First, because the battery supplies a very noisy voltage leading to the internal circuits suffering the noise influences. It separates the voltage between the battery and the different sub-circuits. Next, it isolates the different subsystems from each other. This is really significant between the analog and digital circuits or in the RF section. Finally, it reduces the sensitivity between the circuitry and the transient voltage changes or ripples of the battery. So in order to provide a low-noise output voltage with high efficiency, it has been widely used like a bridge cascading a switching power supply. This thesis includes six chapters. Due to the architecture of the LDO regulator consists of the voltage reference circuit and the similar three-stage operational amplifier. First of all we describe two different topologies of op-amp in Chapter 2 and 3. Chapter 2 introduces the Current-Reused NMC (CRNMC) to lower the power of consumption. Chapter 3 demonstrates a negative active-feedback frequency compensation (NAFFC) technique. By means of pole-zero cancellation to obtain the wider bandwidth. Chapter 4 discusses MOSFET-only voltage reference circuit. This circuit consumes less power and provides a high precision reference voltage. The. 1.

(24) . Figure 1-1. Power management of the mobile phone.. LDO circuit which combines the NAFFC amplifier and voltage reference circuit is presented in detail in Chapter 5. Chapter 6 gives a conclusion.. 1.2 MULTISTAGE AMPLIFIERS

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(60) . Nested-Miller compensation (NMC) amplifier is the most well known topology in the early periods. This configuration is based on the theory of pole-splitting 2.

(61) technique and is not limited to finite stages. However, it sacrifices the bandwidth as increasing the amplification stages to achieve the high dc gain [8]. Another problem is the output stage needs lots of sinking current to maintain the stability leading to be inapplicable in the low-power design. As such, some recent designs use the feedforward technique to maximize the amplifier bandwidth like multipath nested Miller compensation (MNMC) [2] and nested Gm − C compensation (NGCC) [3] or to remove the Miller capacitors such as no-capacitor feedforward (NCFF) amplifier [9]. The other approaches are recommended to enhance the bandwidth by means of removing the capacitive feedback paths at the output. Without the feedback paths, the novel measures should be provided to make sure an amplifier stable. As a result, damping-factor-control frequency compensation (DFCFC) [10] and dual-loop parallel compensation (DLPC) [11] were reported. A DFCFC amplifier uses damping-factor-control (DFC) block to choose the complex-pole locations and a DLPC amplifier utilizes two parallel paths to propagate high-frequency signals. These two schemes can ensure the stability and achieve the wider bandwidth simultaneously. Moreover, the active-feedback frequency-compensation (AFFC) technique [12] replace passive-capacitive-feedback networks by active-capacitive-feedback ones to reduce the physical size of compensation capacitors and improve the transient responses. Outstanding bandwidth improvement was proposed in single Miller capacitor feedforward frequency (SMCFF) compensation [13]. A SMCFF topology is based on pole splitting and pole-zero cancellation to obtain better small-signal and large-signal performances.. 1.3 VOLTAGE REFERENCE CIRCUITS For the most analog and digital circuits such as low-dropout regulators (LDO), A/D and D/A converters, DRAM and flash memories, a voltage reference is a necessary part. In order to make certain that these circuits could work reliably, the reference voltage should be extremely precise and stable. An ideal voltage reference must be insensitive to the external influences that come from power supply, temperature and process variations. A bandgap voltage reference is usually used. Some researches focus on small-area [17] or low-voltage operation [18] [19], however,. 3.

(62) all of them require big-area diodes or parasitic BJT transistors with turn-on voltage as high as 0.6V at room temperature. In the contrast of BJT, the CMOS process is getting more and more prevalent and it has the advantages of smaller area and lower cost. Thus, MOSFET-only voltage reference circuits are presented [20]-[22] and by means of operating MOSFET in the subthreshold region [20] [21] to obtain a low-voltage low-power voltage reference.. 1.4 LOW-DROPOUT REGLATORS As advanced technology is nonstop progressing, the demands for low power and small area are getting stringent. That makes the LDO regulators become the prevalent part of the portable electronic devices. Comparatively speaking, the LDO regulators are easier to integrate in the system-on-chip (SOC) design than switching regulators. Although the latter one achieves the efficiency higher than 80 %, the off-chip inductors and capacitors must be required. Moreover, the LDO regulators produce the stable voltage insensitive to the varying load currents and reduce the voltage ripple. So it’s suitable to cascade with a switching regulator to improve the performance and stability of the whole system. LDO regulators [25]-[29] have been widely used to isolate the different subsystems from each other, especially for SOC design. It separates the analog and digital blocks of the system to prevent the crosstalk problem. In addition, the low quiescent current of LDO regulators increases the battery life of cellular phones, laptops and digital cameras.. 4.

(63) Chapter 2. A Low-Power Multistage Operational Amplifier with Current-Reused Technique. 2.1 INTRODUCTION In this chapter, the technique for low-power amplifier design is proposed when still maintaining the same bandwidth of the NMC amplifier. In the following section, a three-stage NMC amplifier is discussed. The low-power design to improve NMC is given in Section 2.3 and then simulation and experimental results are presented in Section 2.4.. 2.2 NESTED-MILLER COMPENSATION The general structure of the NMC op amp is shown in Figure 2-1, where. g m1 ~ g m 3 are the transconductances of the amplification stages 1~3, Ro1 ~ Ro 3 are the output resistances, C1 ~ C2 and CL are the parasitic and loading capacitors, respectively, and the compensation capacitors are Cm1 ~ Cm 2 . According to Leung et al. [5] and [8], the NMC amplifier in the unity-gain feedback architecture should have the third-order Butterworth frequency response. The dimension of Cm1 and Cm 2 can be approximated as [8]. Cm1 = 4. g m1 CL g m3. (2-1). Cm 2 = 2. gm2 CL g m3. (2-2). 5.

(64) Ro1 Figure 2-1. C1. Ro2. C2. Ro3. CL. Block diagram of the NMC amplifier.. and the gain-bandwidth product (GBW) is given by [8]. GBW=. 1 gm3 4 CL. (2-3). Under the above compensation, the phase margin (PM) is about 60° and the first pole is located at ω3-dB = −1 g m 2 g m 3 Ro1 Ro 2 Ro 3Cm1 . The nondominant complex poles. are ωp2, 3 = − ( g m 3 2CL ) ± j ( g m 3 2CL ) and the damping factor of the complex poles 2.. is 1. The stability analysis is carried out based on the following assumptions: 1). The positions of the zeroes must locate at higher frequency than the poles. 2). The gain of each stage is larger than one. 3). The parasitic capacitances are smaller than the compensation and loading ones. 4). The transconductance of the output stage g m 3 is much larger than g m1 and. gm2 . It should be noted that a NMC amplifier is more stable when g m 3 >> g m1 and. g m 2 comes into existence. However, the higher transconductance represents the transistor should sink more current than any other’s, so it causes the NMC amplifier hardly achieve the low-power design. Table 2-1 lists different g m 3 values with distinct capacitor dimensions, GBW 6.

(65) . I. . . I 2. I. W 2 L. . I 2. I 2. W 2 L. W L. W 2 L. (a). W 2 L. (b) Figure 2-2. (c). Illustration of the current-reuse technique.. and current consumption of the output stages according to Equations (2-1)-(2-3). From simulation and process parameters, the third amplification stage of W L = 160. and. µnCox ≈ 200 A/V are proposed. In fact, the current dissipation of the output. stage is proportional to g m 3 , and so is GBW; However, the required compensation capacitance to maintain stability decreases with g m 3 . The following section provides a technique to maintain large g m 3 , but at the same time the sinking current reduces almost a half.. TABLE 2-1 NMC AMPLIFIER WITH DIFFERENT g m 3. ( CL = 100 pF, µn Cox ≈ 200 A/V and (W L )3 = 160 ). g m1. gm2. gm3. Cm 2. GBW. (pF). (pF). (MHz). 500. 80. 20. 0.2. 3.9. 1000. 40. 10. 0.4. 15.6. 2000. 20. 5. 0.8. 62.5. 3000. 13.3. 3.3. 1.2. 140.6. ( A/V) ( A/V) ( A/V). NMC. 100. 50. Output-stage. Cm1. current ( A). 2.3 CURRENT-REUSED NMC The purpose of the current-reuse technique [16] is to achieve the transconductance of a single device with less current. The derivation is illustrated in 7.

(66) VIN+. VIN-. Figure 2-3. Schematic of the NMC amplifier.. Figure 2-2. Figure 2-2(a) shows that a NMOS transistor has a dimension ratio W L. and drain current I D where g m1 = 2 I D µn Cox (W L )1 . To obtain the same g m , the. two NMOS transistors are in parallel with aspect ratio (1 2 ) W L and drain current. (1 2 ) I D. in Figure 2-2(b). Thus the equivalent transconductance could be expressed. by g m ,eq = g m1 + g m 2 = 2 I D µ n Cox (W 2 L )1 = 2 I D µn Cox (W L )1 . Finally, in Figure. 2-2(c), a PMOS transistor is folded to substitute for the device M2 in Figure 2-2(b). The. above. equation. is. then. modified. to. g m ,eq = I D µ n Cox (W 2 L )1 + I D µ p Cox (W 2 L )2 which is smaller than g m of single. transistor in Figure 2-2(a) because the mobility µn of NMOS is nearly three times than µ p of PMOS. But the current is reduced to half as compared with Figure 2-2(a). From Table I, if g m 3 equals to 3000 A/V , the output-stage current is 140.6 A. Using the current-reuse technique, the current can be decreased to 70.3 A. By means of this technique, the power consumption is reduced to half, but still suitable for high GBW application. The detailed circuit structures of NMC and CRNMC are shown in Figure 2-3 and Figure 2-4, respectively. The only difference is the transistor M10 of the NMC amplifier is now substituted by M101 and M102 in the CRNMC amplifier.. 2.4 SIMULATION AND EXPERIMEATAL RESULTS 8.

(67) VIN-. VIN+. Figure 2-4. Figure 2-5. Schematic of the CRNMC amplifier.. Chip photo of the NMC and CRNMC amplifiers.. In order to confirm the proposed technique, the post-layout simulations are presented using the TSMC 0.35 m CMOS technology. The circuit parameters of the NMC amplifier are g m1 = 125 A/V , g m 2 = 80 A/V , g m 3 = 3260 A/V , Cm1 = 16pF ,. Cm 2 = 4.5pF and CL = 100pF . The measured power consumption equals to 352 W which is larger than 155 W of the CRNMC amplifier. The rest of the performance indexes are nearly the same for the two amplifiers. The chip photo of the NMC and CRNMC amplifiers are shown in Figure 2-5. Figure 2-6 and 2-7 illustrate the frequency response of both amplifiers. Their dc gain are close to 100dB and PM’s are both about 60° . The step responses and settling time of the amplifiers were simulated by 0.5 9.

(68) Vp-p input steps. The slew rate is about 0.25 V/ s and 1% settling time is nearly to 3.5. s. Figure 2-8 shows the transient responses of the two amplifiers. The. performance of NMC and CRNMC amplifiers are listed in Table 2-2 for comparison.. 100. Phase (degree). 80 60 40 Gain (dB). 20 0 -20 10. 3. 10. 4. 10. 5. 10. 6. Frequency (Hz). Figure 2-6. The frequency response of the NMC amplifier.. 100. Phase (degree). 80 60 40 20. Gain (dB). 0 -20 10. 3. 10. 4. 10. 5. 10. 6. Frequency (Hz). Figure 2-7. The frequency response of the CRNMC amplifier.. 10.

(69) (a). (b) Figure 2-8. Transient responses of input step and (a) NMC (b) CRNMC.. 11.

(70) TABLE 2-2 COMPARISON OF NMC AND CRNMC AMPLIFIERS Parameter. NMC. Supply voltage. CRNMC. 1.5V. 100pF25k. Load. Gain (dB). 98.5. 102. PM. 61.1°. 57.2°. GBW (MHZ). 0.899. 0.952. 352. 155. 0.333 / -0.133. 0.128 / -0.377. 1.54 / 4.61. 4.64 / 2.84. 0.045. 0.045. Current consumption ( A). SR + /SR − (V/ s) +. TS /TS Area. −. ( s) 2. ( mm ). 12.

(71) Chapter 3. Negative Active-Feedback Frequency Compensation Technique for Multistage Amplifiers. 3.1 INTRODUCTION A new topology, the negative active-feedback frequency compensation (NAFFC) scheme, is presented in this chapter. For the purpose of achieving wide bandwidth, it avoids the capacitive feedback paths at the output and using pole-zero cancellation skill. Figure 2-1 shows the conventional NMC amplifier. The compensation capacitor. Cm1 connects the first amplification stage and output stage. According to Miller effect theorem, capacitor Cm1 creates the dominant pole close to very low frequency because of the high gain. This leads to the low gain-bandwidth product. Moreover, the capacitor Cm 2 which connects the second amplification stage and output stage is short when op-amp is operated at high frequency. Consequently, the feedback path results in the lower high-frequency gain [14]. By means of removing these two capacitors, the wide bandwidth is obtained. At the mean time, the output push-pull stage increases the slew-rate. The following sections will make a detailed description. In Section 3-2, the principle of NAFFC technique is discussed. Section 3-3 addresses the simulation and experimental results.. 3.2 PROPOSED NEGATIVE ACTIVE-FEEDBACK FREQUENCY COMPENSATION AMPLIFIER 13.

(72) Figure 3-1. Figure 3-2. Block diagram of the NAFFC amplifier.. Equivalent small-signal circuit of the NAFFC amplifier.. 3.2.1 Topology The proposed topology is shown in Figure 3-1, where only one compensation capacitor is connected between the first and second stage, reducing the feedback capacitive paths at the output so the larger bandwidth can be obtained. However, the second stage providing the positive transconductance results in positive feedback leading the system unstable. For this reason the negative sign should be added to this feedback path and active stage g ma is used to create left-half-plane (LHP) zero. In addition, the feedforward stage g mf not only makes a push-pull stage at the output to improve the transient response but shifts the LHP zero close to low frequency to cancel the second non-dominant pole. 14.

(73) 3.2.2 Small-signal analysis The equivalent small-signal circuit of the NAFFC amplifier is shown in Figure 3-2. In order to simplify the transfer function, the following assumptions should be made. One is that the dc gain of all stage must be greater than one. Another is the parasitic capacitances have to be much smaller than the output load capacitance. Depending on above assumptions, the transfer function can be expressed by. Av ( s ) =. Adc 1 + sCm 1+. s. g mf gm 2 gm3 1+. ω-3dB. +. g C C 1 + s 2 mf m 2 g ma g ma g m 2 g m3. C CC 1 + s 1 + s2 1 2 gm 2 g m 2 g ma. s. ωp2. .. (3-1). From numerator of (3-1), there are two LHP zeros. One of the zeros is at a much higher frequency which doesn’t affect the phase margin of the amplifier due to Cm is greatly larger than C2 . The transfer function can be approximated as a one-zero system. Adc 1 + sCm. Av ( s ) ≈ 1+. s. ω-3dB. 1+. g mf g m 2 g m3. s. ωp2. +. 1 g ma. C CC 1 + s 1 + s2 1 2 gm 2 g m 2 g ma. .. (3-2). where Adc , ω-3dB and ω p 2 are the dc gain, dominant pole and second non-dominant pole, respectively, which are given by. Adc = g m1 g m 2 g m3 Ro1 Ro 2 Ro 3. ω−3dB = −. 1 g m 2 Ro 2 Ro1Cm. ωp2 = −. 1 . Ro3CL. (3-3). (3-4). (3-5). From (3-2), there are a LHP zero, ω z , to boost the phase margin and a pair of 15.

(74) (a). (b) Figure 3-3. The pole and GBW locations (a) without zero (b) with zero.. complex pole ω p 3,4 with quality factor Q , which are given as. ω z = − Cm. g mf g m 2 g m3. ω p 3,4 = Q=. 1 + g ma. −1. (3-6). g ma g m 2 C1C2. (3-7). g m 2 C2 . g maC1. (3-8). 3.2.3 Stability issues Owing to two poles and a pair of complex pole in this system, the gain-bandwidth product (GBW) should be at a low frequency to ensure the stability. However, the LHP zero cancels second non-dominant pole causing the location of GBW moves to a higher frequency. Figure 3-3 shows how to place the pole and zero location to obtain the wide bandwidth. For simplification, we assume the dimensions of the two parasitic capacitors are almost equal, C1 ≈ C2 , and the Q value of the complex pole is 1. 2 which. implies no peaking in the magnitude response. From above assumption and (3-8), the g ma is given as g ma = 2 g m 2 . 16. (3-9).

(75) Moreover, the pole-zero cancellation means. 1. ωz = ω p 2 Cm. g mf gm2 gm3. 1 + g ma. =. 1 Ro 3CL. (3-10). where g mf ≈ g m 3 and applying (3-9) into (3-10), the Cm is calculated as. Cm =. 2 g m 2 Ro 3CL g ma Ro 3CL = . 3 3. (3-11). From (3-11), the dimension of the compensation capacitor is proportional to the output capacitive and resistive loads. Thus, by choosing the smaller g m 2 reduces the size of Cm . After the pole-zero cancellation and from (2-3), (3-3), (3-4) and (3-11), the GBW is given by. GBW =. g m1 g m 3 Ro 3 Cm. =. 3 g m1 g m 3 2 g m 2 CL. =. 6 g m1 GBW( NMC) gm2. .. (3-12). As indicated in (3-12), the GBW of the NAFFC amplifier bases on the distinction between g m1 and g m 2 , so in order to maximize the GBW, g m1 should be designed much lager than g m 2 . Finally, the phase margin (PM) of the NAFFC amplifier is calculated as. PM = 180° − tan. GBW. ω-3dB. − 2 tan. 3 g m1 g m 3C1 ≈ 90° − 2 tan 2 2 g m 2 2CL 17. GBW. ωp3,4. .. (3-13).

(76) Figure 3-4. Schematic of the NAFFC amplifier.. Owing to the small dimensions of C1 and C2 , PM is nearly larger than 60° .. 3.2.4 Slew rate and settling time The feedforward transconductance stage and the third amplification stage form a push-pull output stage which improves the transient response of the NAFFC amplifier. In addition, the feedforward stage also helps to shift a LHP zero to a lower frequency to enhance the driving capability as increasing the value of the loading capacitor. Without this feedforward path, the transfer function is given by. Adc 1 + s. Av ( s ) = 1+. s. ω-3dB. 1+. s. ωp2. Cm g ma. C CC 1 + s 1 + s2 1 2 gm 2 g m 2 g ma. (3-14). where the denominator of (3-14) is the same with (3-2) but the LHP zero is farer. It should be noted that the pole-zero doublet may degrade the settling time and the effect depends on the pole-zero spacing and its frequency [15]. So the transconductances of each gain stages should be chosen precisely to avoid the imperfect pole-zero cancellation.. 18.

(77) 3.2.5 Circuit description The schematic of the NAFFC amplifier is shown in Figure 3-4. The transistors M1-M8 compose of the first folded-cascode stage with a PMOS differential input pair. The second noninverting gain stage consists of transistors M9-M11 and transistor M9 provides the transconductance g m 2 . At the last gain stage, the transistor M13 generates transconductance of g m 3 and M14 provides the feedforward path to improve the phase margin. In the negative active-feedback block, the compensation capacitor connects to the source of transistor M5 opposite to M6, the minor sign could be acquired and M5 is the active-feedback transistor. In fact, the architecture of the NAFFC op amp is easy to implement and extra transistors are not needed with a comparison to the NMC topology.. Figure 3-5. Chip photo of the NAFFC amplifier.. 3.3 SIMULATION AND EXPERIMENTAL RESULTS The proposed NAFFC amplifier was fabricated in TSMC 0.18- m CMOS technology. Figure 3-5 shows the chip photograph of the amplifier. From post-layout simulation, g m1 = 161.9. A/V, g m 2 = 66.1. A/V, g m 3 = 4019.8. A/V, g ma =. 124.8 A/V, g mf = 4630.3 A/V, and Cm = 18 pF. The NAFFC amplifier uses the supply voltage of 1.2-V and has a load of 100 pF connecting in parallel with 25 k . The simulated frequency responses are shown in 19.

(78) Figure 3-6 (a) and (b). The dc gain is larger than 100 dB with phase margin of 64° and GBW of 18.9 MHz. In Figure 3-7, the transient response in unity gain feedback with 0.5-V step input is shown. The average slew rate and 1% settling time are 2 V/ s and 0.985 s, respectively. Table I summarizes the detailed performance. In order to precisely compare different amplifiers, two formulas are used to weigh the tradeoff between gain bandwidth product (GBW), slew rate (SR), load capacitance ( CL ), and power consumption (PC), which are given by [4] [10]. FOMS =. GBW[MHz] ⋅ CL [pF] PC[mW]. (3-15). SR[V/µ s ] ⋅ CL [pF] . PC[mW]. (3-16). FOM L =. Table II presents the comparison results of different multistage amplifiers. The both formulas are also given. Apparently, the NAFFC amplifier has the most excellent performance.. TABLE 3-1 PERFORMANCE OF NAFFC AMPLIFIER Technology. 0.18- m CMOS. Voltage supply. ± 0.6 V. DC gain. 101 dB. Unit-gain frequency. 18.9 MHz. Phase margin. 64°. Positive slew rate. 2.74 V/ s. Negative slew rate. 1.34 V/ s. Positive settling time. 1.18 s. Negative settling time. 0.79 s. Power consumption. 0.239 W. Load. 100 pF //25 k. Area. 0.028 mm2. 20.

(79) 100. Gain (dB). 80 60 40 20 0 1. 10. 2. 10. 3. 10. 4. 10. 5. 10. 6. 10. 6. 10. 10. 7. Frequency (Hz). (a) 0. Phase (degrees). -45. -90. -135. -180 1 10. 10. 2. 3. 10. 4. 10. 5. 10. 10. 7. Frequency (Hz). (b) Figure 3-6 Simulated frequency response of the NAFFC amplifier with 25k //100pF load. (a) Magnitude response (b) Phase response.. 21.

(80) Figure 3-7. Transient Response of the NAFFC amplifier in unit-gain feedback topology with a 0.5-V step input.. TABLE 3-2 COMPARISON OF DIFFERENT MULTISTAGE AMPLIFIERS FOMS. FOM L. (pF). MHz ⋅ pF mW. V/µ s ⋅ pF mW. Technology. 60. 100. 131. 46. 3 GHz fT BJT. 5. --. 20. 14. 71. 2 m CMOS. 6.9@3. 89/48. --. 40. 272. 400. 0.6 m CMOS. 1.8. 0.4@2. 0.82/0.75. 1.12/1.18. 100. 450. 196. 0.8 m CMOS. >100. 2.7. [email protected]. 1/1. 1.4/1.0. 130. 1276. 473. 0.35 m CMOS. Leung [10]. >100. 2.6. 0.42@2. 1.36/1.27. 0.96/1.37. 100. 619. 314. 0.8 m CMOS. Lee [11]. >100. 7. [email protected]. 2.2/4.4. 0.315/0.68. 120. 2545. 1200. 0.6 m CMOS. Lee [12]. >100. 4.5. 0.4@2. 2.20/0.78. 0.42/0.85. 120. 1350. 447. 0.8 m CMOS. Fan [13]. >100. 4.6. 0.38@2. 3.28/1.31. 0.53/0.4. 120. 1453. 725. 0.5 m CMOS. Fan [13]. >100. 9. 0.41@2. 4.8/2.0. 0.58/0.43. 120. 2634. 995. 0.5 m CMOS. >100. 18.9. [email protected]. 2.74/1.34. 1.18/0.79. 100. 7908. 854. 0.18 m CMOS. Gain. GBW. Power. SR + / SR −. TS + / TS −. CL. (dB). (MHz). (mW@Vdd). (V/ s). to 1% ( s). Eschauzier [2]. 100. 100. 76@8. 35. You [3]. 100. 1. 1.4@2. Ng [4]. 102. 47. Leung [5]. >100. Ramos [7]. This work NAFFC. 22.

(81) Chapter 4. A Self-Biased CMOS Voltage Reference Based on Weak Inversion Operation. 4.1 INTRODUCTION As the technology scales down, the channel length reduces a lot. This causes that the channel-length modulation effect has a huge impact on CMOS transistors. For the precise and stable voltage reference circuit, the output voltage must be insensitive to the supply voltage and temperature variation. But shorter channel length is, the much output voltage variation will be. However, using the self-biased circuit structure compensates the drain current increasing as supply voltage to reduce this effect. Leading to a reference voltage independent of supple voltage, temperature and process fluctuation. The following section briefly describes two formulas to qualify the dependence on power supply and temperature. In Section 4.3, the general principle of the bandgap voltage reference is presented to show how to design a reference voltage independent of temperature variation. Section 4.4 discusses the subthreshold characteristics of MOSFET. The new voltage reference circuit structure is shown in Section 4.5. Section 4.6 addresses the simulation and experimental results.. 4.2 SENSITIVITY FORMULAS First of all, we have to qualify the dependence on power supply and temperature [23]. That will let us know the performances of the voltage reference circuits. The concepts of sensitivity and fractional temperature coefficient are presented. VREF stands for the reference voltage and supply voltage is designated as VDD . The 23.

(82) VBE. VREF =VBE + VT. VT = KT. q. Figure 4-1. α General principles of bandgap voltage reference.. sensitivity of VREF versus VDD changing can be written as. STVVDDREF = lim. ∆VDD → 0. ∆VREF / VREF VDD ∂VREF = . ∆VDD / VDD VREF ∂VDD. (4-1). From (4-1), for an ideal voltage reference, it is independent of supple voltage. So the term ∂VREF ∂VDD is equal to zero leading to zero sensitivity. But generally speaking,. the practical value of sensitivity is smaller than 1 100 for voltage reference circuits.. Fractional temperature coefficient. (TCF ). is represented for circuits that are. dependent of the temperature. It is defined as. TCF (VREF ) =. 1 ∂VREF . VREF ∂T. (4-2). As a rule, the fractional temperature coefficient is expressed by ppm/. For a stable reference voltage, the TCF must be less than 50 ppm/.. 24.

(83) Figure 4-2. MOS subthreshold characteristics. [23]. 4.3 GENERAL PRINCIPLES OF BANDGAP VOLTAGE REFERENCE In order to obtain the reference voltage independent of the temperature variation, using opposite temperature coefficients make up for each other. The general principles are shown in Figure 4-1. The pn-junction diode generates the voltage VBE and at room temperature ∂VBE ∂T ≈ −1.5 mV/ °K . Vt is the thermal voltage and equal to. kT q whereas ∂Vt ∂T ≈ +0.087 mV/ °K [23] [24]. By setting the appropriate parameter α , the reference voltage with zero-temperature coefficient can be generated.. 4.4 SUBTHRESHOLD CHARACTERISTICS OF MOSFET Subthreshold region is also known as weak-inversion region. It’s for gate-source voltages less than the threshold voltage but high enough to create a depletion region at the silicon surface. The majority of transistors operating in subthreshold region are for low-power applications. First of all, we discuss the relations between the drain current and gate-source voltage in subthreshold region. When VGS < VTH , the drain current I D is quite small and exhibits an exponential dependence on VGS . Figure 4-2 shows the. 25.

(84) characteristics and this effect can be formulated for VDS greater than roughly 200 mV as [23] [24]. I D = I 0 exp. VGS , ς Vt. (4-3). where ς > 1 is a non-ideal factor and Vt = KT q . If the MOSFET is in subthreshold region, the relation between VGS and VTH as a function of temperature is [21]. VGS (T ) = VTH (T ) + VOFF +. n (T ) n(T0 ). × [VGS (T0 ) − VTH (T0 ) − VOFF ]. T , T0. (4-4). is the subthreshold slope factor and VOFF is a corrective where, n(T ) = 1 + Cd Cox constant term used in BSIM3v3 models. By assuming n(T ) only varied slightly with temperature, which means n(T ) ≈ n(T0 ) , the threshold voltage can be modeled as VTH (T ) = VTH (T0 ) + KT (T T0 −1) , where K T < 0 . Therefore, VGS can be approximated as. VGS (T ) ≈ VGS (T0 ) + K G. T −1 , T0. (4-5). where K G ≅ K T + VGS (T0 ) − VTH (T0 ) − VOFF . The quantity K G is negative, so VGS is decreased with the temperature.. 4.5 SELF-BIASED VOLTAGE REFERENCE CIRCUIT The proposed MOSFET-only voltage reference circuit is shown in Figure 4-3. It can be divided into two parts. One is self-biased circuit composing of transistors M1~M4 and resistor R1 . The other is formed by transistors M6~M8 and resistors R2 and R3 generating the reference voltage VREF .. 26.

(85) Figure 4-3. The structure of the self-biased CMOS voltage reference. VDD. R1 . Figure 4-4. Schematic of a self-biased reference.. 4.5.1 Self-biased circuit Figure 4-4 shows the operation of the self-biased circuit [23]. It should be noted that transistor M4 is operated in the subthreshold region. So the current I1 has an exponential relation to the gate-source voltage VGS 4 which is produced by 27.

(86) ( I 2 + I5 ) × R1 .. From the standpoint of current mirror block, the current I1 is. proportional to I 2 + I 5 . The operating point, which is shown in Figure 4-5, is at the intersection of the two characteristics in order to satisfy these two constraints.. Figure 4-5. Definition of the operating point.. 4.5.2 Compensation of channel-length modulation effect Because the transistor M4 is operated in the subthreshold region, from Section 4.4, we know the relation between I1 and VGS 4 are given by. I1 = I 0 exp. VGS 4 . ς Vt. (4-6). I1 . I0. (4-7). The equation (4-6) also can be expressed as. VGS 4 = ς Vt ln. From (4-7), we derive VGS 4 versus supply voltage change. ∂VGS 4 ς Vt ∂I1 = . I1 ∂VDD ∂VDD Finally, the current flowing through resistor R1 is obtained by 28. (4-8).

(87) Figure 4-6. Determination of channel-length modulation reduction.. ∂ (VGS 4 R1 ) ∂VDD. =. ς Vt ∂I1. I1 R1 ∂VDD. .. (4-9). If the resistance of R1 is large, the current VGS 4 R1 is almost independent of supply. voltage variation. From simulated parameters, ∂ (VGS 4 R1 ) ∂VDD ≈ 0.065 ∂I1 ∂VDD. means this current VGS 4 R1 is insensitive to channel-length modulation effect.. The current flows through R1 is equal to . VGS 4 = I 2 + I5 . R1. (4-10). Due to design the short length of transistor M5, the current I 5 has a significant channel-length modulation effect. It can be expressed by I 5 = I 5 ( 0 ) + I 5 ( ∆VDD ) where I 5 ( 0 ) presents the current independent of supply voltage and I 5 ( ∆VDD ) stands for the current increasing as supply voltage. But VGS 4 R1 is stable even when. supply voltage changes a lot, then we can obtain the equation ∂ (VGS 4 R1 ) ∂VDD ≈ 0 .. As a result, the current I 2 must be decreasing as I 5 increasing like equation (4-11). The trend of these two currents is presented in Figure 4-6.. ∂I ( ∆VDD ) ∂V R ∂I ( 0 ) ∂I 5 ( ∆VDD ) ∂I 2 = GS 4 1 − 5 − ≈− 5 . ∂VDD ∂VDD ∂VDD ∂VDD ∂VDD 29. (4-11).

(88) 4.5.3 Output reference voltage For simplification, equation (4-10) is modified by. VGS 4 S = I2 + I5 = I2 1 + 5 , R1 S2. (4-12). where S = (W L ) and we also assume K = (1 + S5 S 2 ) . So it can be obtained by −1. I 2 = K (VGS 4 R1 ) .. (4-13). Moreover, the transistor size of M2 and M6 are the same. So the reference voltage is expressed as. VREF = α I 2 R2 + VGS 7 − VGS 8 ,. (4-14). where the quantity α represents the percentage of the current flowing through the resistor R2 . From the standpoint of resistor R3 , the reference voltage is expressed as. VREF = (1 − α ) I 2 R3. α = 1−. VREF . I 2 R3. (4-15). By substituting equation (4-15) into (4-14), we have. VREF = I 2 R2 −. VREF =. 1 R 1+ 2 R3. R2 VREF + VGS 7 − VGS 8 R3. K. R2 VGS 4 + VGS 7 − VGS 8 . R1. (4-16). From above equation, we know the reference voltage is independent of supply voltage 30.

(89) and process variation. However, note that the transistors M4, M7 and M8 are operated in subthreshold region. They all contain the negative temperature coefficients. The derivative with respect to temperature is. ∂VREF 1 R = KG 4 K 2 + KG 7 − KG8 . T0 (1 + R2 R3 ) R1 ∂T. (4-17). In order to obtain the reference voltage with zero-temperature coefficient, equation (4-17) must be set to zero by choosing the appropriate parameter K R2 R1 .. K. R2 K G 8 − K G 7 = . R1 KG 4. Figure 4-7. (4-18). Chip photo.. 4.6 EXPERIMENTAL RESULTS The proposed circuit was fabricated by TSMC 0.35 m technology. The chip, whose photo is shown in Figure 4-7, occupies a silicon area of about 0.018 mm2. The start-up time of voltage reference circuit is shown in Figure 4-8 and nominal reference voltage is 400.3 mV at room temperature. Figure 4-9 shows the steady–state reference 31.

(90) voltage. Because the proposed voltage reference circuit improves the channel-length modulation effect, the output voltage variation is about 7 mV when supply voltage is changing from 1.5 to 4.0 V. Figure 4-10 shows the reference voltage with and without compensation. The black line comes from the experimental result. The red line stands for the transistor M5 isn’t exist and the output voltage variation is 49 mV. A plot of the reference voltage versus supply voltage changing from 0 V to 4 V is shown in Figure 4-11. The minimum supply voltage is 1.3 V and supply current is 7.6 A. The mean temperature coefficient is 72.4 ppm/ in the temperature range of -20 to 80 . The reference voltage versus temperature variation is shown in Figure 4-12.. Figure 4-8. Figure 4-9. Start-up time of voltage reference circuit.. The steady-state reference voltage. 32.

(91) Reference Voltage (V). 600. 500. 400. with compensation without compensation. 300. 200 1.0. 1.5. 2.0. 2.5. 3.0. 3.5. 4.0. Supply Voltage (V). Figure 4-10. Comparison of reference voltage with and without compensation of channel-length modulation effect.. Figure 4-11. Experimental reference voltage versus supply voltage at room. temperature.. 33.

(92) Reference Voltage (V). 408. VDD = 1.3 V 404. 400. 396. 392. -20. Figure 4-12. 0. 20. 40. Temperature. 60. 80. Experimental reference voltage versus temperature for VDD = 1.3 V.. TABLE 4-1 PERFORMANCE SUMMARY Supply voltage 1.3 V to 4.0 V Supply current 7.6 A Reference voltage 400.3 mV ± 1.45 mV Temperature coefficient (-20 to 80 ) 72.4 ppm/ (mean) Sensitivity to supply voltage (1.3 to 4 V) 10 mVp-p Start-up time ( VDD = 0 ~ 1.3 V) 4.9 s Chip area in 0.35- m CMOS technology 0.01813 mm 2. 34.

(93) Chapter 5. A Low-Dropout Regulator with Negative Active-Feedback Frequency Compensation. 5.1 INTRODUCTION The LDO regulator with negative active-feedback frequency compensation (NAFFC) is presented in this chapter. In order to assure the stability of the system, one compensated capacitor is used. It forms a negative active-feedback path to generate a LHP zero and to solve the unstable issue caused by the large parasitic capacitor of power PMOS. The zero can compensate the frequency response to obtain better phase margin. Section 5.2 shows the brief review of LDO regulators. The proposed circuit is presented in Section 5.3. The circuit descriptions are introduced in Section 5.4. Section 5.5 shows the simulation results.. 5.2 BRIEF REVIEW OF LDO REGULATORS Figure 5-1 illustrates the topology of conventional LDO regulator. It is composed of a power PMOS transistor, an error amplifier and feedback resistors. Moreover, the voltage reference circuit is needed to provide a stable input voltage for the error amplifier. The open-loop system includes at least two low-frequency poles and one zero which are approximated as [26] [28] [29]:. ω p1 ≈. 1 rdspCOUT. (5-1). ωp2 ≈. 1 Roa CPT. (5-2). 35.

(94) Figure 5-1. Topology of conventional LDO regulator.. ω z1 ≈. 1 ReCOUT. (5-3). , where rdsp is the resistance of power PMOS transistor. Roa and CPT are the output resistance and capacitance of the error amplifier. Due to high impedance of the error amplifier and the large size of power PMOS transistor, the pole ω p 2 is located at low frequency. The third pole could be introduced by output parasitic or the internal nodes of the error amplifier capacitance. This results in a potentially unstable system of LDO regulator. Besides that, the variable factors of the load, including output current and equivalent series resistance (ESR), makes frequency compensation become a difficult issue.. 5.3 THE PROPOSED LDO REGULATORS In order to make certain the LDO regulator stable, we presented the negative active-feedback frequency compensation (NAFFC) technique. Topology of proposed regulator is shown in Figure 5-2. The error amplifier, high swing stage and power PMOS transistor can be viewed as a three-stage amplifier and the capacitor Cm provides not only the pole-splitting compensation but also the feedback path to create 36.

(95) a LHP zero. The main compensated operations should be divided into two parts which are discussed in the following.. Figure 5-2. Topology of proposed LDO regulator.. 5.3.1 Without off-chip capacitor and ESR When off-chip capacitor is moved out, there is still a parasitic capacitor ( CPAR ) in the output of LDO regulator. The open-loop transfer function is derived as follows:. H (s) = 1+. A0 1 + s. Cm ( C2 + Cm ) g mf + g ma g m 2 g mPT. s. s. ω p1. 1+. ω p2. C CC 1 + s 1 + s2 1 2 gm2 g ma g m 2. .. (5-4). , where A0 is the dc open-loop gain which is defined in (5-5). A0 =. Rf 1 Rf 1 + Rf 2. (. ). g m1 g m 2 g mPT Ro1 Ro 2 rdsp ( R f 1 + R f 2 ) .. (5-5). The transconductance g m1 , g m 2 , g mPT and the output resistance Ro1 , Ro 2 , rdsp are. 37.

(96) provided by error amplifier, high swing stage and power PMOS individually. From the transfer function (5-4), there are two poles, one complex pole and one zero in the system which are given by. ω p1 =. 1 g m 2 Ro 2 Ro1Cm. ωp2 =. 1. (r ( R dsp. ω p 3,4 =. (5-6). ). f 1 + R f 2 ) CPAR. (5-7). g ma g m 2 (5-8) C1C2. ωz = Cm. 1 + g ma. 1 (1 + C Cm ) gmf. .. (5-9). g m 2 g mPT. In order to obtain the maximum flat response, the damping factor ( ς ) of the second-order function should be set to 1. ς=. 1 2. 2.. g ma C1 1 = g m 2 C2 2. g ma = 2 g m 2. C2 C1. (5-10). , where C1 and C2 are the parasitic capacitors in the output of error amplifier and high-swing stage. Two extreme cases are discussed as follows. When output load current equals to zero, rdsp is maximized and g mPT is minimized. From (5-7) and (5-9), ω p 2 and. ω z are located at low frequency and ω p 2 < ω z . In addition, ω p 3,4 is located at high frequency due to small parasitic capacitor C1 . The frequency response is shown in Figure 5-3 where solid line illustrates the phase margin is better than 60° . When output load current increases a lot, rdsp decreases and g mPT increases significantly. The open-loop transfer function in the case of approximated by. 38. I OUT ≠ 0. is.

(97) A0. H (s) ≈ 1+. s. C CC 1 + s 1 + s2 1 2 gm2 g ma g m 2. ω p1. (5-11). , where ω p 2 and ω z are moved to the high frequency. Because of ω p 3,4 >> ω p1 , we still obtain the phase margin is larger than 60° .. 5.3.2 With off-chip capacitor and ESR The LDO regulator with off-chip capacitor is also stable. The open-loop transfer function is expressed as. A0 1 +. H (s) ≈ 1+. s. ω p1. 1+. s. 1+. ω ze. s. ω p2. s. ωz. C CC 1 + s 1 + s2 1 2 gm2 g ma g m 2. (5-12). , where ω p 3,4 and ω z are defined in (5-8) and (5-9), and ω p1 , ω p 2 , ω ze are given by. ω p1 =. (r ( R dsp. 1. f1. ). + R f 2 ) COUT. (5-13). ωp2 =. 1 (5-14) g m 2 Ro 2 Ro1Cm. ω ze =. 1 (5-15) Re COUT. When I OUT = 0 , rdsp is maximized and COUT is large leading to ω p1 close to zero frequency. ω p 2 is generated by the compensated capacitor. Although the system exists four poles, it is still stable by means of two LHP zeros to provide enough phase margin. When I OUT ≠ 0 , ω p1 and ω z approach the higher frequency. ω ze without a. 39.

(98) shift makes the system stable.. ω p1. ω p2. ωz. ω p 3,4. (a). (b) Figure 5-3. Open-loop gain of LDO regulator without COUT and ESR (a) Magnitude. response (b) Phase response. The load current is 0 (solid line) and 80 (dash line) mA.. 40.

(99) ω p1. ω p2. (a). (b) Figure 5-4. Open-loop gain of LDO regulator with COUT = 10 F and Re = 0.1. (a). Magnitude response (b) Phase response. The load current is 0 (solid line) and 80 (dash line) mA.. 41.

(100) 5.4 CIRCUIT DESCIPTIONS The proposed circuit structure is shown in Figure 5-5. In this LDO regulator, it can be viewed as a three-stage amplifier. The first amplification stage is implemented by transistors M11-M18 with a PMOS input differential pair. The second non-inverting amplification stage and third stage are realized by transistors M21-M24 and MPT, respectively. The compensated capacitor Cm connects the high-swing output stage and source of transistor M15 which supply a negative active-feedback path. Transistor MMF can force the LHP zero ( ω z ) closing to zero frequency. From (5-9), if MMF doesn’t exist, ω z is changed to ω z '= 1 ( Cm g ma ) which is located at. higher frequency than ω z . It is obvious to obtain the better phase margin if ω z is closer to ω p 2 .. Figure 5-5. The schematic of proposed LDO regulator.. 5.5 SIMULATION RESULTS The chip photo of LDO regulator, implemented by TSMC 0.35 m technology, is shown in Figure 5-6, and the chip area is occupied by 365. m × 290. m. The. internal circuit only needs one compensated capacitor Cm =2 pF and it operates in. VIN = 1.5 V and consumes 65- A ground current. The dropout voltage is varied as different load current changed from 0 mA to 100 mA. Figure 5-7 shows the dropout voltage is about 250 mV when load current is lower than 80 mA. 42.

(101) The load transient response for load pulsed currents of 0 mA and 80 mA has been simulated. Two cases without and with off-chip capacitor are taken into consideration. Figure 5-8 and Figure 5-9 show the load transient response, respectively. Moreover, from the simulation results, the larger resistance of ESR is, the faster response time can be achieved. As ESR becomes larger, undershoot and overshoot is increasing at the same time. The influences of ESR are shown in Figure 5-10. Output ripples are 12.5 mVp-p and 2.4 mVp-p produced by supply spikes equaling to 100 mV which shows in Figure 5-11.. Figure 5-6. Chip photo.. 1.30. VOUT (V). 1.25. 1.20. 1.15. 1.10. 0. 20. 40. 60. 80. 100. Load Current (mA). Figure 5-7. Output voltage of LDO regulator vs. load current.. 43.

(102) Figure 5-8. Load transient response without off-chip capacitor as load current is varied from 0 to 80 mA.. Figure 5-9. Load transient response with COUT = 10 F and ESR = 0.1 as load current is varied from 0 to 80 mA.. 44.

(103) (a). (b) Figure 5-10. Load transient response with COUT = 10 F as output current is varied. from 0 to 80 mA. For the ESR, the resistance Re is 0.1, 0.3, 0.5, 1 and 2 .. 45.

(104) (a). (b) Figure 5-11. Power-supply rejection of the regulator for 10-mA load current (a). without off-chip capacitor (b) with COUT = 10 F and Re = 0.1 .. 46.

(105) Chapter 6. Conclusions. A current-reuse technique for nested Miller compensation amplifier is introduced in Chapter2. It can achieve the low-power design with power consumption reduced to half from the traditional nested Miller compensation amplifier. From the derivation of NMC amplifier, there is a tradeoff between the required compensation capacitance and output-stage sinking current. The CRNMC amplifier can have smaller compensation capacitance and also keep low power dissipation at the same time, so is more suitable for low power, mobile applications. All the simulation results and performance parameters are proved by post-layout simulations using a 0.35- m CMOS process. The experimental performance and derivation are matched well. Chapter 3 presents the negative active-feedback frequency compensation (NAFFC) technique. Avoiding the capacitive feedback paths at the output and using the pole-zero cancellation approach improve the gain-bandwidth product obviously. The high slew rate and short settling time of the NAFFC amplifier characteristics make the amplifier suitable for data conversion and switched-capacitor circuits. The experimental results show good frequency and transient responses. Comparison with the other previously published compensation techniques are also presented in this chapter. A MOSFET-only voltage reference circuit based on subthreshold characteristics has been introduced in Chapter 4. It exploits the self-biased circuit to reduce the channel-length modulation effect and weighted gate-source voltage to achieve nearly zero-PTAT reference voltage. A nominal output voltage is 400.3 mV under the lowest supply voltage = 1.3 V. Experimental results reported the reference voltage having 10-mV variation in the supply range of 1.3 V to 4 V. The temperature coefficient is 72.4 ppm in the range [-20 , 80 ]. Chapter 5 presented a novel frequency compensation to assure the LDO regulator. 47.

(106) stable. The regulator occupies 0.106 mm 2 of silicon area with 2-pF compensated capacitor and it is suitable for 1.5-1.25 V conversion. 48.

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