高效能互補金屬氧化層半導體式轉導放大器與濾波器於無線通訊與有線系統之應用

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高效能互補金屬氧化層半導體式轉導放大器與濾

波器於無線通訊與有線系統之應用

High Performance CMOS Transconductors and Gm-C

Filters for Wireless Communications and Wireline

Systems

研究生：羅天佑

Student: Tien-Yu Lo

指導教授：洪崇智博士

Advisor: Dr. Chung-Chih Hung

國立交通大學

電信工程學系

博士論文

A Dissertation

Submitted to Institute of Communication Engineering

College of Electrical and Computer Engineering

National Chiao Tung University

in Partial Fulfillment of the Requirements

for the Degree of Doctor of Philosophy

in

Communication Engineering

Hsinchu, Taiwan

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High Performance CMOS Transconductors and Gm-C

Filters for Wireless Communications and Wireline

Systems

A Dissertation

Presented to

The Academic Faculty

By

Tien-Yu Lo

In Partial Fulfillment

of the Requirement for the Degree of

Doctor of Philosophy in Communication Engineering

Department of Communication Engineering

National Chiao-Tung University

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高效能互補金屬氧化層半導體式轉導放大器與

濾波器於無線通訊與有線系統之應用

研究生：羅天佑

指導教授：洪崇智博士

國立交通大學

電信工程學系

摘要

近年來低電壓的電路系統需求日益增加，尤其對於系統單晶片的應用更加的明顯。當我們把工作電壓降低，數位電路將能在相同的電路效能下擁有更小的功率消耗；但是對於類比電路而言，整體電路的效能將會受到很大的影響。除此之外，電路的面積將需要被適當的考量，以降低進階多功能式系統單晶片的成本。因此，新穎的類比積體電路技術將是個非常熱門的課題。新穎的轉導放大器以及無線與有線系統的應用將被介紹於此篇論文。轉導放大器為類比電路中基本的建構方塊。通常此放大器將應用於轉導電容式濾波器、連續時間三角積分調變器、壓控震盪器以及乘法器。首先，我們設計了兩種工作於高速的轉導放大器。於此設計當中，於奈米技術所產生的短通道效應將被討論與消除。結果驗證了此電路將能於高速下維持非常好的效能。接下來我們討論了一廣泛可調頻寬式的轉導電容式濾波器。此濾波器使用了五階的 elliptic形式並設計於非常低的截止頻寬。經由切換電阻的方式，此濾波器將能工作於生醫系統、音訊系統以及部分的無線系統。結果證明了在可調頻寬範圍內，此電路的線性度將能被適當的維持。三種應用於直接轉換接收器之多模通道選擇濾波器被介紹於此篇論文當中。這些濾波器

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將涵蓋了2G (GSM)、3G(cdma2000與Wideband CDMA)、藍芽(buletooth)與無線區域網路(IEEE 802.11 a/b/g/n Wireless LANs)。我們依照規格設計特定的轉導放大器，並經由三階的elliptic 濾波器的形式加以實現。所設計的結果驗證符合所需的無線系統規範。

最後，兩種高速的濾波器被報告於此篇論文。此高速濾波器接使用了四階equiripple濾波器的形式，以使用於脈衝訊號系統當中。其中之一的濾波器設計於硬碟(HDD)存取系統。同時先進的自動校正電路將被實現，此電路將用來抵抗製程與溫度所產生的變異。另外的濾波器將應用於超寬頻(UWB)系統，經由適當的設計，此電路能工作於低電壓源。

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ABSTRACT

There are growing demands for low-supply circuits and systems. This is especially true for system-on-a-chip application. Switching to use lower power supply voltage, digital circuits do not suffer the degradation of their performances too much. On the other hand, for analog circuits, the circuit performances are strongly affected by the low voltage supply. In addition, the chip area should also be taken into consideration to reduce large costs of advanced multi-function SOC design. Therefore, new design techniques for analog circuits are required to be developed.

In this research work, novel transconductors with the applications to wireless and wireline systems are introduced. The transconductor is a basic building block for analog circuits, such as the

Gm-C filter, continuous-time delta sigma modulator, voltage controlled oscillator and multiplier. Two transconductors working at high frequency is developed at first. The short channel effects in the nano-scale technology are discussed and eliminated, and the results show the high performance even at high speed operation.

A wide tuning range Gm-C filter with a 5th-order Elliptic prototype for very low frequency is discussed. Through the use of switching technology, the filter can operate from the biomedical systems and the audio systems to part of wireless systems. The distortion performance maintained over the tuning range is also shown.

Three multi-mode channel section filters for the Zero-IF direct conversion receiver are presented. These filters cover the wireless applications of GSM, bluetooth, cdma2000, wideband CDMA and IEEE 802.11 a/b/g/n Wireless LANs. The specific transconductors with required function are designed. Through the use of a 3th-order Butterworth prototype, the results are shown to meet the specifications of various wireless applications.

Two high speed filters with a 4th-order equiripple prototype are presented. The high speed filter can be used for pulse signal systems. One is designed for the hard disk storage systems. A novel automatic tuning circuit is also implemented to account for process and temperature variations. The other is designed for the UWB system. This circuit can work well under a low supply voltage.

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Acknowledgments

I would like to express my sincere appreciation to my advisor, Professor Chung-Chih Hung, for his guidance and support during my studies at National Chiao-Tung University. His creativity and insight into circuit design helped me a lot in my research. His energy and love of what he is doing inspires me a lot. I feel very grateful for his supervision both on the technical and the personal levels. He indeed opens a door to the future for me.

I would like to thank my colleagues in the Analog Integrated Circuit Lab for their friendship and all of their help over the years.

Special thanks to my parents and sisters for their love and encouragement. I could not have completed this dissertation without it. Special thank to my girl friend Ling, who is always there for me, no matted I am rich or poor, happy or sad.

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List of Tables

2.1. Comparison with previously reported works. ... 27

2.2. Comparison of previously reported works. ... 39

3.1. Performance summary of the fabricated prototype. ... 85

4.1. Performance Summary of this work. ... 95

4.2. Performance Summary of this work. ... 105

4.3. Performance summary of this work. ... 118

4.4. Comparison with previously reported works. ... 119

5.1. The denominator of equiripple linear phase transfer function.. ... 124

5.2. Comparison of previously reported works. ... 139

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List of Figures

1.1. The filter operation frequency for varies applications. ... 2

2.1. The implementation of the source degeneration transconductor.. ... 5

2.2. The modified source degeneration transconductor... 6

2.3. The transconductor by using linear region transistor as inputs. ... 7

2.4. The regulated control loop amplifier. ... 8

2.5. The differential transconductor. (a) fully-differential. (b) pseudo-differential. ... 9

2.6. The common-mode feed farward scheme. ... 10

2.7. The block diagram of the attenuation technique. ... 12

2.8. The structure of MIFG NMOS transistor. ... 12

2.9. The transconductor implemented by MIFG NMOS transistors. ... 13

2.10. The pseudo-differential circuit by taking short channel effects into consideration. ... 16

2.11. Nonlinearity cancellation using double pseudo-differential pairs with degeneration resistors. ... 16

2.12. Optimal parameter evaluation for the reduced transconductance. ... 19

2.13. Optimal parameter evaluation for the third-order harmonic component. ... 19

2.14. Contour plot for the third-order harmonic component under transconductance tuning. ... 20

2.15. Proposed OTA circuit. ... 22

2.16. Simulated transconductance tuning range... 23

2.17. The common-mode control system. ... 23

2.18. Die microphotograph. ... 26

2.19. Measured two tone inter-modulation distortion. ... 26

2.20. Measured two tone inter-modulation distortion with respect to input signal frequency. ... 26

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2.21. Nolinearity cancellation mechanism... 29

2.22. (a) Basic pseudo-differential CMOS pair. (b)Mobility compensation in the pseudo-differential structure. ... 30

2.23. Proposed OTA circuit. ... 33

2.24. Large signal simulation of the proposed circuit. ... 35

2.26. The output current versus input voltage over the tuning range. ... 37

2.27. Measured two tone inter-modulation distortion. ... 37

3.1. The single-ended integrator. ... 40

3.2. The fully-differential integrator. ... 41

3.3. The gain and phase of ideal (dashed) and non-ideal (solid) integrator. ... 42

3.4. (a) The integrater with maximum unity-gain frequency. (b) The integrator with constant-Gm design. (c) The integrator with constant-CL design. ... 44

3.5. The lossy integrator. ... 46

3.6. The biquad section. ... 47

3.7. The 6th-order ellipitic low-pass passive filter. ... 48

3.8. The SFG synthesis of the LC network. (a) passive prototype. (b) implementation of (3.16). (c) implementation of (3.17). (d) implementation of (3.18). ... 49

3.9. The SFG synthesis of the input R and output RC network. (a) implementation of (3.19). (b) implementation of (3.20). ... 50

3.10. The Gm-C implementation of passive network shown in Fig. 3.9. ... 51

3.11. (a) The biquad bandpass filter including integrator noise model. (b) The bandpss passive prototype with integrator noise model. ... 56

3.12. The illustration of input and output intercept point with the unit of decibel.. .... 60

3.13 The proposed transconductor circuit. ... 64

3.14. Equivalent resistor circuit. ... 72

3.15. Final implementation of the proposed transconductor circuit. ... 72

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3.17. Simulated linearity performance of the equivalent resistor. ... 76

3.18. Fifth-order elliptic RLC ladder network prototype. ... 77

3.19. Fifth-order Elliptic low-pass Gm-C filter. ... 77

3.20. The measurement results of the proposed transconductor circuit. ... 80

3.21. Measured frequency responses over the tuning range. ... 82

3.22. Measured IM3 values at cutoff frequency. ... 83

3.24. FOM comparison with previously published filters. ... 84

4.1. The Basic diagram of the direct-conversion receiver. ... 87

4.2. Proposed transconductor circuit. (a) Implementation of transcontuctor. (b) Open loop model of the FVF circuit. ... 89

4.3. The equivalent resistor circuit. ... 91

4.4. The common-mode feedback circuit. ... 93

4.5. The Gm-C realiazation of the third-order Butterworth filter. ... 94

4.6. Gm variation of the proposed transconductor. ... 94

4.7. The frequency response of the proposed multi-mode filter. ... 95

4.8. Basic diagram of the transconductor. ... 97

4.9. The voltage-to-current cell. ... 99

4.10. The high linearity current multiplier... 101

4.11 The simulated Gm range of the proposed transconductor. ... 102

4.12. The final implementation of the proposed transconductor with the CMFB circuit. ... 103

4.13. The chip micrograph. ... 104

4.14. The measured frequency responses of the proposed multi-mode filter. ... 104

4.15. Implementation of transconductor. (a) The conventional transconductor. (b) The MOSFET-only transconductor. (c) The differential transconductor. ... 108

4.16. The concept of a wide tuning range transconductor. ... 110 4.17. Final implementation of the proposed transconductor with the CMFB circuit. 113

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4.18 The simulated Gm range of the proposed transconductor. ... 114

4.19. The chip micrograph. ... 116

4.20. Two-tone test of the proposed transconductor. ... 116

4.21. The measured frequency responses of the proposed multi-mode filter. ... 117

5.1. Simplified architechure of HDD front-end. ... 121

5.2. Direct tuning scheme. ... 125

5.3. Indirect tuning scheme. ... 126

5.4. Frequency tuning circuit by using single transconductor. (a) Resistor based tuning. (b) Switch based tuning. ... 127

5.5. Frequency tuning based on the VCO. ... 128

5.6. Frequency tuning based on the VCF. ... 129

5.7. The high speed transconductor circuit. ... 131

5.8. Circuit implementation. (a) Negative output resistance circuit for gain enhancement. (b) Transconductance tuning circuit... 133

5.9. The 4th-order equiripple linear phase filter. ... 135

5.10. The modified automatic tuning scheme. ... 135

5.11. The measured frequency response of the proposed filter. ... 137

5.12. The measured group delay of the proposed filter. ... 137

5.13. Two tone inter-modulation of the filter. ... 138

5.14. Die micrograph. ... 139

5.15. Linearized low voltage OTA circuit. ... 141

5.16. The modified low voltage OTA circuit. ... 142

5.17. The common-mode control system. ... 144

5.18. The 4th-order equiripple linear phase filter. ... 146

5.19. Die micrograph. ... 146

5.20. The magnitude response and the group delay of the 4th-order equiripple linear phase Gm-C filter. ... 147

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Chapter 1 Motivation

1.1 Introduction

In recent years, low-voltage VLSI circuits have received lots of attentions. The power supply voltage has decreased following the advancement of process technology, and the operation frequency of CMOS can also go up higher than 100 GHz. The demands for nano-scale applications are mainly driven from three factors: technology-driven, design-driven, and market-driven. They are: reduction of the minimum feature size to scale down the chip area, fabricating millions of transistors on a single chip to save cost, and the increase in market demands for communication electronic products, respectively. These demands seem to be independent to each other. However, the advances in VLSI technology, circuit design, and product market are actually interrelated to one another.

In the past decade, CMOS technology has played a major role in the rapid advancement and the increased integration of VLSI systems. CMOS devices feature high input impedance, extremely low offset switches, high packing density, low switching power consumption, and thus can be easily scaled. The minimum feature size of a MOS transistor has been decreasing [1-3]. Current VLSI technology is scaled down to around 0.09 µm. Scaling down the transistor sizes can then integrate more circuit components in a single chip, so the circuit area and thus its cost will be reduced. Besides this economic consideration, smaller geometry usually lowers the parasitic capacitance, which leads to higher operating speed. When a MOS transistor size is decreased, not only its channel length and width are reduced, but also the thickness of the gate oxide. As a MOS transistor has a thinner gate oxide, in order to prevent the transistor from breakdown because of the higher electrical field across the gate oxide and to ensure its reliability, the power supply voltage is necessary to be reduced [4-8].

Since the digital circuits are more and more popular, the computer-aided design tools for digital circuits are very mature, and digital circuits certainly occupy most of the fabricated chip area, the electrical characteristics of MOS transistors are optimized mainly for digital circuits. Switching to use nano-scale devices, digital circuits do not suffer the degradation of their performances too much.

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Figure 1.1. The filter operation frequency for varies applications.

dynamic range, speed, bandwidth, linearity, etc., are strongly affected by using nano-scale technology. Therefore, new design techniques for nano-scale analog circuits are required to be developed. Moreover, we are living in an analog world, so it is inevitable to use analog signal processing. Modern analog and mixed-signal VLSI applications in areas such as telecommunications, smart sensors, battery-operated consumer electronics and artificial neural computation require CMOS analog design solutions. Thus, analog signal and information processing in nano-scale technology is really a field in which devotion of efforts is eager.

1.2 Applications

In the systems that interface with real word, the processed signal would be measured with unwanted noise. A filter is usually used to get rid of the unwanted noise and reject the surrounding interface. Thus, filters are important block for specified frequency of signals and they are essential for many applications. They can be used to band-limit signals in wireline and wireless communication systems. These filters operate on continuous-time fashion since the systems interface with real analog world. Fig. 1.1 shows the required low-pass filter for specified applications.

There are two kinds of the filters: one is the digital filters and the other is the analog filters. The analog filters process the continuous data rather than the digital data for digital filters. The analog filters can be further divided into pass filters and active filters. The elements of a passive filter are passive, and then a passive filter would include resistors, capacitors, inductors, and transformers. On the contrary, the active filters include active devices. A large area is required for the passive filter, and then the active filter is more suitable in CMOS technology.

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Active filters can be classified into Active-RC, Switched-Capacitor, Gm-C, and LC filters. The Active-RC and Switched-Capacitor filters are only suitable for low to medium frequency applications. For high frequencies, the settling problem of amplifiers would affect the filter performance since very wide bandwidth and large unity-gain frequency is hard to be achieved. For systems at GHz range, LC filters is a better choice since the required values of L and C are small. However, Q enhancement is needed for LC filters because of low inductor quality factors. The

Gm-C filters, which operate on open loop topology, would be sufficient for low to high frequency range. Thus, the Gm-C architecture can be implemented for various applications. In addition, it is note that the performance of the Gm-C filter is highly dependent on the performance of the transconductor.

Another issue is the automatic tuning circuit. The frequency response and the quality factor should be maintained owing to process, supply and temperature variations. Thus, a high performance automatic tuning circuit is required for continuous-time active filters.

1.3 Organization

Our dissertation is focus on the transconductor with the implementation of The

Gm-C filter for wireless and wireline applications. This dissertation is partitioned into four parts. First, we introduce the basic concepts of transconductors. The circuits with varies linearity architecture are discussed. Two modified transcontuctors which can operate under high frequency are present. Next, the filter synthesis from the passive prototype to the active prototype is introduced. The non-ideality caused by the integrator is also discussed. We illustrate some important parameters to illustrate filter performance. A modified wide tuning range filter is presented as an example. Then, the zero-IF architecture for wireless communication is introduced. Three modified channel selection multi-mode filter for various wireless applications are presented. The channel selection filters can be suitable for the specifications of GSM, Bluetooth, cdma2000, Wideband CDMA, IEEE 802.11 a/b/g/n Wireless LANs. At last, we introduce the equiripple filter which is required for pulse signal channel. The processing of the signal requires constant group delay. The basic concept of automatic tuning circuit is also introduced. Then, a high speed filter used for hard disk read channel with a modified frequency tuning circuit is presented. Finally, another filter used for UWB application is then presented.

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Chapter 2 Transconductor

2.1 Introduction

This chapter shows the basic concept and improved design of the transconductor. The transconductor is one of the most important building blocks in analog and mix-mode circuits, including multipliers [9-10], continuous-time Gm-C filters [11-12], voltage controlled oscillators [13], and continuous-time sigma-delta modulators [14]. Its main idea is to convert the input voltage into the output current with a linear transformation factor. The active device is used for replacing passive devices owing to power and area consideration with the tradeoff of the non-ideal performance. The main non-ideal characteristic of the transconductor are the limited linear input range, limited output impedance, finite signal-to-noise ratio and finite bandwidth. The linear performance is the most important issue in the transconductor design. Moreover, as the feature size of CMOS technology scales down with power supply voltage, the dynamic range, bandwidth, and power consumption will be limited by the linearity. A variety of linearization techniques have been reported in recent years.

2.2 A review of CMOS transconductor

The transconductor in CMOS process is required for the system-on-a-chip strategy. Thus, the following section discusses the reported basic linearity technique in CMOS process.

2.2.1 The source degenerated transconductor

Figure 2.1 shows circuit implementation of the source degeneration technology. The output current is related to the input voltage by the following equation [15]:

(

)

2 (1,2) (1,2)( ) 2 1 1 2 1       = − _ _  ₊  _ ₊ _   b _id O id DS sat K I _v i v N N V (2.1) 1 1   = _ _ +   m N G R N (2.2)

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Figure 2.1. The implementation of the source degeneration transconductor.

(

)

(

)

2 3 (1,2)( ) 1 32 1     = +     id DS sat v HD N V (2.3)

where vid = Vi+ - Vi- , VDS(1,2)(sat) = VGS(M1,M2) - Vtn and N = gm(1,2)R is the source degeneration factor. By using the equation, we can found the transconductance is reduced by a factor of 1+N and the third harmonic distortion is reduced by the square of the same factor. It is clear that N should be a large value. This condition not only makes the transconductor being tunable, as shown in (2.2), but also increases the linearity performance, as shown in (2.3). The disadvantage of the technique is the higher current and larger aspect ratio by comparing with the fully differential pair. In actually, the required factor of 1+N is expected. The bandwidth of the transconductor is limited due to additional nodes. It is fortunately that a zero is obtained in this shunt feedback technology. This zero can be used to compensate non-dominate high frequency pole. Thus, the topology can still be suitable for high frequency operations, such as a 550 MHz application [16].

Although the circuits in Fig. 2.1(a) and Fig. 2.1(b) shows the same voltage-to-current relationship, they present different properties. In Fig. 2.1(a), the resistor will provide a voltage drop, and then the range of the common-mode voltage is reduced. In Fig. 2.1(b), the noise of the current source will appear at the output, and

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Figure 2.2. The modified source degeneration transconductor.

this source will dominate the noise performance. Mismatch of the current source would also reflect as the input offset.

In many applications, the MOSFET under the linear region is used to replace the passive resistor. The classical NMOS model equation under the linear region is

(

)

2 2 µ    = _ __ − − _     DS D n ox GS tn DS V W I C V V V a L (2.4)

where a is a process dependant parameter. The linear region is hold as the drain-source voltage is lower than the gate-source voltage. If the equation is exact, the perfect linear circuit can be obtained. However, this equation neglects higher order terms under the short channel process, and some of nonlinear terms would occur and then reduce the circuit performance.

If a small drain-source voltage is used, we can simply neglect the second order terms in (2.4). The drain current is linear with respect to the applied drain-source voltage. Thus we can obtain a small-signal resistance of

(

)

1 µ =   −     DS n ox GS tn r W C V V L (2.5)

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Figure 2.3. The transconductor by using linear region transistor as inputs. gate bias voltage and we add the transconductane continuous tuning ability of Fig. 2.1(b). The disadvantage of the MOS resistor is the sensitivity of the input common-mode voltage. As we change the input common-mode voltage, the resistance is varied owing to the variation at the source node of transistors M1 and M2. For the reported results, the third-order harmonic distortion (HD3) of MOS resistor within source degenerated transistor is limited to be -50 dB.

Fig. 2.2 shows an improved source degeneration transconductor. The circuit relaxes the requirement of large aspect ratio of transistors M1 and M2. However, the feedback topology adds low frequency poles, and thus the circuit is not suitable for high frequency operation.

2.2.2 The constant drain-source transconductor

We recall the linear region equation in (2.4) at first. We can find that if the drain-source voltage is kept constant, the drain current is very linear with respect to the applied gate-source voltage. Figure 2.3 shows the transconductor which uses the constant drain-source technology. By using a regulated control loop, the drain voltage is set to the voltage Vtune through the feedback topology. Then,

(

)

2 1 2 µ +     = _ __ − − _     tune n ox i tn tune V W I C V V V a L (2.6)

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Figure 2.4. The regulated control loop amplifier.

(

)

2 2 2 µ −     =   − −      tune n ox i tn tune V W I C V V V a L (2.7) We can have,

(

)

1 2 µ + −   − = _ _ −   n ox i i tune W I I C V V V L (2.8) G_m _nC_ox W V_tune L µ   = _ _   (2.9)

From the above equation, the transconductance and the biasing current are proportional to the Vtune. In practice, the second-order effect would limit the accuracy of the model. In addition, the regulated control loop can relax the requirement of large gm(3,4) to minimize the voltage variation at drain node of transistors M1 and M2.

In the circuit, the feedback connection will not appear at the signal path, and thus the transconductor could be used at high frequency as well. In [17], a 200MHz implementation was presented, and a third order harmonic terms can be expressed as

(

)

2 2 (1,2) 2 (3,4) (1,2) 3 4 ( ) 1 ( ) =  ₊ ₊ ₋ ₋    i CM tn tune V K HD A s gm K V V V (2.10)

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Figure 2.5. The differential transconductor. (a) fully-differential. (b) pseudo-differential.

where A(s) is the gain of regulated gain control amplifier. In this equation, the high speed operation would degrade the gain of regulated control amplifier, and thus affect the linearity. From the analysis, the gain of larger than 10V/V should be required for -50dB HD3 of the transconductor. The implementation of the regulated gain control amplifier is shown in Fig. 2.4. It is composed by the differential pair and the source followers. The source followers are used to increase the transconductance tuning range and gives more input swing range of the transconductor.

2.2.3 The pseudo-differential transconductor

The topology of a general fully-differential transconductor is shown in Fig. 2.5. Fig. 2.5(a) shows the fully-differential transconductor, and Fig. 2.5(b) shows the pseudo-differential ones. In the fully-differential configuration, the rejection of the common-mode signal is achieved by large output impedance of the tail current source. The transconductor has no internal signal carrying nodes and parasitic poles. Noise contributed by tail current source appears as the common-mode component. The third-order harmonic distortion can be shown that

(

)

2 2 3 32 = − i OV tn V HD V V (2.11)

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Figure 2.6. The common-mode feed farward scheme.

where VOV is the gate overdrive voltage of the input transistors M1 and M2 in Fig. 2.5(a). Thus, the linearity can be improved by increasing the gate overdrive voltage of input transistors. For a high linearity transconductor, a value higher than 250mV in the worst case is sufficient. The way to tune the transconductance is to adjust the bias current in the transconductor. However, if a tuning ratio of α is used, we need to increase the bias current with a ratio of α2 under the saturated square law equation. We can conclude only fine tuning is practical.

The pseudo-differential transconductor can be used under low supply voltage because it avoids the voltage drop across the tail current source. We can find that the pseudo-differential structure achieves a larger signal swing. However, the structure presents additional distortion terms, which produced by the common-mode signal. The even-order terms can appear in a perfectly balance structure owing to the product of the differential and common-mode signals. Besides, the transconductance of the input common-mode signal is equal to the input differential signal, and it is required to control the input common-mode voltage carefully. Thus, additional common-mode control circuit should be required.

A common-mode feedforward is introduced for input common-mode control in [18]. The common-mode feedforward scheme is shown in Fig. 2.6. The basic idea is to convert the input common-mode through another signal path, and then cancellation of input common-mode signal is obtained from the current mirror. In the scheme, transistors M3 and M4 have the same aspect ratio as transistors M1 and M2 to detect

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input common-mode signal. Then, the current which flows through transistor M5 is mirrored to cancel the common-mode signal generated by transistors M1 and M2. The common-mode gain is

(

)

(

)(

)

(1,2) (1,2) (6,7) (6,7) (1,2) (6,7) (1,2) (6,7) + + = + + + + m o o c CM m o o c o o g g g sC A g g g sC g g (2.12)

where Cc is the parasitic capacitance at node C. At low frequencies, the common-mode gain is approximated to 1. At very high frequencies, the common-mode gain is larger than 1 because the mirroring pole created by node C is grounded. The drawback of the scheme is larger input capacitance because the other differential pair is required.

The pseudo-differential transconductor can be seen as the combination of two parallel transconductor with single ended output. From the ideal square law equation under the saturation region, the output current is perfect linear with respect to the input voltage. However, the short channel effect would degrade the linearity and the performance is given by

(

)

(

)

2 2 3 8 1 2 θ θ θ =  + −   + −      i OV OV tn OV tn V HD V V V V V (2.13)

where θ is the mobility reduction coefficient and VOV is the gate overdrive voltage of the input transistors M1 and M2 in Fig. 2.5(b). Thus, the linearity can also be improved by increasing the gate overdrive voltage of input transistors. For the pseudo-differential transconductor, we can change the transconductance by adjusting the input common-mode voltage. We should note that the linearity performance is changed as well.

2.2.4 The floating-gate transconductor

The linear transconductor is designed by the concept of the attenuation. Fig. 2.7 shows the block diagram of the technique. The factor α is smaller then 1. We can see that the input voltage is attenuated by the value α and the output current is given by

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Figure 2.7. The block diagram of the attenuation technique.

Figure 2.8. The structure of MIFG NMOS transistor.

2 3

1(α ) 2(α ) 3(α )

= + + +

o i i i

i a v a v a v (2.14)

We can prove that the HD3 gets a value of α2 smaller than the original one. For the technique, one of the disadvantages is the reduction of the transconductance and the other is the implementation of perfect attenuator.

The high performance attenuator can be obtained by using the floating gate technique. In the technique, we use the multiple input floating gate MOS device. The MIFG MOS transistor is built with a regular MOS transistor where the gate is floating. The basic MIFG NMOS transistor is shown in Fig. 2.8. It can be implemented by double poly process. The floating gate is connected to the input through the capacitor. The equivalent floating gate voltage is given by

1 1 = = + + + = + + +

∑

n GS S GD D GB B i i i FG n GS GD GB i i C V C V C V C V V C C C C (2.15)

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Figure 2.9. The transconductor implemented by MIFG NMOS transistors. transistor. The equation shows the parasitic capacitance would slightly affect the floating gate voltage.

Fig. 2.9 shows the linearized transconductor using this technique [19]. The transistors M1 to M3 would be biased at the weak inversion region. Thus, the output current is expressed as

(

)

(

)

₍

₎

3 5 2 1 1 1 1 2 6 2 1 2 1 3 1 120 24 1 _{4 1} 2 ξ ξ ξ  _ _ _  _ =  +_ − _  + + +   _ _ __ _   _ _   ₋ ₊ _ _ ₊  ₊ ₊ _ _ _    out id id T T id T w w I v v A V A V w v A _A V (2.16)

where w is the ratio between the input capacitor and the total capacitance and A = m/2. We note that m is the device parameter ratio of transistor M3 with respect to transistors M1 and M2. Thus, the third-order distortion terms would be cancelled out by choosing A to be 2.

For the transconductance tuning, MOS capacitor could be a good approach in this technology. However, the floating gate technique is suitable for low speed applications owing to large input capacitance, and thus the transistors in the weak

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inversion region are usually used.

2.3 A 40MHz double differential-pair CMOS OTA with -60dB IM3

A configuration of linearized Operational Transconductance Amplifier (OTA) for low-voltage and high frequency applications is proposed. By using double pseudo-differential pairs and the source degeneration structure under nano-scale CMOS technology, the nonlinearity caused by short channel effect from small feature size can be minimized. A robust common-mode control system is designed for input and output common-mode stability, and thus reduces distortion caused by common-mode voltage variation. Tuning ability can be achieved by using MOS transistors in the linear region. The linearity of the OTA is about -60 dB third-order inter-modulation distortion for up to 0.9 Vpp at 40 MHz. This OTA was fabricated by the TSMC 180 nm Deep N-WELL CMOS process. It occupies a small area of 15.1×10-3 mm2 and the power consumption is 9.5 mW under a 1.5-V supply voltage.

2.3.1 Introduction

A variety of linearization techniques have been reported in previous section. However, some of them exploit the ideal square-law behavior of the MOS transistor in the saturation region to obtain high linearity conversion. Unfortunately, this concept is not quite suitable for small feature sizes of MOS transistors due to the influence of second-order effects like velocity saturation and mobility reduction. Thus, highly linear OTAs should be designed by taking short channel effects into consideration under nano-scale CMOS technology.

The use of multiple input floating-gate (MIFG) MOS transistors was also presented recently [19-20]. The natural attenuation could be obtained from the designed capacitor ratio. The MIFG circuit would act as a voltage divider and thus result in a large linear input swing range. However, the technique would need extra fabrication processes, and it would not be useful in standard CMOS technology. Moreover, large transconductances would be hardly achieved owing to the voltage attenuation of the input node. The linear OTA based on the flipped voltage follower (FVF) would be another useful technique [21-22]. However, the linearity performance would be dependent on the circuit feedback loop gain, and the condition of stability should be carefully designed.

In this disssertation, we present a high linearity and high speed OTA. It makes use of two input transistor pairs with their source terminals connecting to resistor loads

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and the drain terminals cross-coupled to each other. In the approach, high linearity can be achieved by choosing different values of loading resistors. The model of the short channel effect and the nonlinearity analysis of CMOS transistors are described in Section 2.3.2, and the proposed OTA implementation is presented in Section 2.3.3. The analysis of non-ideal effects such as mismatch and noise performance of the proposed circuit are discussed in Section 2.3.4. Section 2.3.5 shows the measured performance of fabricated implementation. Finally, summary is drawn in Section 2.3.6.

2.3.2 Nonlinearity analysis of saturated MOS transistors

2.3.2.1 The linearized V-I characteristic

The relationship of the voltage-to-current conversion could be described as io = f(vin), where vin and io are the input voltage and the output current, respectively. The ideal assumption of the linearized transformation is f(vin) = k×vin , where k is a constant within the applied input voltage range. Unfortunately, the V-I conversion is not possible to be perfectly linear in real circuit implementation, and the conversion can be investigated by a Taylor series expansion. If the differential structure is applied with well matched implementations, which means the even-order terms can be cancelled out, the current conversion can be expressed by:

3 5 7

1 2 1 3 5 7

O D D in in in in

I =I −I =a V +a V +a V +a V + (2.17) where the ai coefficients are determined from the circuit implementation. If the nonlinear factor is suppressed, that is, the parameters ai,i>2 are minimized, the V-I conversion would be close to a linear function, as demanded.

2.3.2.2 Saturated MOS transistor in nano-Scale CMOS technology

Linear V-I conversion is usually developed based on the basic square-law behavior of the MOS transistor in the saturation region.

(

)

2 , 1 -2 D long GS thn I = K V V (2.18)

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Figure 2.10. The pseudo-differential circuit by taking short channel effects into consideration.

Figure 2.11. Nonlinearity cancellation using double pseudo-differential pairs with degeneration resistors.

where K =µnCox(W/L), W and L are the width and length of the device, respectively, Cox is the oxide capacitance per unit channel area, µn is the low-field mobility, and Vthn is the NMOS threshold voltage. However, this condition only holds for large length of MOS transistors. As the device size is scaled down towards nano-scale CMOS technology, the short channel effect occurs due to the transversal and longitudinal electric fields. Thus, with the enhancement of speed and area for small device length, the linearity of V-I conversion based on the ideal square-law equation becomes deteriorated. Fig. 2.10(a) shows the circuit of the pseudo-differential input pair. If the length of the MOS transistors is chosen to be the minimum feature size under nano-scale CMOS technology, the output drain current can be modeled by

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(

)

(

)

2 , -2 1 -GS thn D short GS thn K V V I V V θ =  +    (2.19)

where θ is the mobility reduction coefficient. From the equation shown above, the mobility reduction coefficient can be modeled by a resistor Rθ connected to the source terminal of an ideal MOS transistor, as shown in Fig. 2.10(b). The value of the equivalent resistor equals to θ/K. Moreover, the linearity performance degrades for larger θ. This is confirmed by the results presented in [23], where tunable resistors are introduced in the source terminals of the pseudo-differential pair for the use of transconductance tuning ability with the expense of additional distortion. In this section, in order to resist the nonlinearity which occurs by the short channel effect, the double differential pairs with source degeneration structure is adopted, as shown in Fig. 2.11. In the proposed structure, two different values of resistors, Ra and Rb, are used for each differential pair, and the source degenerated resistors are added up to simplify the expression. Assume that transistors M1 to M4 are operated in the saturation region, and that Vi+ and Vi- are the input differential signals, which would be composed of common-mode and differential-mode voltages

2 2 id i cm id i cm V V V V V V + − = + = − (2.20)

where Vcm is the input common-mode voltage and Vid is the input differential-mode voltage. Then, the output current of each transistor could be given by

( ) ( )( ) ( ) ( )( ) ( ) ( )( ) ( ) ( )( ) 2 1 1 1 1 2 2 2 2 2 2 3 3 3 3 2 4 4 4 4 -2 1 -2 1 -2 1 -2 1 -i thn D a i thn i thn D a i thn i thn D b i thn i thn D b i thn K V V I K R R V V K V V I K R R V V K V V I K R R V V K V V I K R R V V θ θ θ θ + + − − − − + + =  + +    =  ₊ ₊    =  ₊ ₊    =  + +    (2.21)

where K1 = K2, K3 = K4, Rθ1 = Rθ2, and R_θ3 = Rθ4. Thus, under ideal matching, the differential output current would be the function of the input signals:

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(

)

(

)

1 3 2 4 3 1,(1,2) 1,(3,4) 3,(1,2) 3,(3,4) ( ) ( ) ( ) o D D D D id id id I I I I I f V a a V a a V = + − + = = − + − + (2.22)

where aj,i is the jth-order harmonic component provided by the ith transistor of the proposed structure, aj,1 = aj,2 = aj,(1,2), and aj,3 = aj,4 = aj,(3,4). Although the resistors connected to the source of a single pseudo-differential pair degrade the linearity performance, the third-order harmonic component could be cancelled out by proper sizing of the double pseudo-differential pairs through a Taylor series expansion of (2.22):

3,(1,2) 3,(3,4) 0

a −a = (2.23) This expression can be obtained by giving

(

) (

)

(

)

(

) (

)

(

)

2 2 (1,2) (1,2) (1,2) (3,4) (3,4) (3,4) 4 4 (1,2) (1,2) (3,4) (3,4) / / 2 2 a b a m b m W L R R W L R R R R g R R g θ θ θ θ + + =  ₊ ₊   ₊ ₊      (2.24)

where Wi, Li, and gmi is the width, length, and transconductance of the ith transistor, respectively, and Rθi is the ith short channel equivalent resistance. Under the minimization of the third-order harmonic component, the transconductance of the proposed structure is given by

(

)

(

)

(

)

(

)

(1,2) (1,2) (1,2) , 2 (1,2) (1,2) (3,4) (3,4) (3,4) 2 (3,4) (3,4) 2 2 1 2 2 1 m a m m total a m m b m b m g R R g G R R g g R R g R R g θ θ θ θ  ₊ ₊    =  ₊ ₊     ₊ ₊    −  ₊ ₊    (2.25)

The transconductance decreases because of introducing the double differential pairs and the source degeneration resistors. This implies higher linearity with the tradeoff of higher power consumption.

2.3.2.3 Design methodology

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Figure 2.12. Optimal parameter evaluation for the reduced transconductance.

Figure 2.13. Optimal parameter evaluation for the third-order harmonic component.

structure under optimal transconductance efficiency, a simple approach is used by giving the ratio of parameters to represent the circuit operation. Thus, by giving

(1,2) _(1,2) _(1,2) (3,4) _(3,4) (3,4) 2 a DD cm b W L R R V P Q V W L R R θ θ + = = = + (2.26)

We can find that the ratios of (2.26) would be used to define the transconductance efficiency compared with the single differential pair circuit and the third-order harmonic component of the proposed circuit. In addition, the ratio values should be designed within practical implementation boundary. Bandwidth, noise performance, and matching are also taken into consideration.

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Figure 2.14. Contour plot for the third-order harmonic component under transconductance tuning.

The optimization procedure starts from the reduced transconductance value. We define that less then 30 % of the transconductance should be reduced with respect to that of a single differential pair circuit with the same size and current consumption. From Fig. 2.12, we can find that if the value of Q is set to 3 under large P, we can obtain less than 30 % reduction of the transconductance. Moreover, if the value of 4 for Q is used, less than 25 % reduction of the transconductance would be obtained. Fig. 2.13 shows the third-order distortion component of the proposed design. In order to obtain minimized distortion components, the ratio P is chosen as 9 while Q is set to 3. If Q is set to 4 for less transconductance reduction, P should be set to 16, but such a large ratio would degrade the bandwidth performance owing to the large parasitic capacitance of input transistors. After the optimization procedure, the optimal ratios of the proposed circuit would be given by

9 3

P= Q= (2.27) The optimization procedure concludes that the third-order distortion component is ideally cancelled out with the expected transconductance value, as shown in Fig. 2.14. The linearity performance is actually robust to process variation owing to the flat distribution in Fig. 2.13. Thus, the small reduction of the transconductance value makes high linearity and high speed possible under about 30 % of extra power consumption.

Transconductance tuning would be another important issue in the OTA design. The main idea of the transconductance tuning is to compensate the variation caused

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from fabricated process and temperature. Fig. 2.14 shows the contour plot of the third-order harmonic component under transconductance tuning, resulted from Fig. 2.13. We can find that if Q is changed from 1 to 4 when P is set to 9, it implies more than 300 % of the transconductance tuning range, as shown in Fig. 2.12, and the third-order harmonic component value of less than 0.001 can be guaranteed, as illustrated in Fig. 2.14.

2.3.3 Proposed OTA circuit

2.3.3.1 Implementation of linearization technique

Fig. 2.15 shows the proposed OTA design. Two differential pairs M1 to M2 and M3 to M4 are used in order to cancel the nonlinearity component, as described in the previous section. For continuous transconductance tuning strategy, transistors M5 to M8 operating in the linear region are used to replace the resistors. The equivalent resistance is given by

1

( )

eq G thn

R− =K V −V (2.28) where VG is the gate voltage of the transistor. Therefore, we can obtain the required equivalent resistance by applying the voltage Va and Vb.

1 (5,6)( ) a a thn R− =K V −V (2.29) 1 (7,8)( ) b b thn R− =K V −V (2.30) The linearity can be maintained by proper sizing of the degenerated transistors and the control voltage. In addition, the tuning ability of the proposed circuit can be achieved by adjusting the control voltages Va and Vb. Fig. 2.16 shows the simulated large-signal transconductance of the differential OTA operating in 1.5-V supply voltage. The proposed circuit can be tuned from 360 µS to 470 µS. It can be noticed that the transconductance tuning range is limited by the linear-region operation of transistors M5 to M8. Besides, the speed of the proposed OTA is mainly limited by the parasitic capacitors caused by the current mirror circuits.

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Figure 2.15. Proposed OTA circuit. 2.3.3.2The common-mode stability

The OTA shown in Fig. 2.15 requires a proper common-mode control system due to the pseudo-differential structure [24]. The common-mode control system includes the common-mode feedforward (CMFF) circuit and the common-mode feedback (CMFB) circuit. The CMFF circuit should be used with the CMFB circuit for output common-mode voltage stabilization. Fig. 2.17 shows the circuit of the common-mode control system. For the CMFB circuit, the input transistors MF1 to MF4 perform the tasks of the common-mode detection and reference comparison. If the common-mode voltage of the OTA output signal equals the desired common-mode voltage Vref, then the total current through MF7 will be constant and the common-mode bias voltage VCM is fixed. On the other hand, if the common-mode voltage of the OTA output signal is not the same as Vref, a current will be mirrored by MF9 to change VCM adaptively. Thus, the feedback mechanism adjusts the output common-mode voltage to the desired value.

Furthermore, the input common-mode control circuitry is formed by transistors MF14 to MF18 that constitute the CMFF circuit. The combination of transistors MF14 and MF15 generates a scaled copy of input common-mode currents, which is subtracted at the OTA output stage through the use of current mirror MF17 to MF18. Thus, the input common-mode signal could be suppressed out and only the differential-mode signal appears at the output stage. As the mechanism shown above, it is demonstrated the common-mode control circuit can be implemented to achieve

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Figure 2.16. Simulated transconductance tuning range.

Figure 2.17. The common-mode control system.

excellent stability over the tuning range. Moreover, linearity could be maintained by the robust and stable common-mode control system.

The common-mode rejection (CMR) depends on matching. We can define a matching factor of (1+∆) between the CMFF path and the signal path, where ∆ is the mismatch ratio. We can emulate the CMFB circuit as a small resistor of value 1/gCMFB, and then the common-mode gain of ACM=Gm,total(go-∆×gm(17,18))/(gm(17,18)×gCMFB) at low frequency can be obtained, where Gm,total is obtained from (2.25), gm(17,18) is the transconductance of transistors M17 and M18, and go is the output conductance of the OTA. This is the result of the combined CMFB and CMFF systems. Because gCMFB is

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large, ACM is much less than unity even mismatch problems occur so that high CMR can be obtained.

2.3.4 Non-ideality analysis of the implementation

2.3.4.1 Mismatch

Owing to the non-ideal matching phenomena of MOS transistors, the nonlinearity cancellation is not perfect and second-order harmonic distortion components would still appear at the differential output nodes. For the double differential pair structure, it is assumed that there are mismatches of K(1.2) ± εaK(1,2) for transistors M1 and M2 and K(3,4) ± εbK(3,4) for transistors M3 and M4. Repeating the analysis of (2.22), we can find the second-order distortion component resulted from mismatch is given by

(

)

(

)

(1,2) (3,4) 2 3 3 (1,2) (1,2) (3,4) (3,4) 1 1 a b a m b m K K a R R_θ g R R_θ g ε ε ≈ +  ₊ ₊   ₊ ₊      (2.31)

Therefore, the distortion components caused by transistor mismatch could be minimized by applying large degenerated resistors and gate overdrive voltage. Besides, the current mirrors M9 to M12 would also contribute second-order distortion components under the proposed degenerated structure, and thus large device sizes and small aspect ratios would be designed. From the simulation with 2% transistor mismatch, the highest even-order components remain lower than odd-order components by at least 5 dB. In addition, careful layout was taken while the device match is required. The error output current contributed by transistor mismatch can be divided by the overall transconductance to model an equivalent offset voltage, and it could be removed by applying an offset voltage of input differential signals.

2.3.4.1 Thermal noise

For the high speed circuit, the most significant noise source of a single transistor is the thermal noise rather than the flicker noise. The channel noise can be modeled by a current source connected between the drain and source with a spectral density

2 4

n ms

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where k is the Boltzmann constant, T is the absolute temperature, gms is the source conductance, and the device noise parameter δ depends on the bias condition [25]. Using the thermal noise model, the total output-referred noise spectral density of the double differential pairs with degeneration structure is derived as

2 2 , (9,10) (1,2) (1,2) 2 2 (1,2) (3,4) (1,2) (3,4) 2 2 (3,4) (11,12) (17,18) (3,4) (9,10) 1 8 1 1 1 1 8 1 n out s m s m m a m l a s m m a m b m m l b s m m b m I kT g g g R g R g g R g R g g R kT g g R g δ δ δ δ δ δ  _ _  ≈ + _ _ +  _ _      + _ _ + _ _ + +           + _  _{ } _ + +    _  (2.33)

where δs and δl would be the noise parameter at saturation and linear regions, respectively. The input-referred noise spectral density could be calculated by dividing the output-referred noise spectral density by the overall OTA transconductance. From the noise analysis, large aspect ratios of input transistors and small aspect ratios of load transistors should be designed. The input-referred noise of the proposed circuit is higher than the single differential pair circuit owing to the fact that the noise contribution is the combination of two input differential pairs. Moreover, the degenerated MOS resistors contribute additional noise sources to the proposed circuit.

2.3.5 Experimental results

The proposed OTA has been fabricated with TSMC 180 nm Deep N-WELL CMOS process. It has been measured to verify its operation and to evaluate the linear V-I characteristics. A micrograph of the linear OTA is depicted in Fig. 2.18 and the occupied area is 15.1×10-3 mm2. A supply voltage of 1.5-V was employed in the measurements and the nominal static power consumption of the OTA is 9.5 mW. The required supply voltage for the circuit is VGS+2VDS(saturation region), and 1.5-V is sufficient for this circuit to operate under 180 nm CMOS process.

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Figure 2.18. Die microphotograph.

Figure 2.19. Measured two tone inter-modulation distortion.

Figure 2.20. Measured two tone inter-modulation distortion with respect to input signal frequency.

For the measurement setup, the output signal of the signal generator was past through a low-pass filter for the spectral purity of the input signal. The transformers

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Table 2.1. Comparison with previously reported works. Reference 2005 TCAS-I [19] 2005 TCAS-I [22] 2003 JSSC [26] 2006 TCAS-II [27] 2004 TCAS-II [28] 2005 JSSC [29] This work Technology 0.8 µm CMOS 0.8 µm CMOS 0.5 µm CMOS 0.18 µm CMOS *Simulati on 0.35 µm CMOS 0.5 µm CMOS 0.18 µm CMOS Tranconduc tance Value 0.08µS 266µS 1065µS 20µS 100µS 100µS 470µS Linearity -40dB THD at 100Hz -43dB HD3 at 1kHz -43dB HD3 at 30MHz -65dB HD3 at 1MHz -65dB IM3 at 20MHz -66.5dB THD at 100kHz -60dB IM3 at 40MHz Input swing range 1.1 Vpp 0.4 Vpp 0.9Vpp 0.6Vpp 1.3Vpp 2Vpp 0.9Vpp Supply Voltage 1.5V 2V 3.3V 1.8V 3.3V 2.6V 1.5V Power consumptio n 1µW 150µW 10.7mW 145µW 10.5mW 1.7mW 9.5mW Figure of merit (FOM) 29 50 84 82 86 74 93 Input-referr ed noise spectral density - - 9.8nV/√ Hz - 75nV/√ Hz - 23nV/√ Hz

were used before and after the input and output terminals for single-to-differential and differential-to-single conversion for the differential circuit. The output signal was measured with a spectrum analyzer. The third-order inter-modulation distortion measured with two sinusoidal tones of 0.9 Vpp amplitude is shown in Fig. 2.19. The IM3 is shown to be about -60 dB at the speed of 40 MHz. Fig. 2.20 shows the nonlinearity behavior with respect to the frequency under the same input swing range. At low frequencies, the IM3 of -75 dB could be obtained. Moreover, IM3 less than

高效能互補金屬氧化層半導體式轉導放大器與濾波器於無線通訊與有線系統之應用

高效能互補金屬氧化層半導體式轉導放大器與濾

波器於無線通訊與有線系統之應用

High Performance CMOS Transconductors and Gm-C

Filters for Wireless Communications and Wireline

Systems

研究生：羅天佑

Student: Tien-Yu Lo

指導教授：洪崇智 博士

Advisor: Dr. Chung-Chih Hung

國立交通大學

電信工程學系

博士論文

A Dissertation

Submitted to Institute of Communication Engineering

College of Electrical and Computer Engineering

National Chiao Tung University

in Partial Fulfillment of the Requirements

for the Degree of Doctor of Philosophy

in

Communication Engineering

Hsinchu, Taiwan

High Performance CMOS Transconductors and Gm-C

Filters for Wireless Communications and Wireline

Systems

A Dissertation

Presented to

The Academic Faculty

By

Tien-Yu Lo

In Partial Fulfillment

of the Requirement for the Degree of

Doctor of Philosophy in Communication Engineering

Department of Communication Engineering

National Chiao-Tung University

推 薦 函

高效能互補金屬氧化層半導體式轉導放大器與

濾波器於無線通訊與有線系統之應用

研究生：羅天佑

指導教授：洪崇智 博士

國立交通大學

電信工程學系

摘要

ABSTRACT

Acknowledgments

Contents

List of Tables

List of Figures

Chapter 1

Motivation

Chapter 2

Transconductor

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指導教授：洪崇智博士

推薦函

指導教授：洪崇智博士

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